Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PTP 1588 clock for Freescale QorIQ 1588 timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2010 OMICRON electronics GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/fsl/ptp_qoriq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Register access functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* Caller must hold ptp_qoriq->lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static u64 tmr_cnt_read(struct ptp_qoriq *ptp_qoriq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	lo = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	hi = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	ns = ((u64) hi) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	ns |= lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Caller must hold ptp_qoriq->lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static void tmr_cnt_write(struct ptp_qoriq *ptp_qoriq, u64 ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u32 hi = ns >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32 lo = ns & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_l, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_h, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* Caller must hold ptp_qoriq->lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void set_alarm(struct ptp_qoriq *ptp_qoriq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ns = tmr_cnt_read(ptp_qoriq) + 1500000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ns -= ptp_qoriq->tclk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	hi = ns >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	lo = ns & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	ptp_qoriq->write(&regs->alarm_regs->tmr_alarm1_l, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ptp_qoriq->write(&regs->alarm_regs->tmr_alarm1_h, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Caller must hold ptp_qoriq->lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void set_fipers(struct ptp_qoriq *ptp_qoriq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	set_alarm(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	ptp_qoriq->write(&regs->fiper_regs->tmr_fiper1, ptp_qoriq->tmr_fiper1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	ptp_qoriq->write(&regs->fiper_regs->tmr_fiper2, ptp_qoriq->tmr_fiper2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if (ptp_qoriq->fiper3_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		ptp_qoriq->write(&regs->fiper_regs->tmr_fiper3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 				 ptp_qoriq->tmr_fiper3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) int extts_clean_up(struct ptp_qoriq *ptp_qoriq, int index, bool update_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct ptp_clock_event event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	void __iomem *reg_etts_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	void __iomem *reg_etts_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 valid, lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		valid = ETS1_VLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		reg_etts_l = &regs->etts_regs->tmr_etts1_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		reg_etts_h = &regs->etts_regs->tmr_etts1_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		valid = ETS2_VLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		reg_etts_l = &regs->etts_regs->tmr_etts2_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		reg_etts_h = &regs->etts_regs->tmr_etts2_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	event.type = PTP_CLOCK_EXTTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	event.index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (ptp_qoriq->extts_fifo_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		if (!(ptp_qoriq->read(&regs->ctrl_regs->tmr_stat) & valid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		lo = ptp_qoriq->read(reg_etts_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		hi = ptp_qoriq->read(reg_etts_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		if (update_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			event.timestamp = ((u64) hi) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			event.timestamp |= lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			ptp_clock_event(ptp_qoriq->clock, &event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		if (!ptp_qoriq->extts_fifo_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	} while (ptp_qoriq->read(&regs->ctrl_regs->tmr_stat) & valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) EXPORT_SYMBOL_GPL(extts_clean_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * Interrupt service routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) irqreturn_t ptp_qoriq_isr(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct ptp_qoriq *ptp_qoriq = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct ptp_clock_event event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u32 ack = 0, mask, val, irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	spin_lock(&ptp_qoriq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	val = ptp_qoriq->read(&regs->ctrl_regs->tmr_tevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	mask = ptp_qoriq->read(&regs->ctrl_regs->tmr_temask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	spin_unlock(&ptp_qoriq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	irqs = val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (irqs & ETS1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		ack |= ETS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		extts_clean_up(ptp_qoriq, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (irqs & ETS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		ack |= ETS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		extts_clean_up(ptp_qoriq, 1, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (irqs & PP1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		ack |= PP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		event.type = PTP_CLOCK_PPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		ptp_clock_event(ptp_qoriq->clock, &event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (ack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		ptp_qoriq->write(&regs->ctrl_regs->tmr_tevent, ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) EXPORT_SYMBOL_GPL(ptp_qoriq_isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * PTP clock operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u64 adj, diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u32 tmr_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int neg_adj = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (scaled_ppm < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		neg_adj = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		scaled_ppm = -scaled_ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	tmr_add = ptp_qoriq->tmr_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	adj = tmr_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * Calculate diff and round() to the nearest integer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * diff = adj * (ppb / 1000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 *      = adj * scaled_ppm / 65536000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	diff = mul_u64_u64_div_u64(adj, scaled_ppm, 32768000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	diff = DIV64_U64_ROUND_UP(diff, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_add, tmr_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) EXPORT_SYMBOL_GPL(ptp_qoriq_adjfine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	s64 now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	spin_lock_irqsave(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	now = tmr_cnt_read(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	now += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	tmr_cnt_write(ptp_qoriq, now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	set_fipers(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) EXPORT_SYMBOL_GPL(ptp_qoriq_adjtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ptp_qoriq_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	spin_lock_irqsave(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ns = tmr_cnt_read(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	*ts = ns_to_timespec64(ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) EXPORT_SYMBOL_GPL(ptp_qoriq_gettime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int ptp_qoriq_settime(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		      const struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ns = timespec64_to_ns(ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	spin_lock_irqsave(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	tmr_cnt_write(ptp_qoriq, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	set_fipers(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) EXPORT_SYMBOL_GPL(ptp_qoriq_settime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ptp_qoriq_enable(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		     struct ptp_clock_request *rq, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct ptp_qoriq *ptp_qoriq = container_of(ptp, struct ptp_qoriq, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	u32 bit, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	switch (rq->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	case PTP_CLK_REQ_EXTTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		switch (rq->extts.index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			bit = ETS1EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			bit = ETS2EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			extts_clean_up(ptp_qoriq, rq->extts.index, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	case PTP_CLK_REQ_PPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		bit = PP1EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	spin_lock_irqsave(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	mask = ptp_qoriq->read(&regs->ctrl_regs->tmr_temask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		mask |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		ptp_qoriq->write(&regs->ctrl_regs->tmr_tevent, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		mask &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_temask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) EXPORT_SYMBOL_GPL(ptp_qoriq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct ptp_clock_info ptp_qoriq_caps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.name		= "qoriq ptp clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.max_adj	= 512000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.n_alarm	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.n_ext_ts	= N_EXT_TS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.n_per_out	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.n_pins		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.pps		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.adjfine	= ptp_qoriq_adjfine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.adjtime	= ptp_qoriq_adjtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.gettime64	= ptp_qoriq_gettime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.settime64	= ptp_qoriq_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.enable		= ptp_qoriq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)  * ptp_qoriq_nominal_freq - calculate nominal frequency according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)  *			    reference clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)  * @clk_src: reference clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  * The nominal frequency is the desired clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  * It should be less than the reference clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  * It should be a factor of 1000MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)  * Return the nominal frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static u32 ptp_qoriq_nominal_freq(u32 clk_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	u32 remainder = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	clk_src /= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	remainder = clk_src % 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (remainder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		clk_src -= remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		clk_src += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		clk_src -= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	} while (1000 % clk_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return clk_src * 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  * ptp_qoriq_auto_config - calculate a set of default configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  * @ptp_qoriq: pointer to ptp_qoriq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  * @node: pointer to device_node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)  * If below dts properties are not provided, this function will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)  * called to calculate a set of default configurations for them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)  *   "fsl,tclk-period"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)  *   "fsl,tmr-prsc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)  *   "fsl,tmr-add"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)  *   "fsl,tmr-fiper1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)  *   "fsl,tmr-fiper2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)  *   "fsl,tmr-fiper3" (required only for DPAA2 and ENETC hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  *   "fsl,max-adj"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)  * Return 0 if success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int ptp_qoriq_auto_config(struct ptp_qoriq *ptp_qoriq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 				 struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	u64 freq_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	u64 max_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	u32 nominal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	u32 remainder = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	u32 clk_src = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	ptp_qoriq->cksel = DEFAULT_CKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	clk = of_clk_get(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		clk_src = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (clk_src <= 100000000UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		pr_err("error reference clock value, or lower than 100MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	nominal_freq = ptp_qoriq_nominal_freq(clk_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (!nominal_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	ptp_qoriq->tclk_period = 1000000000UL / nominal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	ptp_qoriq->tmr_prsc = DEFAULT_TMR_PRSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	/* Calculate initial frequency compensation value for TMR_ADD register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	 * freq_comp = ceil(2^32 / freq_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	 * freq_ratio = reference_clock_freq / nominal_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	freq_comp = ((u64)1 << 32) * nominal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	freq_comp = div_u64_rem(freq_comp, clk_src, &remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if (remainder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		freq_comp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	ptp_qoriq->tmr_add = freq_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	ptp_qoriq->tmr_fiper1 = DEFAULT_FIPER1_PERIOD - ptp_qoriq->tclk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	ptp_qoriq->tmr_fiper2 = DEFAULT_FIPER2_PERIOD - ptp_qoriq->tclk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	ptp_qoriq->tmr_fiper3 = DEFAULT_FIPER3_PERIOD - ptp_qoriq->tclk_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	/* max_adj = 1000000000 * (freq_ratio - 1.0) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	 * freq_ratio = reference_clock_freq / nominal_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	max_adj = 1000000000ULL * (clk_src - nominal_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	max_adj = div_u64(max_adj, nominal_freq) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	ptp_qoriq->caps.max_adj = max_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int ptp_qoriq_init(struct ptp_qoriq *ptp_qoriq, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		   const struct ptp_clock_info *caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	struct device_node *node = ptp_qoriq->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	struct ptp_qoriq_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	struct timespec64 now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	u32 tmr_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	ptp_qoriq->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	ptp_qoriq->caps = *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (of_property_read_u32(node, "fsl,cksel", &ptp_qoriq->cksel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		ptp_qoriq->cksel = DEFAULT_CKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	if (of_property_read_bool(node, "fsl,extts-fifo"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		ptp_qoriq->extts_fifo_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		ptp_qoriq->extts_fifo_support = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	if (of_device_is_compatible(node, "fsl,dpaa2-ptp") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	    of_device_is_compatible(node, "fsl,enetc-ptp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		ptp_qoriq->fiper3_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	if (of_property_read_u32(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 				 "fsl,tclk-period", &ptp_qoriq->tclk_period) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	    of_property_read_u32(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 				 "fsl,tmr-prsc", &ptp_qoriq->tmr_prsc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	    of_property_read_u32(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 				 "fsl,tmr-add", &ptp_qoriq->tmr_add) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	    of_property_read_u32(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 				 "fsl,tmr-fiper1", &ptp_qoriq->tmr_fiper1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	    of_property_read_u32(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 				 "fsl,tmr-fiper2", &ptp_qoriq->tmr_fiper2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	    of_property_read_u32(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 				 "fsl,max-adj", &ptp_qoriq->caps.max_adj) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	    (ptp_qoriq->fiper3_support &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	     of_property_read_u32(node, "fsl,tmr-fiper3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 				  &ptp_qoriq->tmr_fiper3))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		pr_warn("device tree node missing required elements, try automatic configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		if (ptp_qoriq_auto_config(ptp_qoriq, node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	if (of_property_read_bool(node, "little-endian")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		ptp_qoriq->read = qoriq_read_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		ptp_qoriq->write = qoriq_write_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		ptp_qoriq->read = qoriq_read_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		ptp_qoriq->write = qoriq_write_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	/* The eTSEC uses differnt memory map with DPAA/ENETC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	if (of_device_is_compatible(node, "fsl,etsec-ptp")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		ptp_qoriq->regs.ctrl_regs = base + ETSEC_CTRL_REGS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		ptp_qoriq->regs.alarm_regs = base + ETSEC_ALARM_REGS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		ptp_qoriq->regs.fiper_regs = base + ETSEC_FIPER_REGS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		ptp_qoriq->regs.etts_regs = base + ETSEC_ETTS_REGS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 		ptp_qoriq->regs.ctrl_regs = base + CTRL_REGS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		ptp_qoriq->regs.alarm_regs = base + ALARM_REGS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		ptp_qoriq->regs.fiper_regs = base + FIPER_REGS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		ptp_qoriq->regs.etts_regs = base + ETTS_REGS_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	spin_lock_init(&ptp_qoriq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	ktime_get_real_ts64(&now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	ptp_qoriq_settime(&ptp_qoriq->caps, &now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	tmr_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	  (ptp_qoriq->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	  (ptp_qoriq->cksel & CKSEL_MASK) << CKSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	spin_lock_irqsave(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_ctrl, tmr_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_add, ptp_qoriq->tmr_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_prsc, ptp_qoriq->tmr_prsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	ptp_qoriq->write(&regs->fiper_regs->tmr_fiper1, ptp_qoriq->tmr_fiper1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	ptp_qoriq->write(&regs->fiper_regs->tmr_fiper2, ptp_qoriq->tmr_fiper2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	if (ptp_qoriq->fiper3_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		ptp_qoriq->write(&regs->fiper_regs->tmr_fiper3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 				 ptp_qoriq->tmr_fiper3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	set_alarm(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 			 tmr_ctrl|FIPERST|RTPE|TE|FRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	spin_unlock_irqrestore(&ptp_qoriq->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	ptp_qoriq->clock = ptp_clock_register(&ptp_qoriq->caps, ptp_qoriq->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	if (IS_ERR(ptp_qoriq->clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		return PTR_ERR(ptp_qoriq->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	ptp_qoriq->phc_index = ptp_clock_index(ptp_qoriq->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	ptp_qoriq_create_debugfs(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) EXPORT_SYMBOL_GPL(ptp_qoriq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) void ptp_qoriq_free(struct ptp_qoriq *ptp_qoriq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	struct ptp_qoriq_registers *regs = &ptp_qoriq->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_temask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	ptp_qoriq->write(&regs->ctrl_regs->tmr_ctrl,   0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	ptp_qoriq_remove_debugfs(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	ptp_clock_unregister(ptp_qoriq->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	iounmap(ptp_qoriq->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	free_irq(ptp_qoriq->irq, ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) EXPORT_SYMBOL_GPL(ptp_qoriq_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int ptp_qoriq_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	struct ptp_qoriq *ptp_qoriq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	ptp_qoriq = kzalloc(sizeof(*ptp_qoriq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	if (!ptp_qoriq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		goto no_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	ptp_qoriq->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	ptp_qoriq->irq = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	if (ptp_qoriq->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		pr_err("irq not in device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		goto no_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	if (request_irq(ptp_qoriq->irq, ptp_qoriq_isr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 			DRIVER, ptp_qoriq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		pr_err("request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		goto no_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	ptp_qoriq->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	if (!ptp_qoriq->rsrc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 		pr_err("no resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		goto no_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	if (request_resource(&iomem_resource, ptp_qoriq->rsrc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 		pr_err("resource busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		goto no_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	base = ioremap(ptp_qoriq->rsrc->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 		       resource_size(ptp_qoriq->rsrc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 		pr_err("ioremap ptp registers failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 		goto no_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	err = ptp_qoriq_init(ptp_qoriq, base, &ptp_qoriq_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 		goto no_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	platform_set_drvdata(dev, ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) no_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	iounmap(ptp_qoriq->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) no_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	release_resource(ptp_qoriq->rsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) no_resource:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	free_irq(ptp_qoriq->irq, ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) no_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	kfree(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) no_memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int ptp_qoriq_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	struct ptp_qoriq *ptp_qoriq = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	ptp_qoriq_free(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	release_resource(ptp_qoriq->rsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	kfree(ptp_qoriq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const struct of_device_id match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	{ .compatible = "fsl,etsec-ptp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	{ .compatible = "fsl,fman-ptp-timer" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MODULE_DEVICE_TABLE(of, match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct platform_driver ptp_qoriq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 		.name		= "ptp_qoriq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 		.of_match_table	= match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	.probe       = ptp_qoriq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	.remove      = ptp_qoriq_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) module_platform_driver(ptp_qoriq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MODULE_DESCRIPTION("PTP clock for Freescale QorIQ 1588 timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MODULE_LICENSE("GPL");