^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PTP 1588 clock using the EG20T PCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 OMICRON electronics GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This code was derived from the IXP46X driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ptp_clock_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STATION_ADDR_LEN 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_DEVICE_ID_PCH_1588 0x8819
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IO_MEM_BAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DEFAULT_ADDEND 0xA0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TICKS_NS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define N_EXT_TS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum pch_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PCH_SUCCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PCH_INVALIDPARAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PCH_NOTIMESTAMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PCH_INTERRUPTMODEINUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PCH_FAILED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PCH_UNSUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * struct pch_ts_regs - IEEE 1588 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct pch_ts_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 addend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 accum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 ts_compare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 rsystime_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 rsystime_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 systime_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 systime_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 trgt_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 trgt_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 asms_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 asms_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 amms_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 amms_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 ch_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 ch_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 tx_snap_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 tx_snap_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 rx_snap_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 rx_snap_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 src_uuid_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 src_uuid_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 can_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 can_snap_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 can_snap_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 ts_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 ts_st[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 reserve1[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 stl_max_set_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 stl_max_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 reserve2[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 srst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCH_TSC_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCH_TSC_TTM_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCH_TSC_ASMS_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCH_TSC_AMMS_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCH_TSC_PPSM_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCH_TSE_TTIPEND (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCH_TSE_SNS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCH_TSE_SNM (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCH_TSE_PPS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCH_CC_MM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCH_CC_TA (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCH_CC_MODE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCH_CC_MODE_MASK 0x001F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCH_CC_VERSION (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PCH_CE_TXS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCH_CE_RXS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCH_CE_OVR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCH_CE_VAL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCH_ECS_ETH (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCH_ECS_CAN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCH_STATION_BYTES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCH_IEEE1588_ETH (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCH_IEEE1588_CAN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * struct pch_dev - Driver private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct pch_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pch_ts_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct ptp_clock *ptp_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ptp_clock_info caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int exts0_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int exts1_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) spinlock_t register_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * struct pch_params - 1588 module parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct pch_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 station[STATION_ADDR_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* structure to hold the module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct pch_params pch_param = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "00:00:00:00:00:00"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Register access functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline void pch_eth_enable_set(struct pch_dev *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* SET the eth_enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) iowrite32(val, (&chip->regs->ts_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) lo = ioread32(®s->systime_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) hi = ioread32(®s->systime_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ns = ((u64) hi) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ns |= lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ns <<= TICKS_NS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 hi, lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ns >>= TICKS_NS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) hi = ns >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) lo = ns & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) iowrite32(lo, ®s->systime_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) iowrite32(hi, ®s->systime_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline void pch_block_reset(struct pch_dev *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Reset Hardware Assist block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) iowrite32(val, (&chip->regs->control));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val = val & ~PCH_TSC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) iowrite32(val, (&chip->regs->control));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 pch_ch_control_read(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val = ioread32(&chip->regs->ch_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) EXPORT_SYMBOL(pch_ch_control_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void pch_ch_control_write(struct pci_dev *pdev, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) iowrite32(val, (&chip->regs->ch_control));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) EXPORT_SYMBOL(pch_ch_control_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 pch_ch_event_read(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) val = ioread32(&chip->regs->ch_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EXPORT_SYMBOL(pch_ch_event_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void pch_ch_event_write(struct pci_dev *pdev, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) iowrite32(val, (&chip->regs->ch_event));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) EXPORT_SYMBOL(pch_ch_event_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) val = ioread32(&chip->regs->src_uuid_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) EXPORT_SYMBOL(pch_src_uuid_lo_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val = ioread32(&chip->regs->src_uuid_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) EXPORT_SYMBOL(pch_src_uuid_hi_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u64 pch_rx_snap_read(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) lo = ioread32(&chip->regs->rx_snap_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) hi = ioread32(&chip->regs->rx_snap_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ns = ((u64) hi) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ns |= lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ns <<= TICKS_NS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) EXPORT_SYMBOL(pch_rx_snap_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u64 pch_tx_snap_read(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) lo = ioread32(&chip->regs->tx_snap_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) hi = ioread32(&chip->regs->tx_snap_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ns = ((u64) hi) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ns |= lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ns <<= TICKS_NS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) EXPORT_SYMBOL(pch_tx_snap_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* This function enables all 64 bits in system time registers [high & low].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) This is a work-around for non continuous value in the SystemTime Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void pch_set_system_time_count(struct pch_dev *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) iowrite32(0x01, &chip->regs->stl_max_set_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) iowrite32(0x00, &chip->regs->stl_max_set_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void pch_reset(struct pch_dev *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Reset Hardware Assist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pch_block_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* enable all 32 bits in system time registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pch_set_system_time_count(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * pch_set_station_address() - This API sets the station address used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * IEEE 1588 hardware when looking at PTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * traffic on the ethernet interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @addr: dress which contain the column separated address to be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int pch_set_station_address(u8 *addr, struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) s32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Verify the parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if ((chip->regs == NULL) || addr == (u8 *)NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "invalid params returning PCH_INVALIDPARAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return PCH_INVALIDPARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* For all station address bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) for (i = 0; i < PCH_STATION_BYTES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) s32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tmp = hex_to_bin(addr[i * 3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (tmp < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "invalid params returning PCH_INVALIDPARAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return PCH_INVALIDPARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) val = tmp * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tmp = hex_to_bin(addr[(i * 3) + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (tmp < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "invalid params returning PCH_INVALIDPARAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return PCH_INVALIDPARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) val += tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Expects ':' separated addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if ((i < 5) && (addr[(i * 3) + 2] != ':')) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "invalid params returning PCH_INVALIDPARAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return PCH_INVALIDPARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Ideally we should set the address only after validating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) entire string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(&pdev->dev, "invoking pch_station_set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) iowrite32(val, &chip->regs->ts_st[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) EXPORT_SYMBOL(pch_set_station_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Interrupt service routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static irqreturn_t isr(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct pch_dev *pch_dev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct pch_ts_regs __iomem *regs = pch_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct ptp_clock_event event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 ack = 0, lo, hi, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) val = ioread32(®s->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (val & PCH_TSE_SNS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ack |= PCH_TSE_SNS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (pch_dev->exts0_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) hi = ioread32(®s->asms_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) lo = ioread32(®s->asms_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) event.type = PTP_CLOCK_EXTTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) event.index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) event.timestamp = ((u64) hi) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) event.timestamp |= lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) event.timestamp <<= TICKS_NS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ptp_clock_event(pch_dev->ptp_clock, &event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (val & PCH_TSE_SNM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ack |= PCH_TSE_SNM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (pch_dev->exts1_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) hi = ioread32(®s->amms_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) lo = ioread32(®s->amms_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) event.type = PTP_CLOCK_EXTTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) event.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) event.timestamp = ((u64) hi) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) event.timestamp |= lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) event.timestamp <<= TICKS_NS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ptp_clock_event(pch_dev->ptp_clock, &event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (val & PCH_TSE_TTIPEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) iowrite32(ack, ®s->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * PTP clock operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u64 adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 diff, addend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int neg_adj = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct pch_ts_regs __iomem *regs = pch_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ppb < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) neg_adj = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ppb = -ppb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) addend = DEFAULT_ADDEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) adj = addend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) adj *= ppb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) diff = div_u64(adj, 1000000000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) addend = neg_adj ? addend - diff : addend + diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) iowrite32(addend, ®s->addend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) s64 now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct pch_ts_regs __iomem *regs = pch_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) spin_lock_irqsave(&pch_dev->register_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) now = pch_systime_read(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) now += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pch_systime_write(regs, now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spin_unlock_irqrestore(&pch_dev->register_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct pch_ts_regs __iomem *regs = pch_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spin_lock_irqsave(&pch_dev->register_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ns = pch_systime_read(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) spin_unlock_irqrestore(&pch_dev->register_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *ts = ns_to_timespec64(ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int ptp_pch_settime(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) const struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u64 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct pch_ts_regs __iomem *regs = pch_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ns = timespec64_to_ns(ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) spin_lock_irqsave(&pch_dev->register_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pch_systime_write(regs, ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) spin_unlock_irqrestore(&pch_dev->register_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int ptp_pch_enable(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct ptp_clock_request *rq, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) switch (rq->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case PTP_CLK_REQ_EXTTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) switch (rq->extts.index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pch_dev->exts0_enabled = on ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pch_dev->exts1_enabled = on ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct ptp_clock_info ptp_pch_caps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .name = "PCH timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .max_adj = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .n_ext_ts = N_EXT_TS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .n_pins = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .pps = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .adjfreq = ptp_pch_adjfreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .adjtime = ptp_pch_adjtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .gettime64 = ptp_pch_gettime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .settime64 = ptp_pch_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .enable = ptp_pch_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define pch_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define pch_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static void pch_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct pch_dev *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ptp_clock_unregister(chip->ptp_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* free the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (pdev->irq != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) free_irq(pdev->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* unmap the virtual IO memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (chip->regs != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) iounmap(chip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) chip->regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* release the reserved IO memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (chip->mem_base != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) release_mem_region(chip->mem_base, chip->mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) chip->mem_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_info(&pdev->dev, "complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static s32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct pch_dev *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* enable the 1588 pci device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(&pdev->dev, "could not enable the pci device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) goto err_pci_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!chip->mem_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(&pdev->dev, "could not locate IO memory address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto err_pci_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* retrieve the available length of the IO memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* allocate the memory for the device registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "could not allocate register memory space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) goto err_req_mem_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* get the virtual address to the 1588 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) chip->regs = ioremap(chip->mem_base, chip->mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (!chip->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(&pdev->dev, "Could not get virtual address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto err_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) chip->caps = ptp_pch_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (IS_ERR(chip->ptp_clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = PTR_ERR(chip->ptp_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) goto err_ptp_clock_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) spin_lock_init(&chip->register_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) goto err_req_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* indicate success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) chip->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) chip->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pci_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) spin_lock_irqsave(&chip->register_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* reset the ieee1588 h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pch_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) iowrite32(DEFAULT_ADDEND, &chip->regs->addend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) iowrite32(1, &chip->regs->trgt_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) iowrite32(0, &chip->regs->trgt_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) iowrite32(PCH_TSE_TTIPEND, &chip->regs->event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) pch_eth_enable_set(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (pch_set_station_address(pch_param.station, pdev) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "Invalid station address parameter\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "Module loaded but station address not set correctly\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) spin_unlock_irqrestore(&chip->register_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) err_req_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ptp_clock_unregister(chip->ptp_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) err_ptp_clock_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) iounmap(chip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) chip->regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) err_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) release_mem_region(chip->mem_base, chip->mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) err_req_mem_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) chip->mem_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) err_pci_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) err_pci_en:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct pci_device_id pch_ieee1588_pcidev_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .vendor = PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .device = PCI_DEVICE_ID_PCH_1588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MODULE_DEVICE_TABLE(pci, pch_ieee1588_pcidev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static SIMPLE_DEV_PM_OPS(pch_pm_ops, pch_suspend, pch_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static struct pci_driver pch_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .id_table = pch_ieee1588_pcidev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .probe = pch_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .remove = pch_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .driver.pm = &pch_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void __exit ptp_pch_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pci_unregister_driver(&pch_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static s32 __init ptp_pch_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* register the driver with the pci core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = pci_register_driver(&pch_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) module_init(ptp_pch_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) module_exit(ptp_pch_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) module_param_string(station,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pch_param.station, sizeof(pch_param.station), 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MODULE_PARM_DESC(station,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "IEEE 1588 station address to use - colon separated hex values");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MODULE_DESCRIPTION("PTP clock using the EG20T timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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