^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PTP hardware clock driver for the IDT 82P33XXX family of clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef PTP_IDT82P33_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define PTP_IDT82P33_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Register Map - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PAGE_NUM (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define _ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define _PAGE(addr) (((addr) >> 0x7) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define _OFFSET(addr) ((addr) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DPLL1_TOD_CNFG 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DPLL2_TOD_CNFG 0x1B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DPLL1_TOD_STS 0x10B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DPLL2_TOD_STS 0x18B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DPLL1_TOD_TRIGGER 0x115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DPLL2_TOD_TRIGGER 0x195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DPLL1_OPERATING_MODE_CNFG 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DPLL2_OPERATING_MODE_CNFG 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DPLL1_PHASE_OFFSET_CNFG 0x143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DPLL2_PHASE_OFFSET_CNFG 0x1C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DPLL1_SYNC_EDGE_CNFG 0X140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DPLL2_SYNC_EDGE_CNFG 0X1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DPLL1_INPUT_MODE_CNFG 0X116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DPLL2_INPUT_MODE_CNFG 0X196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OUT_MUX_CNFG(outn) _ADDR(0x6, (0xC * (outn)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PAGE_ADDR 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Register Map end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Register definitions - AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SYNC_TOD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PH_OFFSET_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SQUELCH_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Bit definitions for the DPLL_MODE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLL_MODE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLL_MODE_MASK (0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum pll_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PLL_MODE_MIN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PLL_MODE_FORCE_FREERUN = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PLL_MODE_FORCE_HOLDOVER = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PLL_MODE_FORCE_LOCKED = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PLL_MODE_FORCE_PRE_LOCKED2 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PLL_MODE_FORCE_PRE_LOCKED = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PLL_MODE_FORCE_LOST_PHASE = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PLL_MODE_DCO = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PLL_MODE_WPH = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PLL_MODE_MAX = PLL_MODE_WPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum hw_tod_trig_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) HW_TOD_TRIG_SEL_MIN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) HW_TOD_TRIG_SEL_SYNC_SEL = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) HW_TOD_TRIG_SEL_IN12 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) HW_TOD_TRIG_SEL_IN13 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) HW_TOD_TRIG_SEL_IN14 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) HW_TOD_TRIG_SEL_TOD_PPS = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Register bit definitions end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FW_FILENAME "idt82p33xxx.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAX_PHC_PLL (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TOD_BYTE_COUNT (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MAX_MEASURMENT_COUNT (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SNAP_THRESHOLD_NS (150000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SYNC_TOD_TIMEOUT_SEC (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PLLMASK_ADDR_HI 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PLLMASK_ADDR_LO 0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PLL0_OUTMASK_ADDR_HI 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PLL0_OUTMASK_ADDR_LO 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PLL1_OUTMASK_ADDR_HI 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PLL1_OUTMASK_ADDR_LO 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PLL2_OUTMASK_ADDR_HI 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PLL2_OUTMASK_ADDR_LO 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PLL3_OUTMASK_ADDR_HI 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PLL3_OUTMASK_ADDR_LO 0xB6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DEFAULT_PLL_MASK (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DEFAULT_OUTPUT_MASK_PLL0 (0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* PTP Hardware Clock interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct idt82p33_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct ptp_clock_info caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct ptp_clock *ptp_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct idt82p33 *idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) enum pll_mode pll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* task to turn off SYNC_TOD bit after pps sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct delayed_work sync_tod_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bool sync_tod_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) s32 current_freq_ppb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u16 dpll_tod_cnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u16 dpll_tod_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 dpll_tod_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 dpll_mode_cnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u16 dpll_freq_cnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 dpll_phase_cnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u16 dpll_sync_cnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 dpll_input_mode_cnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct idt82p33 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct idt82p33_channel channel[MAX_PHC_PLL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 page_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 pll_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ktime_t start_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int calculate_overhead_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) s64 tod_write_overhead_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Protects I2C read/modify/write registers from concurrent access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct mutex reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* firmware interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct idt82p33_fwrc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 hiaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 loaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @brief Maximum absolute value for write phase offset in femtoseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define WRITE_PHASE_OFFSET_LIMIT (20000052084ll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /** @brief Phase offset resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * DPLL phase offset = 10^15 fs / ( System Clock * 2^13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * = 10^15 fs / ( 1638400000 * 2^23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * = 74.5058059692382 fs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IDT_T0DPLL_PHASE_RESOL 74506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #endif /* PTP_IDT82P33_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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