^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2018 Integrated Device Technology, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define pr_fmt(fmt) "IDT_82p33xxx: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ptp_clock_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/timekeeping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "ptp_private.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "ptp_idt82p33.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MODULE_DESCRIPTION("Driver for IDT 82p33xxx clock devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MODULE_VERSION("1.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Module Parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static u32 sync_tod_timeout = SYNC_TOD_TIMEOUT_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) module_param(sync_tod_timeout, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_PARM_DESC(sync_tod_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "duration in second to keep SYNC_TOD on (set to 0 to keep it always on)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param(phase_snap_threshold, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_PARM_DESC(phase_snap_threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "threshold (150000ns by default) below which adjtime would ignore");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 buf[TOD_BYTE_COUNT])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) time64_t sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) s32 nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) nsec = buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) nsec <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) nsec |= buf[2 - i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) sec = buf[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) sec <<= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) sec |= buf[8 - i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ts->tv_sec = sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ts->tv_nsec = nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 buf[TOD_BYTE_COUNT])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) time64_t sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) s32 nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) nsec = ts->tv_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) sec = ts->tv_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) buf[i] = nsec & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) nsec >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) for (i = 4; i < TOD_BYTE_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) buf[i] = sec & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sec >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int idt82p33_xfer(struct idt82p33 *idt82p33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned char regaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct i2c_client *client = idt82p33->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) msg[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) msg[0].buf = ®addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) msg[1].flags = write ? 0 : I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) msg[1].len = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) cnt = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (cnt < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_err(&client->dev, "i2c_transfer returned %d\n", cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else if (cnt != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "i2c_transfer sent only %d of %d messages\n", cnt, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int idt82p33_page_offset(struct idt82p33 *idt82p33, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (idt82p33->page_offset == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) err = idt82p33_xfer(idt82p33, PAGE_ADDR, &val, sizeof(val), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(&idt82p33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "failed to set page offset %d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) idt82p33->page_offset = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int idt82p33_rdwr(struct idt82p33 *idt82p33, unsigned int regaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned char *buf, unsigned int count, bool write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 offset, page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) page = _PAGE(regaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) offset = _OFFSET(regaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) err = idt82p33_page_offset(idt82p33, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = idt82p33_xfer(idt82p33, offset, buf, count, write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int idt82p33_read(struct idt82p33 *idt82p33, unsigned int regaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned char *buf, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return idt82p33_rdwr(idt82p33, regaddr, buf, count, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int idt82p33_write(struct idt82p33 *idt82p33, unsigned int regaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned char *buf, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return idt82p33_rdwr(idt82p33, regaddr, buf, count, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enum pll_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 dpll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (channel->pll_mode == mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) &dpll_mode, sizeof(dpll_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dpll_mode |= (mode << PLL_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &dpll_mode, sizeof(dpll_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) channel->pll_mode = dpll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int _idt82p33_gettime(struct idt82p33_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 buf[TOD_BYTE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) &trigger, sizeof(trigger));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (idt82p33->calculate_overhead_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) idt82p33->start_time = ktime_get_raw();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) idt82p33_byte_array_to_timespec(ts, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * TOD Trigger:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Bits[7:4] Write 0x9, MSB write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Bits[3:0] Read 0x9, LSB read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int _idt82p33_settime(struct idt82p33_channel *channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct timespec64 const *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct timespec64 local_ts = *ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) char buf[TOD_BYTE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) s64 dynamic_overhead_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned char trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &trigger, sizeof(trigger));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (idt82p33->calculate_overhead_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dynamic_overhead_ns = ktime_to_ns(ktime_get_raw())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) - ktime_to_ns(idt82p33->start_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) timespec64_add_ns(&local_ts, dynamic_overhead_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) idt82p33->calculate_overhead_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) idt82p33_timespec_to_byte_array(&local_ts, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Store the new time value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 0; i < TOD_BYTE_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) &buf[i], sizeof(buf[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct timespec64 ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) s64 now_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) idt82p33->calculate_overhead_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) err = _idt82p33_gettime(channel, &ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) now_ns = timespec64_to_ns(&ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) now_ns += delta_ns + idt82p33->tod_write_overhead_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ts = ns_to_timespec64(now_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) err = _idt82p33_settime(channel, &ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned char buf[5] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int neg_adj = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) s64 fcw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (scaled_ppm == channel->current_freq_ppb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Frequency Control Word unit is: 1.68 * 10^-10 ppm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * adjfreq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * ppb * 10^9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * FCW = ----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * adjfine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * scaled_ppm * 5^12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * FCW = -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * 168 * 2^4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (scaled_ppm < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) neg_adj = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) scaled_ppm = -scaled_ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) fcw = scaled_ppm * 244140625ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) fcw = div_u64(fcw, 2688);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (neg_adj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) fcw = -fcw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) buf[i] = fcw & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) fcw >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (err == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) channel->current_freq_ppb = scaled_ppm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int idt82p33_measure_one_byte_write_overhead(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct idt82p33_channel *channel, s64 *overhead_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ktime_t start, stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) s64 total_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) total_ns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *overhead_ns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) start = ktime_get_raw();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) &trigger, sizeof(trigger));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) stop = ktime_get_raw();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int idt82p33_measure_tod_write_9_byte_overhead(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct idt82p33_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 buf[TOD_BYTE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ktime_t start, stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) s64 total_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) total_ns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) idt82p33->tod_write_overhead_ns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) start = ktime_get_raw();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Need one less byte for applicable overhead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err = idt82p33_write(idt82p33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) channel->dpll_tod_cnfg + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) &buf[i], sizeof(buf[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) stop = ktime_get_raw();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) idt82p33->tod_write_overhead_ns = div_s64(total_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MAX_MEASURMENT_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int idt82p33_measure_settime_gettime_gap_overhead(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct idt82p33_channel *channel, s64 *overhead_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct timespec64 ts1 = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct timespec64 ts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *overhead_ns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) err = _idt82p33_settime(channel, &ts1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) err = _idt82p33_gettime(channel, &ts2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) s64 trailing_overhead_ns, one_byte_write_ns, gap_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) idt82p33->tod_write_overhead_ns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) err = idt82p33_measure_one_byte_write_overhead(channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &one_byte_write_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) err = idt82p33_measure_tod_write_9_byte_overhead(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) trailing_overhead_ns = gap_ns - (2 * one_byte_write_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u8 page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u8 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (page == PLLMASK_ADDR_HI && offset == PLLMASK_ADDR_LO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if ((val & 0xfc) || !(val & 0x3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(&idt82p33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "Invalid PLL mask 0x%hhx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) idt82p33->pll_mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } else if (page == PLL0_OUTMASK_ADDR_HI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) offset == PLL0_OUTMASK_ADDR_LO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) idt82p33->channel[0].output_mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) } else if (page == PLL1_OUTMASK_ADDR_HI &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) offset == PLL1_OUTMASK_ADDR_LO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) idt82p33->channel[1].output_mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void idt82p33_display_masks(struct idt82p33 *idt82p33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u8 mask, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_info(&idt82p33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "pllmask = 0x%02x\n", idt82p33->pll_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for (i = 0; i < MAX_PHC_PLL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mask = 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (mask & idt82p33->pll_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_info(&idt82p33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) "PLL%d output_mask = 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) i, idt82p33->channel[i].output_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 sync_cnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (enable == channel->sync_tod_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (enable && sync_tod_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mod_delayed_work(system_wq, &channel->sync_tod_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sync_tod_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &sync_cnfg, sizeof(sync_cnfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) sync_cnfg &= ~SYNC_TOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sync_cnfg |= SYNC_TOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) err = idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) &sync_cnfg, sizeof(sync_cnfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) channel->sync_tod_on = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (enable && sync_tod_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mod_delayed_work(system_wq, &channel->sync_tod_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) sync_tod_timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void idt82p33_sync_tod_work_handler(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct idt82p33_channel *channel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) container_of(work, struct idt82p33_channel, sync_tod_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mutex_lock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) (void)idt82p33_sync_tod(channel, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mutex_unlock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int idt82p33_pps_enable(struct idt82p33_channel *channel, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u8 mask, outn, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mask = channel->output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) outn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) while (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (mask & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) &val, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val &= ~SQUELCH_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) val |= SQUELCH_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) err = idt82p33_write(idt82p33, OUT_MUX_CNFG(outn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) &val, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mask >>= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) outn++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int idt82p33_enable_tod(struct idt82p33_channel *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct timespec64 ts = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) err = idt82p33_write(idt82p33, channel->dpll_input_mode_cnfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) &val, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) err = idt82p33_pps_enable(channel, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) err = idt82p33_measure_tod_write_overhead(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) err = _idt82p33_settime(channel, &ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return idt82p33_sync_tod(channel, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct idt82p33_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) for (i = 0; i < MAX_PHC_PLL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) channel = &idt82p33->channel[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (channel->ptp_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ptp_clock_unregister(channel->ptp_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) cancel_delayed_work_sync(&channel->sync_tod_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int idt82p33_enable(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct ptp_clock_request *rq, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct idt82p33_channel *channel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) container_of(ptp, struct idt82p33_channel, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mutex_lock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (rq->type == PTP_CLK_REQ_PEROUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) err = idt82p33_pps_enable(channel, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Only accept a 1-PPS aligned to the second. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) rq->perout.period.nsec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) err = -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) err = idt82p33_pps_enable(channel, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mutex_unlock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct idt82p33_channel *channel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) container_of(ptp, struct idt82p33_channel, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mutex_lock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) err = _idt82p33_adjfine(channel, scaled_ppm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mutex_unlock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct idt82p33_channel *channel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) container_of(ptp, struct idt82p33_channel, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) mutex_lock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (abs(delta_ns) < phase_snap_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mutex_unlock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) err = _idt82p33_adjtime(channel, delta_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mutex_unlock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) err = idt82p33_sync_tod(channel, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mutex_unlock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct idt82p33_channel *channel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) container_of(ptp, struct idt82p33_channel, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mutex_lock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) err = _idt82p33_gettime(channel, ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) mutex_unlock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int idt82p33_settime(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) const struct timespec64 *ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct idt82p33_channel *channel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) container_of(ptp, struct idt82p33_channel, caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct idt82p33 *idt82p33 = channel->idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mutex_lock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) err = _idt82p33_settime(channel, ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mutex_unlock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) channel->dpll_tod_sts = DPLL1_TOD_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) channel->dpll_tod_sts = DPLL2_TOD_STS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) INIT_DELAYED_WORK(&channel->sync_tod_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) idt82p33_sync_tod_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) channel->sync_tod_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) channel->current_freq_ppb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static void idt82p33_caps_init(struct ptp_clock_info *caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) caps->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) caps->max_adj = 92000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) caps->adjfine = idt82p33_adjfine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) caps->adjtime = idt82p33_adjtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) caps->gettime64 = idt82p33_gettime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) caps->settime64 = idt82p33_settime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) caps->enable = idt82p33_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct idt82p33_channel *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!(index < MAX_PHC_PLL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) channel = &idt82p33->channel[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) err = idt82p33_channel_init(channel, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) channel->idt82p33 = idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) idt82p33_caps_init(&channel->caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) snprintf(channel->caps.name, sizeof(channel->caps.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "IDT 82P33 PLL%u", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) channel->caps.n_per_out = hweight8(channel->output_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) err = idt82p33_enable_tod(channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (IS_ERR(channel->ptp_clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) err = PTR_ERR(channel->ptp_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) channel->ptp_clock = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!channel->ptp_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_info(&idt82p33->client->dev, "PLL%d registered as ptp%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) index, channel->ptp_clock->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct idt82p33_fwrc *rec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u8 loaddr, page, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) s32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_dbg(&idt82p33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "requesting firmware '%s'\n", FW_FILENAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) err = request_firmware(&fw, FW_FILENAME, &idt82p33->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_dbg(&idt82p33->client->dev, "firmware size %zu bytes\n", fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) rec = (struct idt82p33_fwrc *) fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) for (len = fw->size; len > 0; len -= sizeof(*rec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (rec->reserved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_err(&idt82p33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "bad firmware, reserved field non-zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) val = rec->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) loaddr = rec->loaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) page = rec->hiaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) rec++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) err = idt82p33_check_and_set_masks(idt82p33, page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) loaddr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (err == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* maximum 8 pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (page >= PAGE_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Page size 128, last 4 bytes of page skipped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (((loaddr > 0x7b) && (loaddr <= 0x7f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) || loaddr > 0xfb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) err = idt82p33_write(idt82p33, _ADDR(page, loaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) &val, sizeof(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) idt82p33_display_masks(idt82p33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int idt82p33_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct idt82p33 *idt82p33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) (void)id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) idt82p33 = devm_kzalloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) sizeof(struct idt82p33), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (!idt82p33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) mutex_init(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) idt82p33->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) idt82p33->page_offset = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) idt82p33->tod_write_overhead_ns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) idt82p33->calculate_overhead_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) idt82p33->pll_mask = DEFAULT_PLL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) mutex_lock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) err = idt82p33_load_firmware(idt82p33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) dev_warn(&idt82p33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) "loading firmware failed with %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (idt82p33->pll_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) for (i = 0; i < MAX_PHC_PLL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (idt82p33->pll_mask & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) err = idt82p33_enable_channel(idt82p33, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dev_err(&idt82p33->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "no PLLs flagged as PHCs, nothing to do\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) mutex_unlock(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) idt82p33_ptp_clock_unregister_all(idt82p33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) i2c_set_clientdata(client, idt82p33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int idt82p33_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct idt82p33 *idt82p33 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) idt82p33_ptp_clock_unregister_all(idt82p33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) mutex_destroy(&idt82p33->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static const struct of_device_id idt82p33_dt_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { .compatible = "idt,82p33810" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { .compatible = "idt,82p33813" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { .compatible = "idt,82p33814" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) { .compatible = "idt,82p33831" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) { .compatible = "idt,82p33910" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) { .compatible = "idt,82p33913" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) { .compatible = "idt,82p33914" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) { .compatible = "idt,82p33931" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) MODULE_DEVICE_TABLE(of, idt82p33_dt_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const struct i2c_device_id idt82p33_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) { "idt82p33810", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) { "idt82p33813", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) { "idt82p33814", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) { "idt82p33831", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) { "idt82p33910", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) { "idt82p33913", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) { "idt82p33914", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) { "idt82p33931", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) MODULE_DEVICE_TABLE(i2c, idt82p33_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static struct i2c_driver idt82p33_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .of_match_table = of_match_ptr(idt82p33_dt_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .name = "idt82p33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .probe = idt82p33_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .remove = idt82p33_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .id_table = idt82p33_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) module_i2c_driver(idt82p33_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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