^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * synchronization devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef PTP_IDTCLOCKMATRIX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PTP_IDTCLOCKMATRIX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "idt8a340_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FW_FILENAME "idtcm.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MAX_TOD (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MAX_PLL (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TOD_MASK_ADDR (0xFFA5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DEFAULT_TOD_MASK (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TOD0_PTP_PLL_ADDR (0xFFA8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TOD1_PTP_PLL_ADDR (0xFFA9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TOD2_PTP_PLL_ADDR (0xFFAA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TOD3_PTP_PLL_ADDR (0xFFAB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TOD0_OUT_ALIGN_MASK_ADDR (0xFFB0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TOD1_OUT_ALIGN_MASK_ADDR (0xFFB2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TOD2_OUT_ALIGN_MASK_ADDR (0xFFB4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TOD3_OUT_ALIGN_MASK_ADDR (0xFFB6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DEFAULT_OUTPUT_MASK_PLL0 (0x003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DEFAULT_OUTPUT_MASK_PLL1 (0x00c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DEFAULT_OUTPUT_MASK_PLL2 (0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DEFAULT_OUTPUT_MASK_PLL3 (0x0c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DEFAULT_TOD0_PTP_PLL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DEFAULT_TOD1_PTP_PLL (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DEFAULT_TOD2_PTP_PLL (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DEFAULT_TOD3_PTP_PLL (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define POST_SM_RESET_DELAY_MS (3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PHASE_PULL_IN_THRESHOLD_NS (150000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PHASE_PULL_IN_THRESHOLD_NS_V487 (15000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TOD_WRITE_OVERHEAD_COUNT_MAX (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TOD_BYTE_COUNT (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WR_PHASE_SETUP_MS (5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OUTPUT_MODULE_FROM_INDEX(index) (OUTPUT_0 + (index) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IDTCM_MAX_WRITE_COUNT (512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Values of DPLL_N.DPLL_MODE.PLL_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum pll_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PLL_MODE_MIN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PLL_MODE_NORMAL = PLL_MODE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PLL_MODE_WRITE_PHASE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PLL_MODE_WRITE_FREQUENCY = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PLL_MODE_GPIO_INC_DEC = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PLL_MODE_SYNTHESIS = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PLL_MODE_PHASE_MEASUREMENT = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PLL_MODE_DISABLED = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PLL_MODE_MAX = PLL_MODE_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum hw_tod_write_trig_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) HW_TOD_WR_TRIG_SEL_MIN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) HW_TOD_WR_TRIG_SEL_RESERVED = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) HW_TOD_WR_TRIG_SEL_GPIO = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* 4.8.7 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enum scsr_tod_write_trig_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SCSR_TOD_WR_TRIG_SEL_DISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SCSR_TOD_WR_TRIG_SEL_IMMEDIATE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SCSR_TOD_WR_TRIG_SEL_REFCLK = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SCSR_TOD_WR_TRIG_SEL_PWMPPS = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SCSR_TOD_WR_TRIG_SEL_TODPPS = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SCSR_TOD_WR_TRIG_SEL_SYNCFOD = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SCSR_TOD_WR_TRIG_SEL_GPIO = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SCSR_TOD_WR_TRIG_SEL_MAX = SCSR_TOD_WR_TRIG_SEL_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* 4.8.7 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) enum scsr_tod_write_type_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SCSR_TOD_WR_TYPE_SEL_ABSOLUTE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SCSR_TOD_WR_TYPE_SEL_MAX = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct idtcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct idtcm_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct ptp_clock_info caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct ptp_clock *ptp_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct idtcm *idtcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 dpll_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 dpll_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 dpll_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 dpll_ctrl_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u16 dpll_phase_pull_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u16 tod_read_primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u16 tod_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 tod_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 hw_dpll_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum pll_mode pll_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u16 output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int write_phase_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct idtcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct idtcm_channel channel[MAX_TOD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 page_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 tod_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) char version[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Overhead calculation for adjtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 calculate_overhead_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) s64 tod_write_overhead_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ktime_t start_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Protects I2C read/modify/write registers from concurrent access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct mutex reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct idtcm_fwrc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 hiaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 loaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif /* PTP_IDTCLOCKMATRIX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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