^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* idt8a340_reg.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Originally generated by regen.tcl on Thu Feb 14 19:23:44 PST 2019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * https://github.com/richardcochran/regen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Hand modified to include some HW registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on 4.8.0, SCSR rev C commit a03c7ae5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef HAVE_IDT8A340_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define HAVE_IDT8A340_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PAGE_ADDR_BASE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PAGE_ADDR 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HW_REVISION 0x8180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REV_ID 0x007a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HW_DPLL_0 (0x8a00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HW_DPLL_1 (0x8b00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HW_DPLL_2 (0x8c00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HW_DPLL_3 (0x8d00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HW_DPLL_4 (0x8e00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HW_DPLL_5 (0x8f00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HW_DPLL_6 (0x9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HW_DPLL_7 (0x9100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HW_DPLL_TOD_CTRL_1 (0x089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HW_DPLL_TOD_CTRL_2 (0x08A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HW_DPLL_TOD_OVR__0 (0x098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HW_DPLL_TOD_OUT_0__0 (0x0B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HW_Q8_CH_SYNC_CTRL_0 (0xa748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HW_Q8_CH_SYNC_CTRL_1 (0xa749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HW_Q9_CH_SYNC_CTRL_0 (0xa74a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HW_Q9_CH_SYNC_CTRL_1 (0xa74b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HW_Q10_CH_SYNC_CTRL_0 (0xa74c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HW_Q10_CH_SYNC_CTRL_1 (0xa74d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HW_Q11_CH_SYNC_CTRL_0 (0xa74e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HW_Q11_CH_SYNC_CTRL_1 (0xa74f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SYNC_SOURCE_DPLL0_TOD_PPS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SYNC_SOURCE_DPLL1_TOD_PPS 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SYNC_SOURCE_DPLL2_TOD_PPS 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SYNC_SOURCE_DPLL3_TOD_PPS 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SYNCTRL1_MASTER_SYNC_RST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SYNCTRL1_MASTER_SYNC_TRIG BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SYNCTRL1_TOD_SYNC_TRIG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HW_Q8_CTRL_SPARE (0xa7d4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HW_Q11_CTRL_SPARE (0xa7ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Select FOD5 as sync_trigger for Q8 divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Transition from logic zero to one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * sets trigger to sync Q8 divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Unused when FOD4 is driving Q8 divider (normal operation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define Q9_TO_Q8_SYNC_TRIG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Enable FOD5 as driver for clock and sync for Q8 divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Enable fanout buffer for FOD5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Unused when FOD4 is driving Q8 divider (normal operation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Select FOD6 as sync_trigger for Q11 divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Transition from logic zero to one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * sets trigger to sync Q11 divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Unused when FOD7 is driving Q11 divider (normal operation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define Q10_TO_Q11_SYNC_TRIG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Enable FOD6 as driver for clock and sync for Q11 divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Enable fanout buffer for FOD6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Unused when FOD7 is driving Q11 divider (normal operation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RESET_CTRL 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SM_RESET 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SM_RESET_CMD 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GENERAL_STATUS 0xc014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HW_REV_ID 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BOND_ID 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HW_CSR_ID 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HW_IRQ_ID 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MAJ_REL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MIN_REL 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HOTFIX_REL 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PIPELINE_ID 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BUILD_ID 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define JTAG_DEVICE_ID 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PRODUCT_ID 0x001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OTP_SCSR_CONFIG_SELECT 0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define STATUS 0xc03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define USER_GPIO0_TO_7_STATUS 0x008a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define USER_GPIO8_TO_15_STATUS 0x008b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GPIO_USER_CONTROL 0xc160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GPIO0_TO_7_OUT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GPIO8_TO_15_OUT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define STICKY_STATUS_CLEAR 0xc164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ALERT_CFG 0xc188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SYS_DPLL_XO 0xc194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SYS_APLL 0xc19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define INPUT_0 0xc1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define INPUT_1 0xc1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define INPUT_2 0xc1d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define INPUT_3 0xc200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define INPUT_4 0xc210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define INPUT_5 0xc220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define INPUT_6 0xc230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define INPUT_7 0xc240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define INPUT_8 0xc250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define INPUT_9 0xc260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define INPUT_10 0xc280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define INPUT_11 0xc290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define INPUT_12 0xc2a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define INPUT_13 0xc2b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define INPUT_14 0xc2c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define INPUT_15 0xc2d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define REF_MON_0 0xc2e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define REF_MON_1 0xc2ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define REF_MON_2 0xc300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define REF_MON_3 0xc30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define REF_MON_4 0xc318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define REF_MON_5 0xc324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define REF_MON_6 0xc330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define REF_MON_7 0xc33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define REF_MON_8 0xc348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define REF_MON_9 0xc354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define REF_MON_10 0xc360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define REF_MON_11 0xc36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define REF_MON_12 0xc380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define REF_MON_13 0xc38c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define REF_MON_14 0xc398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define REF_MON_15 0xc3a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DPLL_0 0xc3b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DPLL_CTRL_REG_0 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DPLL_CTRL_REG_1 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DPLL_CTRL_REG_2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DPLL_TOD_SYNC_CFG 0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DPLL_COMBO_SLAVE_CFG_0 0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DPLL_COMBO_SLAVE_CFG_1 0x0033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DPLL_SLAVE_REF_CFG 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DPLL_REF_MODE 0x0035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DPLL_PHASE_MEASUREMENT_CFG 0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DPLL_MODE 0x0037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DPLL_1 0xc400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DPLL_2 0xc438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DPLL_3 0xc480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DPLL_4 0xc4b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DPLL_5 0xc500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DPLL_6 0xc538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DPLL_7 0xc580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SYS_DPLL 0xc5b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DPLL_CTRL_0 0xc600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DPLL_CTRL_COMBO_MASTER_CFG 0x003a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DPLL_CTRL_1 0xc63c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DPLL_CTRL_2 0xc680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DPLL_CTRL_3 0xc6bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DPLL_CTRL_4 0xc700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DPLL_CTRL_5 0xc73c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DPLL_CTRL_6 0xc780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DPLL_CTRL_7 0xc7bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SYS_DPLL_CTRL 0xc800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DPLL_PHASE_0 0xc818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Signed 42-bit FFO in units of 2^(-53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DPLL_WR_PHASE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DPLL_PHASE_1 0xc81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DPLL_PHASE_2 0xc820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DPLL_PHASE_3 0xc824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DPLL_PHASE_4 0xc828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DPLL_PHASE_5 0xc82c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DPLL_PHASE_6 0xc830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DPLL_PHASE_7 0xc834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DPLL_FREQ_0 0xc838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Signed 42-bit FFO in units of 2^(-53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DPLL_WR_FREQ 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DPLL_FREQ_1 0xc840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DPLL_FREQ_2 0xc848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DPLL_FREQ_3 0xc850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DPLL_FREQ_4 0xc858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DPLL_FREQ_5 0xc860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DPLL_FREQ_6 0xc868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DPLL_FREQ_7 0xc870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DPLL_PHASE_PULL_IN_0 0xc880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define PULL_IN_CTRL 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DPLL_PHASE_PULL_IN_1 0xc888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DPLL_PHASE_PULL_IN_2 0xc890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DPLL_PHASE_PULL_IN_3 0xc898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DPLL_PHASE_PULL_IN_4 0xc8a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DPLL_PHASE_PULL_IN_5 0xc8a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DPLL_PHASE_PULL_IN_6 0xc8b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DPLL_PHASE_PULL_IN_7 0xc8b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define GPIO_CFG 0xc8c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define GPIO_CFG_GBL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define GPIO_0 0xc8c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define GPIO_DCO_INC_DEC 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define GPIO_OUT_CTRL_0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define GPIO_OUT_CTRL_1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define GPIO_TOD_TRIG 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GPIO_DPLL_INDICATOR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GPIO_LOS_INDICATOR 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define GPIO_REF_INPUT_DSQ_0 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define GPIO_REF_INPUT_DSQ_1 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define GPIO_REF_INPUT_DSQ_2 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define GPIO_REF_INPUT_DSQ_3 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define GPIO_MAN_CLK_SEL_0 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define GPIO_MAN_CLK_SEL_1 0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define GPIO_MAN_CLK_SEL_2 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define GPIO_SLAVE 0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define GPIO_ALERT_OUT_CFG 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define GPIO_TOD_NOTIFICATION_CFG 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define GPIO_CTRL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define GPIO_1 0xc8d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define GPIO_2 0xc8e6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define GPIO_3 0xc900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define GPIO_4 0xc912
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define GPIO_5 0xc924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define GPIO_6 0xc936
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define GPIO_7 0xc948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define GPIO_8 0xc95a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define GPIO_9 0xc980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define GPIO_10 0xc992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define GPIO_11 0xc9a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define GPIO_12 0xc9b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define GPIO_13 0xc9c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define GPIO_14 0xc9da
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define GPIO_15 0xca00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define OUT_DIV_MUX 0xca12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OUTPUT_0 0xca14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* FOD frequency output divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define OUT_DIV 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define OUT_DUTY_CYCLE_HIGH 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define OUT_CTRL_0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define OUT_CTRL_1 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Phase adjustment in FOD cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define OUT_PHASE_ADJ 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define OUTPUT_1 0xca24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define OUTPUT_2 0xca34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define OUTPUT_3 0xca44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define OUTPUT_4 0xca54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OUTPUT_5 0xca64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define OUTPUT_6 0xca80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define OUTPUT_7 0xca90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define OUTPUT_8 0xcaa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define OUTPUT_9 0xcab0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define OUTPUT_10 0xcac0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define OUTPUT_11 0xcad0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SERIAL 0xcae0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define PWM_ENCODER_0 0xcb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PWM_ENCODER_1 0xcb08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PWM_ENCODER_2 0xcb10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PWM_ENCODER_3 0xcb18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PWM_ENCODER_4 0xcb20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PWM_ENCODER_5 0xcb28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PWM_ENCODER_6 0xcb30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PWM_ENCODER_7 0xcb38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PWM_DECODER_0 0xcb40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define PWM_DECODER_1 0xcb48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PWM_DECODER_2 0xcb50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PWM_DECODER_3 0xcb58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PWM_DECODER_4 0xcb60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PWM_DECODER_5 0xcb68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PWM_DECODER_6 0xcb70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PWM_DECODER_7 0xcb80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PWM_DECODER_8 0xcb88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PWM_DECODER_9 0xcb90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PWM_DECODER_10 0xcb98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PWM_DECODER_11 0xcba0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PWM_DECODER_12 0xcba8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PWM_DECODER_13 0xcbb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define PWM_DECODER_14 0xcbb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define PWM_DECODER_15 0xcbc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PWM_USER_DATA 0xcbc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define TOD_0 0xcbcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Enable TOD counter, output channel sync and even-PPS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TOD_CFG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TOD_1 0xcbce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TOD_2 0xcbd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define TOD_3 0xcbd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define TOD_WRITE_0 0xcc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* 8-bit subns, 32-bit ns, 48-bit seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define TOD_WRITE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Counter increments after TOD write is completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define TOD_WRITE_COUNTER 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* TOD write trigger configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define TOD_WRITE_SELECT_CFG_0 0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* TOD write trigger selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define TOD_WRITE_CMD 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define TOD_WRITE_1 0xcc10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define TOD_WRITE_2 0xcc20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define TOD_WRITE_3 0xcc30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define TOD_READ_PRIMARY_0 0xcc40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* 8-bit subns, 32-bit ns, 48-bit seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define TOD_READ_PRIMARY 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Counter increments after TOD write is completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define TOD_READ_PRIMARY_COUNTER 0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Read trigger configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define TOD_READ_PRIMARY_SEL_CFG_0 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Read trigger selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define TOD_READ_PRIMARY_CMD 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define TOD_READ_PRIMARY_1 0xcc50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define TOD_READ_PRIMARY_2 0xcc60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define TOD_READ_PRIMARY_3 0xcc80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define TOD_READ_SECONDARY_0 0xcc90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define TOD_READ_SECONDARY_1 0xcca0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define TOD_READ_SECONDARY_2 0xccb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define TOD_READ_SECONDARY_3 0xccc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define OUTPUT_TDC_CFG 0xccd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define OUTPUT_TDC_0 0xcd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define OUTPUT_TDC_1 0xcd08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define OUTPUT_TDC_2 0xcd10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define OUTPUT_TDC_3 0xcd18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define INPUT_TDC 0xcd20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SCRATCH 0xcf50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define EEPROM 0xcf68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define OTP 0xcf70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define BYTE 0xcf80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Bit definitions for the MAJ_REL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define MAJOR_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define MAJOR_MASK (0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define PR_BUILD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define GPIO0_LEVEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define GPIO1_LEVEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define GPIO2_LEVEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define GPIO3_LEVEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define GPIO4_LEVEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define GPIO5_LEVEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define GPIO6_LEVEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define GPIO7_LEVEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define GPIO8_LEVEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define GPIO9_LEVEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define GPIO10_LEVEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define GPIO11_LEVEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define GPIO12_LEVEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define GPIO13_LEVEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define GPIO14_LEVEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define GPIO15_LEVEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* Bit definitions for the GPIO0_TO_7_OUT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define GPIO0_DRIVE_LEVEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define GPIO1_DRIVE_LEVEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define GPIO2_DRIVE_LEVEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define GPIO3_DRIVE_LEVEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define GPIO4_DRIVE_LEVEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define GPIO5_DRIVE_LEVEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define GPIO6_DRIVE_LEVEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define GPIO7_DRIVE_LEVEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Bit definitions for the GPIO8_TO_15_OUT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define GPIO8_DRIVE_LEVEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define GPIO9_DRIVE_LEVEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define GPIO10_DRIVE_LEVEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define GPIO11_DRIVE_LEVEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define GPIO12_DRIVE_LEVEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define GPIO13_DRIVE_LEVEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define GPIO14_DRIVE_LEVEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define GPIO15_DRIVE_LEVEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Bit definitions for the DPLL_TOD_SYNC_CFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define TOD_SYNC_SOURCE_SHIFT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define TOD_SYNC_SOURCE_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define TOD_SYNC_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Bit definitions for the DPLL_MODE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define WRITE_TIMER_MODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define PLL_MODE_SHIFT (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define PLL_MODE_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define STATE_MODE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define STATE_MODE_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Bit definitions for the GPIO_CFG_GBL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SUPPLY_MODE_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SUPPLY_MODE_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Bit definitions for the GPIO_DCO_INC_DEC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define INCDEC_DPLL_INDEX_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define INCDEC_DPLL_INDEX_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Bit definitions for the GPIO_OUT_CTRL_0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define CTRL_OUT_0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define CTRL_OUT_1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define CTRL_OUT_2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define CTRL_OUT_3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define CTRL_OUT_4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define CTRL_OUT_5 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define CTRL_OUT_6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define CTRL_OUT_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Bit definitions for the GPIO_OUT_CTRL_1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define CTRL_OUT_8 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define CTRL_OUT_9 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define CTRL_OUT_10 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define CTRL_OUT_11 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define CTRL_OUT_12 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define CTRL_OUT_13 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define CTRL_OUT_14 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define CTRL_OUT_15 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Bit definitions for the GPIO_TOD_TRIG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define TOD_TRIG_0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define TOD_TRIG_1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define TOD_TRIG_2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define TOD_TRIG_3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Bit definitions for the GPIO_DPLL_INDICATOR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define IND_DPLL_INDEX_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define IND_DPLL_INDEX_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Bit definitions for the GPIO_LOS_INDICATOR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define REFMON_INDEX_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define REFMON_INDEX_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Active level of LOS indicator, 0=low 1=high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define ACTIVE_LEVEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define DSQ_INP_0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define DSQ_INP_1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define DSQ_INP_2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define DSQ_INP_3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define DSQ_INP_4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define DSQ_INP_5 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define DSQ_INP_6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define DSQ_INP_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define DSQ_INP_8 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define DSQ_INP_9 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define DSQ_INP_10 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define DSQ_INP_11 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define DSQ_INP_12 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define DSQ_INP_13 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define DSQ_INP_14 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define DSQ_INP_15 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define DSQ_DPLL_0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define DSQ_DPLL_1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define DSQ_DPLL_2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define DSQ_DPLL_3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define DSQ_DPLL_4 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define DSQ_DPLL_5 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define DSQ_DPLL_6 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define DSQ_DPLL_7 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define DSQ_DPLL_SYS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define GPIO_DSQ_LEVEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define DPLL_TOD_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define DPLL_TOD_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define TOD_READ_SECONDARY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define GPIO_ASSERT_LEVEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Bit definitions for the GPIO_CTRL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define GPIO_FUNCTION_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define GPIO_CMOS_OD_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define GPIO_CONTROL_DIR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define GPIO_PU_PD_MODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define GPIO_FUNCTION_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define GPIO_FUNCTION_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Bit definitions for the OUT_CTRL_1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define OUT_SYNC_DISABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SQUELCH_VALUE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SQUELCH_DISABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define PAD_VDDO_SHIFT (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define PAD_VDDO_MASK (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define PAD_CMOSDRV_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define PAD_CMOSDRV_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Bit definitions for the TOD_CFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define TOD_EVEN_PPS_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define TOD_OUT_SYNC_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define TOD_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define WR_PWM_DECODER_INDEX_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define WR_PWM_DECODER_INDEX_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define WR_REF_INDEX_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define WR_REF_INDEX_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Bit definitions for the TOD_WRITE_CMD register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define TOD_WRITE_SELECTION_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define TOD_WRITE_SELECTION_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* 4.8.7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define TOD_WRITE_TYPE_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define TOD_WRITE_TYPE_MASK (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define RD_PWM_DECODER_INDEX_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define RD_PWM_DECODER_INDEX_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define RD_REF_INDEX_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define RD_REF_INDEX_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* Bit definitions for the TOD_READ_PRIMARY_CMD register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define TOD_READ_TRIGGER_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define TOD_READ_TRIGGER_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define TOD_READ_TRIGGER_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define COMBO_MASTER_HOLD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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