^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Chrager driver for Sgm4154x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Xu Shengfei <xsf@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/power_supply.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int dbg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) module_param_named(dbg_level, dbg_enable, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DBG(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (dbg_enable) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pr_info(args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SGM4154x_MANUFACTURER "SGMICRO"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SGM4154x_NAME "sgm41542"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SGM4154x_PN_ID (BIT(6) | BIT(5) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* define register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SGM4154x_CHRG_CTRL_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SGM4154x_CHRG_CTRL_1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SGM4154x_CHRG_CTRL_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SGM4154x_CHRG_CTRL_3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SGM4154x_CHRG_CTRL_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SGM4154x_CHRG_CTRL_5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SGM4154x_CHRG_CTRL_6 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SGM4154x_CHRG_CTRL_7 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SGM4154x_CHRG_STAT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SGM4154x_CHRG_FAULT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SGM4154x_CHRG_CTRL_a 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SGM4154x_CHRG_CTRL_b 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SGM4154x_CHRG_CTRL_c 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SGM4154x_CHRG_CTRL_d 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SGM4154x_INPUT_DET 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SGM4154x_CHRG_CTRL_f 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* charge status flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SGM4154x_CHRG_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SGM4154x_HIZ_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SGM4154x_TERM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SGM4154x_VAC_OVP_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SGM4154x_DPDM_ONGOING BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SGM4154x_VBUS_GOOD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SGM4154x_BOOSTV GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SGM4154x_BOOST_LIM BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SGM4154x_OTG_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Part ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SGM4154x_PN_MASK GENMASK(6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* WDT TIMER SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SGM4154x_WDT_TIMER_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SGM4154x_WDT_TIMER_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SGM4154x_WDT_TIMER_40S BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SGM4154x_WDT_TIMER_80S BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SGM4154x_WDT_TIMER_160S (BIT(4) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SGM4154x_WDT_RST_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* SAFETY TIMER SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SGM4154x_SAFETY_TIMER_MASK GENMASK(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SGM4154x_SAFETY_TIMER_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SGM4154x_SAFETY_TIMER_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SGM4154x_SAFETY_TIMER_5H 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SGM4154x_SAFETY_TIMER_10H BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* recharge voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SGM4154x_VRECHARGE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SGM4154x_VRECHRG_STEP_mV 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SGM4154x_VRECHRG_OFFSET_mV 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* charge status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SGM4154x_VSYS_STAT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SGM4154x_THERM_STAT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SGM4154x_PG_STAT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SGM4154x_CHG_STAT_MASK GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SGM4154x_PRECHRG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SGM4154x_FAST_CHRG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SGM4154x_TERM_CHRG (BIT(3) | BIT(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* charge type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SGM4154x_VBUS_STAT_MASK GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SGM4154x_NOT_CHRGING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SGM4154x_USB_SDP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SGM4154x_USB_CDP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SGM4154x_USB_DCP (BIT(5) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SGM4154x_UNKNOWN (BIT(7) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SGM4154x_NON_STANDARD (BIT(7) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SGM4154x_OTG_MODE (BIT(7) | BIT(6) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* TEMP Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SGM4154x_TEMP_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SGM4154x_TEMP_NORMAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SGM4154x_TEMP_WARM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SGM4154x_TEMP_COOL (BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SGM4154x_TEMP_COLD (BIT(0) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SGM4154x_TEMP_HOT (BIT(2) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* precharge current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SGM4154x_PRECHRG_CUR_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SGM4154x_PRECHRG_CURRENT_STEP_uA 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SGM4154x_PRECHRG_I_MIN_uA 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SGM4154x_PRECHRG_I_MAX_uA 780000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SGM4154x_PRECHRG_I_DEF_uA 180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* termination current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SGM4154x_TERMCHRG_CUR_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SGM4154x_TERMCHRG_CURRENT_STEP_uA 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SGM4154x_TERMCHRG_I_MIN_uA 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SGM4154x_TERMCHRG_I_MAX_uA 960000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SGM4154x_TERMCHRG_I_DEF_uA 180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* charge current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SGM4154x_ICHRG_CUR_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SGM4154x_ICHRG_I_STEP_uA 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SGM4154x_ICHRG_I_MIN_uA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SGM4154x_ICHRG_I_MAX_uA 3780000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SGM4154x_ICHRG_I_DEF_uA 2040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* charge voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SGM4154x_VREG_V_MASK GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SGM4154x_VREG_V_MAX_uV 4624000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SGM4154x_VREG_V_MIN_uV 3856000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SGM4154x_VREG_V_DEF_uV 4208000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SGM4154x_VREG_V_STEP_uV 32000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* VREG Fine Tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SGM4154x_VREG_FT_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SGM4154x_VREG_FT_UP_8mV BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SGM4154x_VREG_FT_DN_8mV BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SGM4154x_VREG_FT_DN_16mV (BIT(7) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* iindpm current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SGM4154x_IINDPM_I_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SGM4154x_IINDPM_I_MIN_uA 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SGM4154x_IINDPM_I_MAX_uA 3800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SGM4154x_IINDPM_STEP_uA 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SGM4154x_IINDPM_DEF_uA 2400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* vindpm voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SGM4154x_VINDPM_V_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SGM4154x_VINDPM_V_MIN_uV 3900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SGM4154x_VINDPM_V_MAX_uV 12000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SGM4154x_VINDPM_STEP_uV 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SGM4154x_VINDPM_DEF_uV 4500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SGM4154x_VINDPM_OS_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* DP DM SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SGM4154x_DP_VSEL_MASK GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SGM4154x_DM_VSEL_MASK GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* PUMPX SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SGM4154x_EN_PUMPX BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SGM4154x_PUMPX_UP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SGM4154x_PUMPX_DN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct sgm4154x_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ichg; /* charge current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ilim; /* input current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int vreg; /* regulation voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int iterm; /* termination current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int iprechg; /* precharge current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int vlim; /* minimum system voltage limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int max_ichg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int max_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct sgm4154x_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) bool vsys_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bool therm_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 chrg_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 vbus_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool chrg_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool hiz_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bool term_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bool vbus_gd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 chrg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 health;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 chrg_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 ntc_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct sgm4154x_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct power_supply *charger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct mutex i2c_rw_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) char model_name[I2C_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct sgm4154x_init_data init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct sgm4154x_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 watchdog_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct regulator_dev *otg_rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct notifier_block pm_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int input_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bool sgm4154x_suspend_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* SGM4154x REG06 BOOST_LIM[5:4], uV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const unsigned int BOOST_VOLT_LIMIT[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 4850000, 5000000, 5150000, 5300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const unsigned int BOOST_CURRENT_LIMIT[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 1200000, 2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum SGM4154x_VINDPM_OS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) VINDPM_OS_3900mV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) VINDPM_OS_5900mV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) VINDPM_OS_7500mV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) VINDPM_OS_10500mV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int sgm4154x_set_term_curr(struct sgm4154x_device *sgm, int uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (uA < SGM4154x_TERMCHRG_I_MIN_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) uA = SGM4154x_TERMCHRG_I_MIN_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else if (uA > SGM4154x_TERMCHRG_I_MAX_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) uA = SGM4154x_TERMCHRG_I_MAX_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) reg_val = (uA - SGM4154x_TERMCHRG_I_MIN_uA) / SGM4154x_TERMCHRG_CURRENT_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SGM4154x_CHRG_CTRL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SGM4154x_TERMCHRG_CUR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(sgm->dev, "set term current error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int sgm4154x_set_prechrg_curr(struct sgm4154x_device *sgm, int uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (uA < SGM4154x_PRECHRG_I_MIN_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) uA = SGM4154x_PRECHRG_I_MIN_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else if (uA > SGM4154x_PRECHRG_I_MAX_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uA = SGM4154x_PRECHRG_I_MAX_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg_val = (uA - SGM4154x_PRECHRG_I_MIN_uA) / SGM4154x_PRECHRG_CURRENT_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) reg_val = reg_val << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SGM4154x_CHRG_CTRL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SGM4154x_PRECHRG_CUR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev_err(sgm->dev, "set precharge current error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int sgm4154x_set_ichrg_curr(struct sgm4154x_device *sgm, int uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (uA < SGM4154x_ICHRG_I_MIN_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) uA = SGM4154x_ICHRG_I_MIN_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else if (uA > sgm->init_data.max_ichg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) uA = sgm->init_data.max_ichg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) reg_val = uA / SGM4154x_ICHRG_I_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SGM4154x_CHRG_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SGM4154x_ICHRG_CUR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(sgm->dev, "set icharge current error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int sgm4154x_set_chrg_volt(struct sgm4154x_device *sgm, int chrg_volt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (chrg_volt < SGM4154x_VREG_V_MIN_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) chrg_volt = SGM4154x_VREG_V_MIN_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) else if (chrg_volt > sgm->init_data.max_vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) chrg_volt = sgm->init_data.max_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) reg_val = (chrg_volt - SGM4154x_VREG_V_MIN_uV) / SGM4154x_VREG_V_STEP_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) reg_val = reg_val << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SGM4154x_CHRG_CTRL_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SGM4154x_VREG_V_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(sgm->dev, "set charge voltage error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int sgm4154x_set_vindpm_offset_os(struct sgm4154x_device *sgm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enum SGM4154x_VINDPM_OS offset_os)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) SGM4154x_CHRG_CTRL_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SGM4154x_VINDPM_OS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) offset_os);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(sgm->dev, "set vindpm offset os error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int sgm4154x_set_input_volt_lim(struct sgm4154x_device *sgm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int vindpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) enum SGM4154x_VINDPM_OS os_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (vindpm < SGM4154x_VINDPM_V_MIN_uV ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) vindpm > SGM4154x_VINDPM_V_MAX_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (vindpm < 5900000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) os_val = VINDPM_OS_3900mV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) offset = 3900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } else if (vindpm >= 5900000 && vindpm < 7500000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) os_val = VINDPM_OS_5900mV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) offset = 5900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) } else if (vindpm >= 7500000 && vindpm < 10500000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) os_val = VINDPM_OS_7500mV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) offset = 7500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) os_val = VINDPM_OS_10500mV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) offset = 10500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = sgm4154x_set_vindpm_offset_os(sgm, os_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_err(sgm->dev, "set vin dpm error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) reg_val = (vindpm - offset) / SGM4154x_VINDPM_STEP_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = regmap_update_bits(sgm->regmap, SGM4154x_CHRG_CTRL_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) SGM4154x_VINDPM_V_MASK, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(sgm->dev, "input voltage error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int sgm4154x_set_input_curr_lim(struct sgm4154x_device *sgm, int iindpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (iindpm > sgm->init_data.ilim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) iindpm = sgm->init_data.ilim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sgm->input_current = iindpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (iindpm < SGM4154x_IINDPM_I_MIN_uA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) iindpm > SGM4154x_IINDPM_I_MAX_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (iindpm >= SGM4154x_IINDPM_I_MIN_uA && iindpm <= 3100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) reg_val = (iindpm-SGM4154x_IINDPM_I_MIN_uA) / SGM4154x_IINDPM_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) else if (iindpm > 3100000 && iindpm < SGM4154x_IINDPM_I_MAX_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) reg_val = 0x1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) reg_val = 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) SGM4154x_CHRG_CTRL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) SGM4154x_IINDPM_I_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_err(sgm->dev, "set input current limit error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int sgm4154x_get_input_curr_lim(struct sgm4154x_device *sgm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int ilim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = regmap_read(sgm->regmap, SGM4154x_CHRG_CTRL_0, &ilim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_err(sgm->dev, "get input current limit error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (SGM4154x_IINDPM_I_MASK == (ilim & SGM4154x_IINDPM_I_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return SGM4154x_IINDPM_I_MAX_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ilim = (ilim & SGM4154x_IINDPM_I_MASK) * SGM4154x_IINDPM_STEP_uA + SGM4154x_IINDPM_I_MIN_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ilim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int sgm4154x_set_watchdog_timer(struct sgm4154x_device *sgm, int time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (time == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) reg_val = SGM4154x_WDT_TIMER_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) else if (time == 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) reg_val = SGM4154x_WDT_TIMER_40S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else if (time == 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) reg_val = SGM4154x_WDT_TIMER_80S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) reg_val = SGM4154x_WDT_TIMER_160S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SGM4154x_CHRG_CTRL_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SGM4154x_WDT_TIMER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(sgm->dev, "set watchdog timer error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int sgm4154x_enable_charger(struct sgm4154x_device *sgm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SGM4154x_CHRG_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SGM4154x_CHRG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SGM4154x_CHRG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(sgm->dev, "enable charger error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int sgm4154x_disable_charger(struct sgm4154x_device *sgm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SGM4154x_CHRG_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SGM4154x_CHRG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_err(sgm->dev, "disable charger error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int sgm4154x_set_vac_ovp(struct sgm4154x_device *sgm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) reg_val = 0xFF & SGM4154x_VAC_OVP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) SGM4154x_CHRG_CTRL_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) SGM4154x_VAC_OVP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(sgm->dev, "set vac ovp error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int sgm4154x_set_recharge_volt(struct sgm4154x_device *sgm, int recharge_volt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) reg_val = (recharge_volt - SGM4154x_VRECHRG_OFFSET_mV) / SGM4154x_VRECHRG_STEP_mV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) SGM4154x_CHRG_CTRL_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) SGM4154x_VRECHARGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(sgm->dev, "set recharger error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int sgm4154x_get_state(struct sgm4154x_device *sgm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct sgm4154x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int chrg_param_0, chrg_param_1, chrg_param_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int chrg_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = regmap_read(sgm->regmap, SGM4154x_CHRG_STAT, &chrg_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pr_err("read SGM4154x_CHRG_STAT fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DBG("SGM4154x_CHRG_STAT[0x%x]: 0x%x\n", SGM4154x_CHRG_STAT, chrg_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) state->chrg_type = chrg_stat & SGM4154x_VBUS_STAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) state->chrg_stat = chrg_stat & SGM4154x_CHG_STAT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) state->online = !!(chrg_stat & SGM4154x_PG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) state->therm_stat = !!(chrg_stat & SGM4154x_THERM_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) state->vsys_stat = !!(chrg_stat & SGM4154x_VSYS_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = regmap_read(sgm->regmap, SGM4154x_CHRG_FAULT, &fault);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) pr_err("read SGM4154x_CHRG_FAULT fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) DBG("SGM4154x_CHRG_FAULT[0x%x]: 0x%x\n", SGM4154x_CHRG_FAULT, fault);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) state->chrg_fault = fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) state->ntc_fault = fault & SGM4154x_TEMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) state->health = state->ntc_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = regmap_read(sgm->regmap, SGM4154x_CHRG_CTRL_0, &chrg_param_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pr_err("read SGM4154x_CHRG_CTRL_0 fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) state->hiz_en = !!(chrg_param_0 & SGM4154x_HIZ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) DBG("SGM4154x_CHRG_CTRL_0[0x%x]: 0x%x\n", SGM4154x_CHRG_CTRL_0, chrg_param_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = regmap_read(sgm->regmap, SGM4154x_CHRG_CTRL_5, &chrg_param_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pr_err("read SGM4154x_CHRG_CTRL_5 fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) state->term_en = !!(chrg_param_1 & SGM4154x_TERM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) DBG("SGM4154x_CHRG_CTRL_5[0x%x]: 0x%x\n", SGM4154x_CHRG_CTRL_5, chrg_param_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = regmap_read(sgm->regmap, SGM4154x_CHRG_CTRL_a, &chrg_param_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pr_err("read SGM4154x_CHRG_CTRL_a fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) state->vbus_gd = !!(chrg_param_2 & SGM4154x_VBUS_GOOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) DBG("SGM4154x_CHRG_CTRL_a[0x%x]: 0x%x\n", SGM4154x_CHRG_CTRL_a, chrg_param_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) DBG("chrg_type: 0x%x\n", state->chrg_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) DBG("chrg_stat: 0x%x\n", state->chrg_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DBG("online: 0x%x\n", state->online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DBG("therm_stat: 0x%x\n", state->therm_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) DBG("vsys_stat: 0x%x\n", state->vsys_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) DBG("chrg_fault: 0x%x\n", state->chrg_fault);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) DBG("ntc_fault: 0x%x\n", state->ntc_fault);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) DBG("health: 0x%x\n", state->health);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) DBG("hiz_en: 0x%x\n", state->hiz_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) DBG("term_en: 0x%x\n", state->term_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) DBG("vbus_gd: 0x%x\n", state->vbus_gd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int sgm4154x_property_is_writeable(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) enum power_supply_property prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) switch (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case POWER_SUPPLY_PROP_ONLINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int sgm4154x_charger_set_property(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) enum power_supply_property prop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) const union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct sgm4154x_device *sgm = power_supply_get_drvdata(psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) switch (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case POWER_SUPPLY_PROP_ONLINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) DBG("ONLINE: %d", val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (val->intval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ret = sgm4154x_enable_charger(sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = sgm4154x_disable_charger(sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) DBG("INPUT_CURRENT_LIMIT: %d\n", val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = sgm4154x_set_input_curr_lim(sgm, val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = sgm4154x_set_chrg_volt(sgm, val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int sgm4154x_charger_get_property(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) enum power_supply_property psp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct sgm4154x_device *sgm = power_supply_get_drvdata(psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct sgm4154x_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mutex_lock(&sgm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ret = sgm4154x_get_state(sgm, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(sgm->dev, "get state error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) mutex_unlock(&sgm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) sgm->state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mutex_unlock(&sgm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) switch (psp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case POWER_SUPPLY_PROP_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!state.chrg_type || (state.chrg_type == SGM4154x_OTG_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) else if (!state.chrg_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) else if (state.chrg_stat == SGM4154x_TERM_CHRG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) val->intval = POWER_SUPPLY_STATUS_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) val->intval = POWER_SUPPLY_STATUS_CHARGING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case POWER_SUPPLY_PROP_CHARGE_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) switch (state.chrg_stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case SGM4154x_PRECHRG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case SGM4154x_FAST_CHRG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case SGM4154x_TERM_CHRG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) val->intval = POWER_SUPPLY_CHARGE_TYPE_TRICKLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case SGM4154x_NOT_CHRGING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) val->intval = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case POWER_SUPPLY_PROP_MANUFACTURER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) val->strval = SGM4154x_MANUFACTURER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case POWER_SUPPLY_PROP_MODEL_NAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) val->strval = SGM4154x_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case POWER_SUPPLY_PROP_ONLINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) val->intval = state.online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case POWER_SUPPLY_PROP_PRESENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) val->intval = state.vbus_gd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case POWER_SUPPLY_PROP_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) val->intval = POWER_SUPPLY_TYPE_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) val->intval = sgm->init_data.max_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) val->intval = SGM4154x_ICHRG_I_MAX_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) val->intval = 12 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) val->intval = sgm4154x_get_input_curr_lim(sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (val->intval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static ssize_t registers_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct sgm4154x_device *sgm4154x = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u8 tmpbuf[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) for (addr = 0x0; addr <= SGM4154x_CHRG_CTRL_f; addr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = regmap_read(sgm4154x->regmap, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) len = snprintf(tmpbuf, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "Reg[%.2X] = 0x%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) memcpy(&buf[idx], tmpbuf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) idx += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static ssize_t registers_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct sgm4154x_device *sgm4154x = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = sscanf(buf, "%x %x", ®, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (ret == 2 && reg <= SGM4154x_CHRG_CTRL_f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) regmap_write(sgm4154x->regmap, (unsigned char)reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static DEVICE_ATTR_RW(registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void sgm4154x_create_device_node(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) device_create_file(dev, &dev_attr_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static irqreturn_t sgm4154x_irq_handler_thread(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct sgm4154x_device *sgm4154x = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct sgm4154x_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = sgm4154x_get_state(sgm4154x, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(sgm4154x->dev, "get state error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) sgm4154x->state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (state.vbus_gd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = sgm4154x_set_input_curr_lim(sgm4154x, sgm4154x->input_current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(sgm4154x->dev, "set input current error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) power_supply_changed(sgm4154x->charger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static enum power_supply_property sgm4154x_power_supply_props[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) POWER_SUPPLY_PROP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) POWER_SUPPLY_PROP_MANUFACTURER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) POWER_SUPPLY_PROP_MODEL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) POWER_SUPPLY_PROP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) POWER_SUPPLY_PROP_ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) POWER_SUPPLY_PROP_CHARGE_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) POWER_SUPPLY_PROP_PRESENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static char *sgm4154x_charger_supplied_to[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static struct power_supply_desc sgm4154x_power_supply_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .name = "sgm4154x-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .type = POWER_SUPPLY_TYPE_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .properties = sgm4154x_power_supply_props,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .num_properties = ARRAY_SIZE(sgm4154x_power_supply_props),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .get_property = sgm4154x_charger_get_property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .set_property = sgm4154x_charger_set_property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .property_is_writeable = sgm4154x_property_is_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static bool sgm4154x_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) case SGM4154x_CHRG_CTRL_0 ... SGM4154x_CHRG_CTRL_f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const struct regmap_config sgm4154x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .max_register = SGM4154x_CHRG_CTRL_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .volatile_reg = sgm4154x_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int sgm4154x_power_supply_init(struct sgm4154x_device *sgm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct power_supply_config psy_cfg = { .drv_data = sgm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .of_node = dev->of_node, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) psy_cfg.supplied_to = sgm4154x_charger_supplied_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) psy_cfg.num_supplicants = ARRAY_SIZE(sgm4154x_charger_supplied_to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) psy_cfg.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) sgm->charger = devm_power_supply_register(sgm->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) &sgm4154x_power_supply_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) &psy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (IS_ERR(sgm->charger))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int sgm4154x_hw_init(struct sgm4154x_device *sgm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct power_supply_battery_info bat_info = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ret = power_supply_get_battery_info(sgm->charger, &bat_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pr_info("sgm4154x: no battery information is supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * If no battery information is supplied, we should set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * default charge termination current to 120 mA, and default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * charge termination voltage to 4.35V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) bat_info.constant_charge_current_max_ua =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) SGM4154x_ICHRG_I_DEF_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) bat_info.constant_charge_voltage_max_uv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) SGM4154x_VREG_V_DEF_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) bat_info.precharge_current_ua =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SGM4154x_PRECHRG_I_DEF_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) bat_info.charge_term_current_ua =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) SGM4154x_TERMCHRG_I_DEF_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) sgm->init_data.max_ichg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) SGM4154x_ICHRG_I_MAX_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) sgm->init_data.max_vreg = SGM4154x_VREG_V_DEF_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (!bat_info.constant_charge_current_max_ua)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) bat_info.constant_charge_current_max_ua =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) SGM4154x_ICHRG_I_MAX_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!bat_info.constant_charge_voltage_max_uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) bat_info.constant_charge_voltage_max_uv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) SGM4154x_VREG_V_DEF_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!bat_info.precharge_current_ua)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) bat_info.precharge_current_ua =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) SGM4154x_PRECHRG_I_DEF_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (!bat_info.charge_term_current_ua)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) bat_info.charge_term_current_ua =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) SGM4154x_TERMCHRG_I_DEF_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!sgm->init_data.max_ichg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) sgm->init_data.max_ichg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) SGM4154x_ICHRG_I_MAX_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (bat_info.constant_charge_voltage_max_uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) sgm->init_data.max_vreg = bat_info.constant_charge_voltage_max_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret = sgm4154x_set_watchdog_timer(sgm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret = sgm4154x_set_ichrg_curr(sgm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) bat_info.constant_charge_current_max_ua);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = sgm4154x_set_prechrg_curr(sgm, bat_info.precharge_current_ua);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = sgm4154x_set_chrg_volt(sgm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) sgm->init_data.max_vreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = sgm4154x_set_term_curr(sgm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) bat_info.charge_term_current_ua);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = sgm4154x_set_input_volt_lim(sgm, sgm->init_data.vlim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = sgm4154x_set_input_curr_lim(sgm, 500 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret = sgm4154x_set_vac_ovp(sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = sgm4154x_set_recharge_volt(sgm, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) DBG("ichrg_curr:%d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) "prechrg_curr:%d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) "chrg_vol:%d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) "term_curr:%d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "input_curr_lim:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) bat_info.constant_charge_current_max_ua,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) bat_info.precharge_current_ua,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) bat_info.constant_charge_voltage_max_uv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) bat_info.charge_term_current_ua,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) sgm->init_data.ilim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int sgm4154x_parse_dt(struct sgm4154x_device *sgm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret = device_property_read_u32(sgm->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) "input-voltage-limit-microvolt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) &sgm->init_data.vlim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) sgm->init_data.vlim = SGM4154x_VINDPM_DEF_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (sgm->init_data.vlim > SGM4154x_VINDPM_V_MAX_uV ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) sgm->init_data.vlim < SGM4154x_VINDPM_V_MIN_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = device_property_read_u32(sgm->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) "input-current-limit-microamp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) &sgm->init_data.ilim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) sgm->init_data.ilim = SGM4154x_IINDPM_DEF_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (sgm->init_data.ilim > SGM4154x_IINDPM_I_MAX_uA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) sgm->init_data.ilim < SGM4154x_IINDPM_I_MIN_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static int sgm4154x_set_otg_voltage(struct sgm4154x_device *sgm, int uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int reg_val = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) while (i < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (uv == BOOST_VOLT_LIMIT[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) reg_val = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (reg_val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) reg_val = reg_val << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) SGM4154x_CHRG_CTRL_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) SGM4154x_BOOSTV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) dev_err(sgm->dev, "set otg voltage error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int sgm4154x_set_otg_current(struct sgm4154x_device *sgm, int ua)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (ua == BOOST_CURRENT_LIMIT[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) SGM4154x_CHRG_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) SGM4154x_BOOST_LIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_err(sgm->dev, "set boost current limit error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } else if (ua == BOOST_CURRENT_LIMIT[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) SGM4154x_CHRG_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) SGM4154x_BOOST_LIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) BIT(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dev_err(sgm->dev, "set boost current limit error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int sgm4154x_enable_vbus(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct sgm4154x_device *sgm = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) SGM4154x_CHRG_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) SGM4154x_OTG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) SGM4154x_OTG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev_err(sgm->dev, "set OTG enable error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static int sgm4154x_disable_vbus(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct sgm4154x_device *sgm = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ret = regmap_update_bits(sgm->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) SGM4154x_CHRG_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) SGM4154x_OTG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dev_err(sgm->dev, "set OTG disable error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int sgm4154x_is_enabled_vbus(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct sgm4154x_device *sgm = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) int temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ret = regmap_read(sgm->regmap, SGM4154x_CHRG_CTRL_1, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev_err(sgm->dev, "get vbus status error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return (temp & SGM4154x_OTG_EN) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static const struct regulator_ops sgm4154x_vbus_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .enable = sgm4154x_enable_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .disable = sgm4154x_disable_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .is_enabled = sgm4154x_is_enabled_vbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static struct regulator_desc sgm4154x_otg_rdesc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .of_match = "otg-vbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .name = "otg-vbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .regulators_node = of_match_ptr("regulators"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .ops = &sgm4154x_vbus_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .fixed_uV = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static int sgm4154x_vbus_regulator_register(struct sgm4154x_device *sgm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct regulator_config config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) np = of_get_child_by_name(sgm->dev->of_node, "regulators");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) dev_warn(sgm->dev, "cannot find regulators node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* otg regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) config.dev = sgm->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) config.driver_data = sgm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) sgm->otg_rdev = devm_regulator_register(sgm->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) &sgm4154x_otg_rdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (IS_ERR(sgm->otg_rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ret = PTR_ERR(sgm->otg_rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static int sgm4154x_suspend_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) unsigned long event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct sgm4154x_device *sgm = container_of(nb, struct sgm4154x_device, pm_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) case PM_SUSPEND_PREPARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) sgm->sgm4154x_suspend_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) case PM_POST_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) sgm->sgm4154x_suspend_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static int sgm4154x_hw_chipid_detect(struct sgm4154x_device *sgm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ret = regmap_read(sgm->regmap, SGM4154x_CHRG_CTRL_b, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static int sgm4154x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct sgm4154x_device *sgm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) sgm = devm_kzalloc(dev, sizeof(*sgm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (!sgm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) sgm->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) sgm->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) mutex_init(&sgm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) strncpy(sgm->model_name, id->name, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) sgm->regmap = devm_regmap_init_i2c(client, &sgm4154x_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (IS_ERR(sgm->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_err(dev, "Failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return PTR_ERR(sgm->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) i2c_set_clientdata(client, sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ret = sgm4154x_parse_dt(sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_err(dev, "Failed to read device tree properties%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ret = sgm4154x_hw_chipid_detect(sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if ((ret & SGM4154x_PN_MASK) != SGM4154x_PN_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pr_info("[%s] device not found !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) device_init_wakeup(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ret = devm_request_threaded_irq(dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) sgm4154x_irq_handler_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) IRQF_TRIGGER_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) "sgm41542-irq", sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) enable_irq_wake(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) sgm->pm_nb.notifier_call = sgm4154x_suspend_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) register_pm_notifier(&sgm->pm_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret = sgm4154x_power_supply_init(sgm, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) dev_err(dev, "Failed to register power supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ret = sgm4154x_hw_init(sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dev_err(dev, "Cannot initialize the chip.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* OTG setting 5V/1.2A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = sgm4154x_set_otg_voltage(sgm, 5000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dev_err(sgm->dev, "set OTG voltage error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = sgm4154x_set_otg_current(sgm, 1200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_err(sgm->dev, "set OTG current error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) sgm4154x_vbus_regulator_register(sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) sgm4154x_create_device_node(sgm->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static int sgm4154x_charger_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct sgm4154x_device *sgm = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) regulator_unregister(sgm->otg_rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) power_supply_unregister(sgm->charger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) mutex_destroy(&sgm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static void sgm4154x_charger_shutdown(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct sgm4154x_device *sgm = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret = sgm4154x_disable_charger(sgm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) pr_err("Failed to disable charger, ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static const struct i2c_device_id sgm4154x_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) { "sgm41542", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) MODULE_DEVICE_TABLE(i2c, sgm4154x_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static const struct of_device_id sgm4154x_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) { .compatible = "sgm,sgm41542", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) MODULE_DEVICE_TABLE(of, sgm4154x_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static struct i2c_driver sgm4154x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .name = "sgm4154x-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .of_match_table = sgm4154x_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .probe = sgm4154x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .remove = sgm4154x_charger_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .shutdown = sgm4154x_charger_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .id_table = sgm4154x_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) module_i2c_driver(sgm4154x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) MODULE_DESCRIPTION("sgm4154x charger driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags