^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Chrager driver for Sc8551
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Xu Shengfei <xsf@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/power_supply.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Register 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SC8551_REG_00 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SC8551_BAT_OVP_DIS_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SC8551_BAT_OVP_DIS_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SC8551_BAT_OVP_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SC8551_BAT_OVP_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SC8551_BAT_OVP_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SC8551_BAT_OVP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC8551_BAT_OVP_BASE 3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SC8551_BAT_OVP_LSB 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Register 02h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SC8551_REG_02 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC8551_BAT_OCP_DIS_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SC8551_BAT_OCP_DIS_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SC8551_BAT_OCP_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC8551_BAT_OCP_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC8551_BAT_OCP_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC8551_BAT_OCP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC8551_BAT_OCP_BASE 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC8551_BAT_OCP_LSB 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Register 05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC8551_REG_05 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC8551_AC_OVP_STAT_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC8551_AC_OVP_STAT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC8551_AC_OVP_FLAG_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC8551_AC_OVP_FLAG_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC8551_AC_OVP_MASK_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC8551_AC_OVP_MASK_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC8551_VDROP_THRESHOLD_SET_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC8551_VDROP_THRESHOLD_SET_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC8551_VDROP_THRESHOLD_300MV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC8551_VDROP_THRESHOLD_400MV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC8551_VDROP_DEGLITCH_SET_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC8551_VDROP_DEGLITCH_SET_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC8551_VDROP_DEGLITCH_8US 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC8551_VDROP_DEGLITCH_5MS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC8551_AC_OVP_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC8551_AC_OVP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC8551_AC_OVP_BASE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC8551_AC_OVP_LSB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC8551_AC_OVP_6P5V 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Register 06h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC8551_REG_06 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC8551_VBUS_PD_EN_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC8551_VBUS_PD_EN_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SC8551_VBUS_PD_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SC8551_VBUS_PD_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC8551_BUS_OVP_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC8551_BUS_OVP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC8551_BUS_OVP_BASE 6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC8551_BUS_OVP_LSB 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Register 08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SC8551_REG_08 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SC8551_BUS_OCP_DIS_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC8551_BUS_OCP_DIS_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC8551_BUS_OCP_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SC8551_BUS_OCP_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SC8551_IBUS_UCP_RISE_FLAG_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SC8551_IBUS_UCP_RISE_FLAG_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SC8551_IBUS_UCP_RISE_MASK_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SC8551_IBUS_UCP_RISE_MASK_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SC8551_IBUS_UCP_RISE_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SC8551_IBUS_UCP_RISE_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SC8551_IBUS_UCP_FALL_FLAG_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SC8551_IBUS_UCP_FALL_FLAG_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SC8551_BUS_OCP_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SC8551_BUS_OCP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SC8551_BUS_OCP_BASE 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SC8551_BUS_OCP_LSB 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Register 0Ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SC8551_REG_0A 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SC8551_TSHUT_FLAG_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SC8551_TSHUT_FLAG_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SC8551_TSHUT_STAT_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SC8551_TSHUT_STAT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SC8551_VBUS_ERRORLO_STAT_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SC8551_VBUS_ERRORLO_STAT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SC8551_VBUS_ERRORHI_STAT_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SC8551_VBUS_ERRORHI_STAT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SC8551_SS_TIMEOUT_FLAG_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SC8551_SS_TIMEOUT_FLAG_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SC8551_CONV_SWITCHING_STAT_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SC8551_CONV_SWITCHING_STAT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SC8551_CONV_OCP_FLAG_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SC8551_CONV_OCP_FLAG_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SC8551_PIN_DIAG_FALL_FLAG_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SC8551_PIN_DIAG_FALL_FLAG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Register 0Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SC8551_REG_0B 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SC8551_REG_RST_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SC8551_REG_RST_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SC8551_REG_RST_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SC8551_REG_RST_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SC8551_FSW_SET_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SC8551_FSW_SET_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SC8551_FSW_SET_300KHZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SC8551_FSW_SET_350KHZ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SC8551_FSW_SET_400KHZ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SC8551_FSW_SET_450KHZ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SC8551_FSW_SET_500KHZ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SC8551_FSW_SET_550KHZ 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SC8551_FSW_SET_600KHZ 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SC8551_FSW_SET_750KHZ 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SC8551_WD_TIMEOUT_FLAG_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SC8551_WD_TIMEOUT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SC8551_WATCHDOG_DIS_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SC8551_WATCHDOG_DIS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SC8551_WATCHDOG_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SC8551_WATCHDOG_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SC8551_WATCHDOG_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SC8551_WATCHDOG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SC8551_WATCHDOG_0P5S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SC8551_WATCHDOG_1S 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SC8551_WATCHDOG_5S 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SC8551_WATCHDOG_30S 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Register 0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SC8551_REG_0C 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SC8551_CHG_EN_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SC8551_CHG_EN_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SC8551_CHG_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SC8551_CHG_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SC8551_MS_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SC8551_MS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SC8551_MS_STANDALONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SC8551_MS_SLAVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SC8551_MS_MASTER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SC8551_ROLE_STDALONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SC8551_ROLE_SLAVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SC8551_ROLE_MASTER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SC8551_FREQ_SHIFT_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SC8551_FREQ_SHIFT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SC8551_FREQ_SHIFT_NORMINAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SC8551_FREQ_SHIFT_POSITIVE10 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SC8551_FREQ_SHIFT_NEGATIVE10 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SC8551_FREQ_SHIFT_SPREAD_SPECTRUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SC8551_TSBUS_DIS_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SC8551_TSBUS_DIS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SC8551_TSBUS_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SC8551_TSBUS_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SC8551_TSBAT_DIS_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SC8551_TSBAT_DIS_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SC8551_TSBAT_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SC8551_TSBAT_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Register 0Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SC8551_REG_0D 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SC8551_BAT_OVP_ALM_STAT_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SC8551_BAT_OVP_ALM_STAT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SC8551_BAT_OCP_ALM_STAT_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SC8551_BAT_OCP_ALM_STAT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SC8551_BUS_OVP_ALM_STAT_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SC8551_BUS_OVP_ALM_STAT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SC8551_BUS_OCP_ALM_STAT_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SC8551_BUS_OCP_ALM_STAT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SC8551_BAT_UCP_ALM_STAT_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SC8551_BAT_UCP_ALM_STAT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SC8551_ADAPTER_INSERT_STAT_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SC8551_ADAPTER_INSERT_STAT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SC8551_VBAT_INSERT_STAT_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SC8551_VBAT_INSERT_STAT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SC8551_ADC_DONE_STAT_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SC8551_ADC_DONE_STAT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SC8551_ADC_DONE_STAT_COMPLETE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SC8551_ADC_DONE_STAT_NOTCOMPLETE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Register 0Eh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SC8551_REG_0E 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SC8551_BAT_OVP_ALM_FLAG_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SC8551_BAT_OVP_ALM_FLAG_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SC8551_BAT_OCP_ALM_FLAG_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SC8551_BAT_OCP_ALM_FLAG_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SC8551_BUS_OVP_ALM_FLAG_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SC8551_BUS_OVP_ALM_FLAG_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SC8551_BUS_OCP_ALM_FLAG_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SC8551_BUS_OCP_ALM_FLAG_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SC8551_BAT_UCP_ALM_FLAG_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SC8551_BAT_UCP_ALM_FLAG_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SC8551_ADAPTER_INSERT_FLAG_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SC8551_ADAPTER_INSERT_FLAG_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SC8551_VBAT_INSERT_FLAG_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SC8551_VBAT_INSERT_FLAG_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SC8551_ADC_DONE_FLAG_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SC8551_ADC_DONE_FLAG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SC8551_ADC_DONE_FLAG_COMPLETE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SC8551_ADC_DONE_FLAG_NOTCOMPLETE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Register 0Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SC8551_REG_0F 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SC8551_BAT_OVP_ALM_MASK_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SC8551_BAT_OVP_ALM_MASK_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SC8551_BAT_OVP_ALM_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SC8551_BAT_OVP_ALM_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SC8551_BAT_OCP_ALM_MASK_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SC8551_BAT_OCP_ALM_MASK_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SC8551_BAT_OCP_ALM_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SC8551_BAT_OCP_ALM_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SC8551_BUS_OVP_ALM_MASK_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SC8551_BUS_OVP_ALM_MASK_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SC8551_BUS_OVP_ALM_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SC8551_BUS_OVP_ALM_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SC8551_BUS_OCP_ALM_MASK_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SC8551_BUS_OCP_ALM_MASK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SC8551_BUS_OCP_ALM_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SC8551_BUS_OCP_ALM_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SC8551_BAT_UCP_ALM_MASK_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SC8551_BAT_UCP_ALM_MASK_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SC8551_BAT_UCP_ALM_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SC8551_BAT_UCP_ALM_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SC8551_ADAPTER_INSERT_MASK_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SC8551_ADAPTER_INSERT_MASK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SC8551_ADAPTER_INSERT_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SC8551_ADAPTER_INSERT_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SC8551_VBAT_INSERT_MASK_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SC8551_VBAT_INSERT_MASK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SC8551_VBAT_INSERT_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SC8551_VBAT_INSERT_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SC8551_ADC_DONE_MASK_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SC8551_ADC_DONE_MASK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SC8551_ADC_DONE_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SC8551_ADC_DONE_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Register 10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SC8551_REG_10 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SC8551_BAT_OVP_FLT_STAT_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SC8551_BAT_OVP_FLT_STAT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SC8551_BAT_OCP_FLT_STAT_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SC8551_BAT_OCP_FLT_STAT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SC8551_BUS_OVP_FLT_STAT_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SC8551_BUS_OVP_FLT_STAT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SC8551_BUS_OCP_FLT_STAT_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SC8551_BUS_OCP_FLT_STAT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SC8551_TSBUS_TSBAT_ALM_STAT_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SC8551_TSBUS_TSBAT_ALM_STAT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SC8551_TSBAT_FLT_STAT_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SC8551_TSBAT_FLT_STAT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SC8551_TSBUS_FLT_STAT_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SC8551_TSBUS_FLT_STAT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SC8551_TDIE_ALM_STAT_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SC8551_TDIE_ALM_STAT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Register 11h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SC8551_REG_11 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SC8551_BAT_OVP_FLT_FLAG_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SC8551_BAT_OVP_FLT_FLAG_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SC8551_BAT_OCP_FLT_FLAG_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SC8551_BAT_OCP_FLT_FLAG_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SC8551_BUS_OVP_FLT_FLAG_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SC8551_BUS_OVP_FLT_FLAG_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SC8551_BUS_OCP_FLT_FLAG_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SC8551_BUS_OCP_FLT_FLAG_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SC8551_TSBUS_TSBAT_ALM_FLAG_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SC8551_TSBUS_TSBAT_ALM_FLAG_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SC8551_TSBAT_FLT_FLAG_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SC8551_TSBAT_FLT_FLAG_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SC8551_TSBUS_FLT_FLAG_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SC8551_TSBUS_FLT_FLAG_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SC8551_TDIE_ALM_FLAG_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SC8551_TDIE_ALM_FLAG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Register 12h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SC8551_REG_12 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SC8551_BAT_OVP_FLT_MASK_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SC8551_BAT_OVP_FLT_MASK_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SC8551_BAT_OVP_FLT_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SC8551_BAT_OVP_FLT_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SC8551_BAT_OCP_FLT_MASK_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SC8551_BAT_OCP_FLT_MASK_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SC8551_BAT_OCP_FLT_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SC8551_BAT_OCP_FLT_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SC8551_BUS_OVP_FLT_MASK_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SC8551_BUS_OVP_FLT_MASK_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SC8551_BUS_OVP_FLT_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SC8551_BUS_OVP_FLT_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SC8551_BUS_OCP_FLT_MASK_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SC8551_BUS_OCP_FLT_MASK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SC8551_BUS_OCP_FLT_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SC8551_BUS_OCP_FLT_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SC8551_TSBUS_TSBAT_ALM_MASK_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SC8551_TSBUS_TSBAT_ALM_MASK_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SC8551_TSBUS_TSBAT_ALM_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SC8551_TSBUS_TSBAT_ALM_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SC8551_TSBAT_FLT_MASK_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SC8551_TSBAT_FLT_MASK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SC8551_TSBAT_FLT_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SC8551_TSBAT_FLT_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SC8551_TSBUS_FLT_MASK_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SC8551_TSBUS_FLT_MASK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SC8551_TSBUS_FLT_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SC8551_TSBUS_FLT_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SC8551_TDIE_ALM_MASK_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SC8551_TDIE_ALM_MASK_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SC8551_TDIE_ALM_MASK_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SC8551_TDIE_ALM_MASK_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Register 13h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SC8551_REG_13 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SC8551_DEV_ID_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SC8551_DEV_ID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Register 14h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SC8551_REG_14 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SC8551_ADC_EN_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SC8551_ADC_EN_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SC8551_ADC_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SC8551_ADC_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SC8551_ADC_RATE_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SC8551_ADC_RATE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SC8551_ADC_RATE_CONTINOUS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SC8551_ADC_RATE_ONESHOT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SC8551_IBUS_ADC_DIS_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SC8551_IBUS_ADC_DIS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SC8551_IBUS_ADC_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SC8551_IBUS_ADC_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Register 15h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SC8551_REG_15 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SC8551_VBUS_ADC_DIS_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SC8551_VBUS_ADC_DIS_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SC8551_VBUS_ADC_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SC8551_VBUS_ADC_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SC8551_VAC_ADC_DIS_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SC8551_VAC_ADC_DIS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SC8551_VAC_ADC_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define SC8551_VAC_ADC_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SC8551_VOUT_ADC_DIS_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SC8551_VOUT_ADC_DIS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SC8551_VOUT_ADC_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SC8551_VOUT_ADC_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SC8551_VBAT_ADC_DIS_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SC8551_VBAT_ADC_DIS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SC8551_VBAT_ADC_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SC8551_VBAT_ADC_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SC8551_IBAT_ADC_DIS_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SC8551_IBAT_ADC_DIS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SC8551_IBAT_ADC_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SC8551_IBAT_ADC_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SC8551_TSBUS_ADC_DIS_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SC8551_TSBUS_ADC_DIS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SC8551_TSBUS_ADC_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SC8551_TSBUS_ADC_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SC8551_TSBAT_ADC_DIS_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SC8551_TSBAT_ADC_DIS_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SC8551_TSBAT_ADC_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SC8551_TSBAT_ADC_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SC8551_TDIE_ADC_DIS_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SC8551_TDIE_ADC_DIS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SC8551_TDIE_ADC_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SC8551_TDIE_ADC_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Register 16h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SC8551_REG_16 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SC8551_IBUS_POL_H_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Register 17h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SC8551_REG_17 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SC8551_IBUS_POL_L_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Register 18h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SC8551_REG_18 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SC8551_VBUS_POL_H_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Register 19h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SC8551_REG_19 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SC8551_VBUS_POL_L_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Register 1Ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SC8551_REG_1A 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SC8551_VAC_POL_H_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Register 1Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define SC8551_REG_1B 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SC8551_VAC_POL_L_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Register 1Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SC8551_REG_1C 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SC8551_VOUT_POL_H_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Register 1Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SC8551_REG_1D 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SC8551_VOUT_POL_L_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Register 1Eh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define SC8551_REG_1E 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SC8551_VBAT_POL_H_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Register 1Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SC8551_REG_1F 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SC8551_VBAT_POL_L_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Register 20h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SC8551_REG_20 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SC8551_IBAT_POL_H_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Register 21h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SC8551_REG_21 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SC8551_IBAT_POL_L_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Register 26h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SC8551_REG_26 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SC8551_TDIE_POL_H_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Register 2Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SC8551_REG_2B 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SC8551_SS_TIMEOUT_SET_MASK 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define SC8551_SS_TIMEOUT_SET_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SC8551_SS_TIMEOUT_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SC8551_SS_TIMEOUT_12P5MS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SC8551_SS_TIMEOUT_25MS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SC8551_SS_TIMEOUT_50MS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SC8551_SS_TIMEOUT_100MS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define SC8551_SS_TIMEOUT_400MS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define SC8551_SS_TIMEOUT_1500MS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SC8551_SS_TIMEOUT_100000MS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SC8551_EN_REGULATION_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SC8551_EN_REGULATION_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SC8551_EN_REGULATION_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SC8551_EN_REGULATION_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SC8551_VOUT_OVP_DIS_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SC8551_VOUT_OVP_DIS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SC8551_VOUT_OVP_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SC8551_VOUT_OVP_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SC8551_IBUS_UCP_RISE_TH_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SC8551_IBUS_UCP_RISE_TH_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SC8551_IBUS_UCP_RISE_150MA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SC8551_IBUS_UCP_RISE_250MA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SC8551_SET_IBAT_SNS_RES_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SC8551_SET_IBAT_SNS_RES_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SC8551_SET_IBAT_SNS_RES_2MHM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SC8551_SET_IBAT_SNS_RES_5MHM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SC8551_VAC_PD_EN_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SC8551_VAC_PD_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SC8551_VAC_PD_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SC8551_VAC_PD_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Register 2Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SC8551_REG_2C 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SC8551_IBAT_REG_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SC8551_IBAT_REG_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SC8551_IBAT_REG_200MA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SC8551_IBAT_REG_300MA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SC8551_IBAT_REG_400MA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SC8551_IBAT_REG_500MA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SC8551_VBAT_REG_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SC8551_VBAT_REG_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SC8551_VBAT_REG_50MV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SC8551_VBAT_REG_100MV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SC8551_VBAT_REG_150MV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define SC8551_VBAT_REG_200MV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SC8551_VBAT_REG_ACTIVE_STAT_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SC8551_IBAT_REG_ACTIVE_STAT_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SC8551_VDROP_OVP_ACTIVE_STAT_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SC8551_VOUT_OVP_ACTIVE_STAT_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SC8551_REG_2D 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define SC8551_VBAT_REG_ACTIVE_FLAG_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SC8551_IBAT_REG_ACTIVE_FLAG_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SC8551_VDROP_OVP_FLAG_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SC8551_VOUT_OVP_FLAG_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SC8551_VBAT_REG_ACTIVE_MASK_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SC8551_IBAT_REG_ACTIVE_MASK_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SC8551_VDROP_OVP_MASK_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SC8551_VOUT_OVP_MASK_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define SC8551_REG_2E 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SC8551_IBUS_LOW_DG_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SC8551_IBUS_LOW_DG_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SC8551_IBUS_LOW_DG_10US 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SC8551_IBUS_LOW_DG_5MS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define SC8551_REG_2F 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define SC8551_PMID2OUT_UVP_FLAG_MASK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define SC8551_PMID2OUT_OVP_FLAG_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define SC8551_PMID2OUT_UVP_STAT_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SC8551_PMID2OUT_OVP_STAT_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define SC8551_REG_30 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define SC8551_IBUS_REG_EN_MASK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SC8551_IBUS_REG_EN_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SC8551_IBUS_REG_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SC8551_IBUS_REG_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SC8551_IBUS_REG_ACTIVE_STAT_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SC8551_IBUS_REG_ACTIVE_FLAG_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define SC8551_IBUS_REG_ACTIVE_MASK_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SC8551_IBUS_REG_ACTIVE_MASK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SC8551_IBUS_REG_ACTIVE_NOT_MASK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SC8551_IBUS_REG_ACTIVE_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define SC8551_IBUS_REG_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define SC8551_IBUS_REG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SC8551_IBUS_REG_BASE 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define SC8551_IBUS_REG_LSB 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define SC8551_REG_31 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define SC8551_CHARGE_MODE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define SC8551_CHARGE_MODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define SC8551_CHARGE_MODE_2_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SC8551_CHARGE_MODE_1_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SC8551_REG_35 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SC8551_VBUS_IN_RANGE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SC8551_VBUS_IN_RANGE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SC8551_VBUS_IN_RANGE_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define SC8551_VBUS_IN_RANGE_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define SC8551_REG_36 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define SC8551_OVPGATE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define SC8551_OVPGATE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define SC8551_OVPGATE_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SC8551_OVPGATE_DISABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define VBUS_INSERT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define VBAT_INSERT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define ADC_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define BAT_OVP_FAULT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define BAT_OCP_FAULT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define BUS_OVP_FAULT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define BUS_OCP_FAULT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*below used for comm with other module*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define BAT_OVP_FAULT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define BAT_OCP_FAULT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define BUS_OVP_FAULT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define BUS_OCP_FAULT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define BAT_THERM_FAULT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define BUS_THERM_FAULT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define DIE_THERM_FAULT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define BAT_OVP_FAULT_MASK (1 << BAT_OVP_FAULT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define BAT_OCP_FAULT_MASK (1 << BAT_OCP_FAULT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define BUS_OVP_FAULT_MASK (1 << BUS_OVP_FAULT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define BUS_OCP_FAULT_MASK (1 << BUS_OCP_FAULT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define BAT_THERM_FAULT_MASK (1 << BAT_THERM_FAULT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define BUS_THERM_FAULT_MASK (1 << BUS_THERM_FAULT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define DIE_THERM_FAULT_MASK (1 << DIE_THERM_FAULT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define BAT_OVP_ALARM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define BAT_OCP_ALARM_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define BUS_OVP_ALARM_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define BUS_OCP_ALARM_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define BAT_THERM_ALARM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define BUS_THERM_ALARM_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define DIE_THERM_ALARM_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define BAT_UCP_ALARM_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define BAT_OVP_ALARM_MASK (1 << BAT_OVP_ALARM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define BAT_OCP_ALARM_MASK (1 << BAT_OCP_ALARM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define BUS_OVP_ALARM_MASK (1 << BUS_OVP_ALARM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define BUS_OCP_ALARM_MASK (1 << BUS_OCP_ALARM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define BAT_THERM_ALARM_MASK (1 << BAT_THERM_ALARM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define BUS_THERM_ALARM_MASK (1 << BUS_THERM_ALARM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define DIE_THERM_ALARM_MASK (1 << DIE_THERM_ALARM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define BAT_UCP_ALARM_MASK (1 << BAT_UCP_ALARM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define VBAT_REG_STATUS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define IBAT_REG_STATUS_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define VBAT_REG_STATUS_MASK (1 << VBAT_REG_STATUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define IBAT_REG_STATUS_MASK (1 << VBAT_REG_STATUS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define SC8551_DEBUG_BUF_LEN 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ADC_IBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ADC_VBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ADC_VAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ADC_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ADC_VBAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ADC_IBAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ADC_TBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ADC_TBAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ADC_TDIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ADC_MAX_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct sc8551_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) bool bat_ovp_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) bool bat_ocp_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int bat_ovp_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int bat_ovp_alm_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int bat_ocp_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) bool bus_ocp_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int bus_ovp_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int bus_ocp_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int ac_ovp_th;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) bool bat_therm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) bool bus_therm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) bool die_therm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int sense_r_mohm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct sc8551 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int part_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct mutex data_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct mutex i2c_rw_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) bool batt_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) bool vbus_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) bool usb_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) bool charge_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int vbus_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* ADC reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int vbat_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int vbus_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int vout_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int vac_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int ibat_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int ibus_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int die_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* alarm/fault status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) bool bat_ovp_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) bool bat_ocp_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) bool bus_ovp_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) bool bus_ocp_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) bool vbat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) bool ibat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int prev_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int prev_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct sc8551_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct power_supply_desc psy_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct power_supply_config psy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct power_supply *fc2_psy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int __sc8551_read_byte(struct sc8551 *sc, u8 reg, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = i2c_smbus_read_byte_data(sc->client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(sc->dev, "i2c read fail: can't read from reg 0x%02X\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *data = (u8) ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int __sc8551_write_byte(struct sc8551 *sc, int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ret = i2c_smbus_write_byte_data(sc->client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_err(sc->dev, "i2c write fail: can't write 0x%02X to reg 0x%02X: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) val, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int sc8551_read_byte(struct sc8551 *sc, u8 reg, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) mutex_lock(&sc->i2c_rw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = __sc8551_read_byte(sc, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) mutex_unlock(&sc->i2c_rw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int sc8551_write_byte(struct sc8551 *sc, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mutex_lock(&sc->i2c_rw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = __sc8551_write_byte(sc, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mutex_unlock(&sc->i2c_rw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int sc8551_update_bits(struct sc8551 *sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u8 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mutex_lock(&sc->i2c_rw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = __sc8551_read_byte(sc, reg, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_err(sc->dev, "Failed: reg=%02X, ret=%d\n", reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) tmp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) tmp |= data & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = __sc8551_write_byte(sc, reg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_err(sc->dev, "Failed: reg=%02X, ret=%d\n", reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) mutex_unlock(&sc->i2c_rw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int sc8551_enable_charge(struct sc8551 *sc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) val = SC8551_CHG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) val = SC8551_CHG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) val <<= SC8551_CHG_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) SC8551_REG_0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) SC8551_CHG_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int sc8551_check_charge_enabled(struct sc8551 *sc, bool *enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = sc8551_read_byte(sc, SC8551_REG_0C, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) *enabled = !!(val & SC8551_CHG_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static int sc8551_enable_wdt(struct sc8551 *sc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) val = SC8551_WATCHDOG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) val = SC8551_WATCHDOG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) val <<= SC8551_WATCHDOG_DIS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) SC8551_REG_0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) SC8551_WATCHDOG_DIS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int sc8551_set_wdt(struct sc8551 *sc, int ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ms == 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) val = SC8551_WATCHDOG_0P5S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) else if (ms == 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) val = SC8551_WATCHDOG_1S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) else if (ms == 5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) val = SC8551_WATCHDOG_5S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) else if (ms == 30000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) val = SC8551_WATCHDOG_30S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) val = SC8551_WATCHDOG_30S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) val <<= SC8551_WATCHDOG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SC8551_REG_0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) SC8551_WATCHDOG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int sc8551_enable_batovp(struct sc8551 *sc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) val = SC8551_BAT_OVP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) val = SC8551_BAT_OVP_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) val <<= SC8551_BAT_OVP_DIS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SC8551_REG_00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) SC8551_BAT_OVP_DIS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static int sc8551_set_batovp_th(struct sc8551 *sc, int threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (threshold < SC8551_BAT_OVP_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) threshold = SC8551_BAT_OVP_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) val = (threshold - SC8551_BAT_OVP_BASE) / SC8551_BAT_OVP_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) val <<= SC8551_BAT_OVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) SC8551_REG_00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) SC8551_BAT_OVP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int sc8551_enable_batocp(struct sc8551 *sc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) val = SC8551_BAT_OCP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) val = SC8551_BAT_OCP_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) val <<= SC8551_BAT_OCP_DIS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) SC8551_REG_02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) SC8551_BAT_OCP_DIS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static int sc8551_set_batocp_th(struct sc8551 *sc, int threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (threshold < SC8551_BAT_OCP_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) threshold = SC8551_BAT_OCP_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) val = (threshold - SC8551_BAT_OCP_BASE) / SC8551_BAT_OCP_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) val <<= SC8551_BAT_OCP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) SC8551_REG_02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) SC8551_BAT_OCP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int sc8551_set_busovp_th(struct sc8551 *sc, int threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (threshold < SC8551_BUS_OVP_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) threshold = SC8551_BUS_OVP_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) val = (threshold - SC8551_BUS_OVP_BASE) / SC8551_BUS_OVP_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) val <<= SC8551_BUS_OVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) SC8551_REG_06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) SC8551_BUS_OVP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static int sc8551_enable_busocp(struct sc8551 *sc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) val = SC8551_BUS_OCP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) val = SC8551_BUS_OCP_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) val <<= SC8551_BUS_OCP_DIS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) SC8551_REG_08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) SC8551_BUS_OCP_DIS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static int sc8551_set_busocp_th(struct sc8551 *sc, int threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (threshold < SC8551_BUS_OCP_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) threshold = SC8551_BUS_OCP_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) val = (threshold - SC8551_BUS_OCP_BASE) / SC8551_BUS_OCP_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) val <<= SC8551_BUS_OCP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) SC8551_REG_08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) SC8551_BUS_OCP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int sc8551_set_acovp_th(struct sc8551 *sc, int threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (threshold < SC8551_AC_OVP_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) threshold = SC8551_AC_OVP_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (threshold == SC8551_AC_OVP_6P5V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) val = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) val = (threshold - SC8551_AC_OVP_BASE) / SC8551_AC_OVP_LSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) val <<= SC8551_AC_OVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ret = sc8551_update_bits(sc, SC8551_REG_05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) SC8551_AC_OVP_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int sc8551_set_vdrop_th(struct sc8551 *sc, int threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (threshold == 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) val = SC8551_VDROP_THRESHOLD_300MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) val = SC8551_VDROP_THRESHOLD_400MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) val <<= SC8551_VDROP_THRESHOLD_SET_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ret = sc8551_update_bits(sc, SC8551_REG_05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) SC8551_VDROP_THRESHOLD_SET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int sc8551_set_vdrop_deglitch(struct sc8551 *sc, int us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (us == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) val = SC8551_VDROP_DEGLITCH_8US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) val = SC8551_VDROP_DEGLITCH_5MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) val <<= SC8551_VDROP_DEGLITCH_SET_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) SC8551_REG_05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) SC8551_VDROP_DEGLITCH_SET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int sc8551_enable_bat_therm(struct sc8551 *sc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) val = SC8551_TSBAT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) val = SC8551_TSBAT_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) val <<= SC8551_TSBAT_DIS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret = sc8551_update_bits(sc, SC8551_REG_0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) SC8551_TSBAT_DIS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static int sc8551_enable_bus_therm(struct sc8551 *sc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) val = SC8551_TSBUS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) val = SC8551_TSBUS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) val <<= SC8551_TSBUS_DIS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ret = sc8551_update_bits(sc, SC8551_REG_0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) SC8551_TSBUS_DIS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static int sc8551_enable_adc(struct sc8551 *sc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) val = SC8551_ADC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) val = SC8551_ADC_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) val <<= SC8551_ADC_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ret = sc8551_update_bits(sc, SC8551_REG_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) SC8551_ADC_EN_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static int sc8551_set_adc_scanrate(struct sc8551 *sc, bool oneshot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (oneshot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) val = SC8551_ADC_RATE_ONESHOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) val = SC8551_ADC_RATE_CONTINOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) val <<= SC8551_ADC_RATE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret = sc8551_update_bits(sc, SC8551_REG_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SC8551_ADC_RATE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static int sc8551_get_adc_data(struct sc8551 *sc, int channel, int *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) u8 val_l = 0, val_h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) u16 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (channel >= ADC_MAX_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret = sc8551_read_byte(sc, SC8551_REG_16 + (channel << 1), &val_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = sc8551_read_byte(sc, SC8551_REG_16 + (channel << 1) + 1, &val_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) val = (val_h << 8) | val_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (channel == ADC_IBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) val = val * 15625 / 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) else if (channel == ADC_VBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) val = val * 375 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) else if (channel == ADC_VAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) val = val * 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) else if (channel == ADC_VOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) val = val * 125 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) else if (channel == ADC_VBAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) val = val * 125 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) else if (channel == ADC_IBAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) val = val * 3125 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) else if (channel == ADC_TDIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) val = val * 5 / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) *result = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static int sc8551_set_adc_scan(struct sc8551 *sc, int channel, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (channel > ADC_MAX_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (channel == ADC_IBUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) reg = SC8551_REG_14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) shift = SC8551_IBUS_ADC_DIS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) mask = SC8551_IBUS_ADC_DIS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) reg = SC8551_REG_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) shift = 8 - channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) mask = 1 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) val = 0 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) val = 1 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = sc8551_update_bits(sc, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static int sc8551_set_alarm_int_mask(struct sc8551 *sc, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ret = sc8551_read_byte(sc, SC8551_REG_0F, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = sc8551_write_byte(sc, SC8551_REG_0F, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int sc8551_set_sense_resistor(struct sc8551 *sc, int r_mohm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (r_mohm == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) val = SC8551_SET_IBAT_SNS_RES_2MHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) else if (r_mohm == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) val = SC8551_SET_IBAT_SNS_RES_5MHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) val <<= SC8551_SET_IBAT_SNS_RES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) SC8551_REG_2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) SC8551_SET_IBAT_SNS_RES_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static int sc8551_enable_regulation(struct sc8551 *sc, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) val = SC8551_EN_REGULATION_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) val = SC8551_EN_REGULATION_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) val <<= SC8551_EN_REGULATION_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) SC8551_REG_2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) SC8551_EN_REGULATION_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static int sc8551_set_ss_timeout(struct sc8551 *sc, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) switch (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) val = SC8551_SS_TIMEOUT_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) val = SC8551_SS_TIMEOUT_12P5MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) case 25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) val = SC8551_SS_TIMEOUT_25MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) val = SC8551_SS_TIMEOUT_50MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) case 100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) val = SC8551_SS_TIMEOUT_100MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) case 400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) val = SC8551_SS_TIMEOUT_400MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) case 1500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) val = SC8551_SS_TIMEOUT_1500MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) case 100000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) val = SC8551_SS_TIMEOUT_100000MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) val = SC8551_SS_TIMEOUT_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) val <<= SC8551_SS_TIMEOUT_SET_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) SC8551_REG_2B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) SC8551_SS_TIMEOUT_SET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static int sc8551_set_ibat_reg_th(struct sc8551 *sc, int th_ma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (th_ma == 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) val = SC8551_IBAT_REG_200MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) else if (th_ma == 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) val = SC8551_IBAT_REG_300MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) else if (th_ma == 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) val = SC8551_IBAT_REG_400MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) else if (th_ma == 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) val = SC8551_IBAT_REG_500MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) val = SC8551_IBAT_REG_500MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) val <<= SC8551_IBAT_REG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) SC8551_REG_2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) SC8551_IBAT_REG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static int sc8551_set_vbat_reg_th(struct sc8551 *sc, int th_mv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (th_mv == 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) val = SC8551_VBAT_REG_50MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) else if (th_mv == 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) val = SC8551_VBAT_REG_100MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) else if (th_mv == 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) val = SC8551_VBAT_REG_150MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) val = SC8551_VBAT_REG_200MV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) val <<= SC8551_VBAT_REG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ret = sc8551_update_bits(sc, SC8551_REG_2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) SC8551_VBAT_REG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static int sc8551_get_work_mode(struct sc8551 *sc, int *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ret = sc8551_read_byte(sc, SC8551_REG_0C, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dev_err(sc->dev, "Failed to read operation mode register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) val = (val & SC8551_MS_MASK) >> SC8551_MS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (val == SC8551_MS_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) *mode = SC8551_ROLE_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) else if (val == SC8551_MS_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) *mode = SC8551_ROLE_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) *mode = SC8551_ROLE_STDALONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) pr_debug("work mode:%s\n", *mode == SC8551_ROLE_STDALONE ? "Standalone" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) (*mode == SC8551_ROLE_SLAVE ? "Slave" : "Master"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static int sc8551_check_vbus_error_status(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ret = sc8551_read_byte(sc, SC8551_REG_0A, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) sc->vbus_error = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static void sc8551_check_alarm_status(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u8 flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u8 stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) mutex_lock(&sc->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ret = sc8551_read_byte(sc, SC8551_REG_08, &flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (!ret && (flag & SC8551_IBUS_UCP_FALL_FLAG_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) pr_debug("UCP_FLAG =0x%02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) !!(flag & SC8551_IBUS_UCP_FALL_FLAG_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) ret = sc8551_read_byte(sc, SC8551_REG_2D, &flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (!ret && (flag & SC8551_VDROP_OVP_FLAG_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) pr_debug("VDROP_OVP_FLAG =0x%02X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) !!(flag & SC8551_VDROP_OVP_FLAG_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /*read to clear alarm flag*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ret = sc8551_read_byte(sc, SC8551_REG_0E, &flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (!ret && flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) pr_debug("INT_FLAG =0x%02X\n", flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ret = sc8551_read_byte(sc, SC8551_REG_0D, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (!ret && stat != sc->prev_alarm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) pr_debug("INT_STAT = 0X%02x\n", stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) sc->prev_alarm = stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) sc->batt_present = !!(stat & VBAT_INSERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) sc->vbus_present = !!(stat & VBUS_INSERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ret = sc8551_read_byte(sc, SC8551_REG_08, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (!ret && (stat & 0x50))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) dev_err(sc->dev, "Reg[05]BUS_UCPOVP = 0x%02X\n", stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ret = sc8551_read_byte(sc, SC8551_REG_0A, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (!ret && (stat & 0x02))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) dev_err(sc->dev, "Reg[0A]CONV_OCP = 0x%02X\n", stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) mutex_unlock(&sc->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static void sc8551_check_fault_status(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u8 flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) u8 stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) mutex_lock(&sc->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ret = sc8551_read_byte(sc, SC8551_REG_10, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (!ret && stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) dev_err(sc->dev, "FAULT_STAT = 0x%02X\n", stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = sc8551_read_byte(sc, SC8551_REG_11, &flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (!ret && flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dev_err(sc->dev, "FAULT_FLAG = 0x%02X\n", flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (!ret && flag != sc->prev_fault) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) sc->prev_fault = flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) sc->bat_ovp_fault = !!(flag & BAT_OVP_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) sc->bat_ocp_fault = !!(flag & BAT_OCP_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) sc->bus_ovp_fault = !!(flag & BUS_OVP_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) sc->bus_ocp_fault = !!(flag & BUS_OCP_FAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) mutex_unlock(&sc->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static int sc8551_detect_device(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ret = sc8551_read_byte(sc, SC8551_REG_13, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) sc->part_no = (data & SC8551_DEV_ID_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) sc->part_no >>= SC8551_DEV_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static int sc8551_parse_dt(struct sc8551 *sc, struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) sc->cfg = devm_kzalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) sizeof(struct sc8551_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (!sc->cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) sc->cfg->bat_ovp_disable = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) "sc,sc8551,bat-ovp-disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) sc->cfg->bat_ocp_disable = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) "sc,sc8551,bat-ocp-disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) sc->cfg->bus_ocp_disable = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) "sc,sc8551,bus-ocp-disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) sc->cfg->bat_therm_disable = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) "sc,sc8551,bat-therm-disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) sc->cfg->bus_therm_disable = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) "sc,sc8551,bus-therm-disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ret = of_property_read_u32(np, "sc,sc8551,bat-ovp-threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) &sc->cfg->bat_ovp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dev_err(sc->dev, "failed to read bat-ovp-threshold\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ret = of_property_read_u32(np, "sc,sc8551,bat-ocp-threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) &sc->cfg->bat_ocp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dev_err(sc->dev, "failed to read bat-ocp-threshold\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) ret = of_property_read_u32(np, "sc,sc8551,bus-ovp-threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) &sc->cfg->bus_ovp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) dev_err(sc->dev, "failed to read bus-ovp-threshold\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) ret = of_property_read_u32(np, "sc,sc8551,bus-ocp-threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) &sc->cfg->bus_ocp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) dev_err(sc->dev, "failed to read bus-ocp-threshold\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ret = of_property_read_u32(np, "sc,sc8551,ac-ovp-threshold",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) &sc->cfg->ac_ovp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) dev_err(sc->dev, "failed to read ac-ovp-threshold\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) ret = of_property_read_u32(np, "sc,sc8551,sense-resistor-mohm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) &sc->cfg->sense_r_mohm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) dev_err(sc->dev, "failed to read sense-resistor-mohm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static int sc8551_init_protection(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ret = sc8551_enable_batovp(sc, !sc->cfg->bat_ovp_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) pr_debug("%s bat ovp %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) sc->cfg->bat_ovp_disable ? "disable" : "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ret = sc8551_enable_batocp(sc, !sc->cfg->bat_ocp_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) pr_debug("%s bat ocp %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) sc->cfg->bat_ocp_disable ? "disable" : "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) ret = sc8551_enable_busocp(sc, !sc->cfg->bus_ocp_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pr_debug("%s bus ocp %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) sc->cfg->bus_ocp_disable ? "disable" : "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ret = sc8551_enable_bat_therm(sc, !sc->cfg->bat_therm_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) pr_debug("%s bat therm %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) sc->cfg->bat_therm_disable ? "disable" : "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) ret = sc8551_enable_bus_therm(sc, !sc->cfg->bus_therm_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) pr_debug("%s bus therm %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) sc->cfg->bus_therm_disable ? "disable" : "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ret = sc8551_set_batovp_th(sc, sc->cfg->bat_ovp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) pr_debug("set bat ovp th %d %s\n", sc->cfg->bat_ovp_th,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ret = sc8551_set_batocp_th(sc, sc->cfg->bat_ocp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) pr_debug("set bat ocp threshold %d %s\n", sc->cfg->bat_ocp_th,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ret = sc8551_set_busovp_th(sc, sc->cfg->bus_ovp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) pr_debug("set bus ovp threshold %d %s\n", sc->cfg->bus_ovp_th,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ret = sc8551_set_busocp_th(sc, sc->cfg->bus_ocp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) pr_debug("set bus ocp threshold %d %s\n", sc->cfg->bus_ocp_th,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ret = sc8551_set_acovp_th(sc, sc->cfg->ac_ovp_th);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) pr_debug("set ac ovp threshold %d %s\n", sc->cfg->ac_ovp_th,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) !ret ? "successfully" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static int sc8551_init_adc(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ret = sc8551_set_adc_scanrate(sc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ret = sc8551_set_adc_scan(sc, ADC_IBUS, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ret = sc8551_set_adc_scan(sc, ADC_VBUS, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ret = sc8551_set_adc_scan(sc, ADC_VOUT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ret = sc8551_set_adc_scan(sc, ADC_VBAT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ret = sc8551_set_adc_scan(sc, ADC_IBAT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ret = sc8551_set_adc_scan(sc, ADC_TBUS, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ret = sc8551_set_adc_scan(sc, ADC_TBAT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ret = sc8551_set_adc_scan(sc, ADC_TDIE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ret = sc8551_set_adc_scan(sc, ADC_VAC, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) ret = sc8551_enable_adc(sc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static int sc8551_init_int_src(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /*TODO:be careful ts bus and ts bat alarm bit mask is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * fault mask register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ret = sc8551_set_alarm_int_mask(sc, ADC_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) dev_err(sc->dev, "failed to set alarm mask:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static int sc8551_init_regulation(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret = sc8551_set_ibat_reg_th(sc, 300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ret = sc8551_set_vbat_reg_th(sc, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ret = sc8551_set_vdrop_deglitch(sc, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) ret = sc8551_set_vdrop_th(sc, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ret = sc8551_enable_regulation(sc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ret = sc8551_write_byte(sc, SC8551_REG_2E, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static int sc8551_init_device(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /* Reset registers to their default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) ret = sc8551_update_bits(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) SC8551_REG_0B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) SC8551_REG_RST_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) SC8551_REG_RST_ENABLE << SC8551_REG_RST_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ret = sc8551_enable_wdt(sc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) ret = sc8551_set_wdt(sc, 30000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) ret = sc8551_set_ss_timeout(sc, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) ret = sc8551_set_sense_resistor(sc, sc->cfg->sense_r_mohm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) ret = sc8551_init_protection(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ret = sc8551_init_adc(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) ret = sc8551_init_int_src(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret = sc8551_init_regulation(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static int sc8551_set_present(struct sc8551 *sc, bool present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) sc->usb_present = present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) sc8551_init_device(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static ssize_t registers_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) struct sc8551 *sc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) u8 tmpbuf[SC8551_DEBUG_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) u8 addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) int len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) ret = sc8551_get_adc_data(sc, ADC_VBAT, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) sc->vbat_volt = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) ret = sc8551_get_adc_data(sc, ADC_VAC, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) sc->vac_volt = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) ret = sc8551_get_adc_data(sc, ADC_VBUS, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) sc->vbus_volt = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ret = sc8551_get_adc_data(sc, ADC_VOUT, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) sc->vout_volt = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ret = sc8551_get_adc_data(sc, ADC_IBUS, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) sc->ibus_curr = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ret = sc8551_get_adc_data(sc, ADC_TDIE, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) sc->die_temp = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ret = sc8551_get_adc_data(sc, ADC_IBAT, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) sc->ibat_curr = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) dev_err(sc->dev, "vbus_vol %d vbat_vol(vout) %d vout %d, vac: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) sc->vbus_volt, sc->vbat_volt, sc->vout_volt, sc->vac_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) dev_err(sc->dev, "ibus_curr %d ibat_curr %d\n", sc->ibus_curr, sc->ibat_curr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) dev_err(sc->dev, "die_temp %d\n", sc->die_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) for (addr = SC8551_REG_00; addr <= SC8551_REG_36; addr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ret = sc8551_read_byte(sc, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) len = snprintf(tmpbuf, SC8551_DEBUG_BUF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) "Reg[%.2X] = 0x%.2x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) memcpy(&buf[idx], tmpbuf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) idx += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static ssize_t registers_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct sc8551 *sc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ret = sscanf(buf, "%x %x", ®, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if ((ret == 2) && (reg >= SC8551_REG_00) && (reg <= SC8551_REG_36))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) sc8551_write_byte(sc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) (unsigned char)reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) (unsigned char)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static DEVICE_ATTR_RW(registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static void sc8551_create_device_node(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) device_create_file(dev, &dev_attr_registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) static enum power_supply_property sc8551_charger_props[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) POWER_SUPPLY_PROP_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) POWER_SUPPLY_PROP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) POWER_SUPPLY_PROP_CP_CHARGING_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) POWER_SUPPLY_PROP_ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) POWER_SUPPLY_PROP_VOLTAGE_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) POWER_SUPPLY_PROP_CURRENT_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) POWER_SUPPLY_PROP_CP_DIE_TEMPERATURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) POWER_SUPPLY_PROP_CP_BAT_OVP_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) POWER_SUPPLY_PROP_CP_BAT_OCP_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) POWER_SUPPLY_PROP_CP_BUS_OVP_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) POWER_SUPPLY_PROP_CP_BUS_OCP_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) POWER_SUPPLY_PROP_CP_VBUS_HERROR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) POWER_SUPPLY_PROP_CP_VBUS_LERROR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static int sc8551_charger_get_property(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) enum power_supply_property psp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) struct sc8551 *sc = power_supply_get_drvdata(psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) sc8551_check_alarm_status(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) sc8551_check_fault_status(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) sc8551_check_vbus_error_status(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) switch (psp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) case POWER_SUPPLY_PROP_CP_CHARGING_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) sc8551_check_charge_enabled(sc, &sc->charge_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) val->intval = sc->charge_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) case POWER_SUPPLY_PROP_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) val->intval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) case POWER_SUPPLY_PROP_PRESENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) val->intval = sc->usb_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) case POWER_SUPPLY_PROP_ONLINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) ret = sc8551_read_byte(sc, SC8551_REG_0D, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) sc->vbus_present = !!(reg_val & VBUS_INSERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) val->intval = sc->vbus_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) case POWER_SUPPLY_PROP_VOLTAGE_NOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ret = sc8551_get_adc_data(sc, ADC_VBAT, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) sc->vbat_volt = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) val->intval = sc->vbat_volt * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) case POWER_SUPPLY_PROP_CURRENT_NOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ret = sc8551_get_adc_data(sc, ADC_IBAT, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) sc->ibat_curr = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) val->intval = sc->ibat_curr * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) case POWER_SUPPLY_PROP_CP_VBUS: /* BUS_VOLTAGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ret = sc8551_get_adc_data(sc, ADC_VBUS, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) sc->vbus_volt = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) val->intval = sc->vbus_volt * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) case POWER_SUPPLY_PROP_CP_IBUS: /* BUS_CURRENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ret = sc8551_get_adc_data(sc, ADC_IBUS, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) sc->ibus_curr = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) val->intval = sc->ibus_curr * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT: /* BUS_VOLTAGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) val->intval = 12000 * 1000; /* 20V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT: /* BUS_CURRENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) val->intval = 4500 * 1000; /* 4.75A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) case POWER_SUPPLY_PROP_CP_DIE_TEMPERATURE:/* DIE_TEMPERATURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) ret = sc8551_get_adc_data(sc, ADC_TDIE, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) sc->die_temp = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) val->intval = sc->die_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) case POWER_SUPPLY_PROP_VOLTAGE_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) val->intval = 4300 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) val->intval = 8000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) case POWER_SUPPLY_PROP_CP_BAT_OVP_FAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) val->intval = sc->bat_ovp_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) case POWER_SUPPLY_PROP_CP_BAT_OCP_FAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) val->intval = sc->bat_ocp_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) case POWER_SUPPLY_PROP_CP_BUS_OVP_FAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) val->intval = sc->bus_ovp_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) case POWER_SUPPLY_PROP_CP_BUS_OCP_FAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) val->intval = sc->bus_ocp_fault;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) case POWER_SUPPLY_PROP_CP_VBUS_HERROR_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) val->intval = (sc->vbus_error >> 0x04) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) case POWER_SUPPLY_PROP_CP_VBUS_LERROR_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) val->intval = (sc->vbus_error >> 0x05) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static int sc8551_charger_set_property(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) enum power_supply_property prop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) const union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) struct sc8551 *sc = power_supply_get_drvdata(psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) switch (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) case POWER_SUPPLY_PROP_CP_CHARGING_ENABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) sc8551_enable_charge(sc, val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (val->intval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) sc8551_enable_wdt(sc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) sc8551_enable_wdt(sc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) sc8551_check_charge_enabled(sc, &sc->charge_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) case POWER_SUPPLY_PROP_PRESENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) sc8551_set_present(sc, !!val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) static int sc8551_charger_is_writeable(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) enum power_supply_property prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) switch (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) case POWER_SUPPLY_PROP_ONLINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static int sc8551_psy_register(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) sc->psy_cfg.drv_data = sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) sc->psy_cfg.of_node = sc->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) sc->psy_desc.name = "sc8551-standalone";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) sc->psy_desc.type = POWER_SUPPLY_TYPE_CHARGE_PUMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) sc->psy_desc.properties = sc8551_charger_props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) sc->psy_desc.num_properties = ARRAY_SIZE(sc8551_charger_props);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) sc->psy_desc.get_property = sc8551_charger_get_property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) sc->psy_desc.set_property = sc8551_charger_set_property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) sc->psy_desc.property_is_writeable = sc8551_charger_is_writeable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) sc->fc2_psy = devm_power_supply_register(sc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) &sc->psy_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) &sc->psy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (IS_ERR(sc->fc2_psy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) dev_err(sc->dev, "failed to register fc2_psy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return PTR_ERR(sc->fc2_psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) * interrupt does nothing, just info event change, other module could get info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) * through power supply interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static irqreturn_t sc8551_charger_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) struct sc8551 *sc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) int ret, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) ret = sc8551_get_adc_data(sc, ADC_VOUT, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) sc->vbat_volt = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ret = sc8551_get_adc_data(sc, ADC_IBAT, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) sc->ibat_curr = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ret = sc8551_get_adc_data(sc, ADC_VBUS, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) sc->vbus_volt = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) ret = sc8551_get_adc_data(sc, ADC_IBUS, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) sc->ibus_curr = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) ret = sc8551_get_adc_data(sc, ADC_TDIE, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) sc->die_temp = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ret = sc8551_get_adc_data(sc, ADC_IBAT, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) sc->ibat_curr = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) sc8551_check_alarm_status(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) sc8551_check_fault_status(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) sc8551_check_vbus_error_status(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) power_supply_changed(sc->fc2_psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static int sc8551_init_irq(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) sc->irq = sc->client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (sc->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) dev_err(sc->dev, "irq mapping fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) ret = devm_request_threaded_irq(sc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) sc->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) sc8551_charger_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) "sc8551 standalone irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) dev_err(sc->dev, "request irq for irq=%d failed, ret =%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) sc->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) enable_irq_wake(sc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) device_init_wakeup(sc->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) static void determine_initial_status(struct sc8551 *sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) if (sc->client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) sc8551_charger_interrupt(sc->client->irq, sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) static const struct of_device_id sc8551_charger_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) { .compatible = "sc,sc8551-standalone", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static int sc8551_charger_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) struct sc8551 *sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) struct device_node *node = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) sc = devm_kzalloc(&client->dev, sizeof(struct sc8551), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (!sc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) sc->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) sc->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) mutex_init(&sc->i2c_rw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) mutex_init(&sc->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) ret = sc8551_detect_device(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) dev_err(sc->dev, "No sc8551 device found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) i2c_set_clientdata(client, sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) match = of_match_node(sc8551_charger_match, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) if (match == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) dev_err(sc->dev, "device tree match not found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) sc8551_get_work_mode(sc, &sc->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (sc->mode != SC8551_ROLE_STDALONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) dev_err(sc->dev, "device operation mode mismatch with dts configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) ret = sc8551_parse_dt(sc, &client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ret = sc8551_init_device(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) dev_err(sc->dev, "Failed to init device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) ret = sc8551_psy_register(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) ret = sc8551_init_irq(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) goto err_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) determine_initial_status(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) sc8551_create_device_node(&(client->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) err_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) power_supply_unregister(sc->fc2_psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static int sc8551_charger_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) struct sc8551 *sc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) sc8551_enable_adc(sc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) power_supply_unregister(sc->fc2_psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) mutex_destroy(&sc->data_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) mutex_destroy(&sc->i2c_rw_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static void sc8551_charger_shutdown(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) struct sc8551 *sc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) sc8551_enable_adc(sc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) static const struct i2c_device_id sc8551_charger_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) {"sc8551-standalone", SC8551_ROLE_STDALONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) static struct i2c_driver sc8551_charger_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .name = "sc8551-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .of_match_table = sc8551_charger_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .id_table = sc8551_charger_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .probe = sc8551_charger_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .remove = sc8551_charger_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .shutdown = sc8551_charger_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) module_i2c_driver(sc8551_charger_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) MODULE_DESCRIPTION("SC SC8551 Charge Pump Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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