^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * rk818_battery.h: fuel gauge driver structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2016 Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: chenjh <chenjh@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * under the terms and conditions of the GNU General Public License,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * version 2, as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed in the hope it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef RK818_BATTERY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK818_BATTERY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* RK818_INT_STS_MSK_REG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLUG_IN_MSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PLUG_OUT_MSK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CHRG_CVTLMT_INT_MSK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* RK818_TS_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GG_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ADC_CUR_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADC_TS1_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADC_TS2_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TS1_CUR_MSK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* RK818_GGCON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OCV_SAMP_MIN_MSK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OCV_SAMP_8MIN (0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ADC_CAL_MIN_MSK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ADC_CAL_8MIN (0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ADC_CUR_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* RK818_GGSTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BAT_CON BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RELAX_VOL1_UPD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RELAX_VOL2_UPD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RELAX_VOL12_UPD_MSK (RELAX_VOL1_UPD | RELAX_VOL2_UPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* RK818_SUP_STS_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHRG_STATUS_MSK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BAT_EXS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CHARGE_OFF (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DEAD_CHARGE (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TRICKLE_CHARGE (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CC_OR_CV (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CHARGE_FINISH (0x4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USB_OVER_VOL (0x5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BAT_TMP_ERR (0x6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TIMER_ERR (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define USB_VLIMIT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USB_CLIMIT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USB_EXIST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define USB_EFF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* RK818_USB_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CHRG_CT_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FINISH_CUR_MSK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEMP_105C (0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FINISH_100MA (0x00 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FINISH_150MA (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FINISH_200MA (0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FINISH_250MA (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* RK818_CHRG_CTRL_REG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CHRG_TERM_MODE_MSK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CHRG_TERM_ANA_SIGNAL (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CHRG_TERM_DIG_SIGNAL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CHRG_TIMER_CCCV_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CHRG_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* RK818_VB_MON_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RK818_VBAT_LOW_3V0 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RK818_VBAT_LOW_3V4 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PLUG_IN_STS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* RK818_THERMAL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FB_TEMP_MSK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HOTDIE_STS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* RK818_INT_STS_MSK_REG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VB_LOW_INT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* RK818_MISC_MARK_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FG_INIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FG_RESET_LATE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FG_RESET_NOW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ALGO_REST_MODE_MSK (0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ALGO_REST_MODE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* bit shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FB_TEMP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* parse ocv table param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TIMER_MS_COUNTS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAX_PERCENTAGE 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MAX_INTERPOLATE 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MAX_INT 0x7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRIVER_VERSION "7.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct battery_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 *ocv_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 *zero_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 *ntc_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 ocv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 max_chrg_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 ntc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ntc_degree_from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 pwroff_vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 monitor_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 zero_algorithm_vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 zero_reserve_dsoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 bat_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 design_capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 design_qmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 sleep_enter_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 sleep_exit_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 max_soc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 sample_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 bat_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 fb_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 energy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 cccv_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 ntc_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 ntc_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) enum work_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MODE_ZERO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODE_FINISH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MODE_SMOOTH_CHRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MODE_SMOOTH_DISCHRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MODE_SMOOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum bat_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODE_BATTARY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MODE_VIRTUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const u16 feedback_temp_array[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 85, 95, 105, 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const u16 chrg_vol_sel_array[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 4050, 4100, 4150, 4200, 4250, 4300, 4350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const u16 chrg_cur_sel_array[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 1000, 1200, 1400, 1600, 1800, 2000, 2250, 2400, 2600, 2800, 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const u16 chrg_cur_input_array[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 450, 80, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void kernel_power_off(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int rk818_bat_temp_notifier_register(struct notifier_block *nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int rk818_bat_temp_notifier_unregister(struct notifier_block *nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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