Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * rk816_battery.h: fuel gauge driver structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2016 Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: chenjh <chenjh@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * under the terms and conditions of the GNU General Public License,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * version 2, as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is distributed in the hope it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #ifndef RK816_BATTERY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define RK816_BATTERY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*TS_CTRL_REG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define GG_EN			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ADC_CUR_EN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ADC_TS1_EN		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ADC_TS2_EN		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*GGCON*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ADC_CUR_MODE		(0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AVG_CUR_MODE		(0x00 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ADC_CAL_MIN_MSK		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ADC_CAL_8MIN		(0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OCV_SAMP_MIN_MSK	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OCV_SAMP_8MIN		(0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /*GGSTS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define FCC_LOCK		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define BAT_CON			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RELAX_STS		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RELAX_VOL1_UPD		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define RELAX_VOL2_UPD		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RELAX_VOL12_UPD_MSK	(RELAX_VOL1_UPD | RELAX_VOL2_UPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /*SUP_STS_REG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define BAT_EXS			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CHARGE_OFF		(0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DEAD_CHARGE		(0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TRICKLE_CHARGE		(0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CC_OR_CV		(0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CHARGE_FINISH		(0x04 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define USB_OVER_VOL		(0x05 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define BAT_TMP_ERR		(0x06 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TIMER_ERR		(0x07 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define USB_EXIST		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define USB_EFF			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define USB_VLIMIT_EN		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define USB_CLIMIT_EN		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CHRG_STATUS_MSK		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /*USB_CTRL_REG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CHRG_CT_EN		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define INPUT_CUR_MSK		(0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define FINISH_CUR_MSK		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CHRG_CUR_MSK		(0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* BAT_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define USB_SYS_EN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* THERMAL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define FB_TEMP_MSK		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define HOTDIE_STS		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /*CHGR_CUR_INPUT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define INPUT_CUR450MA		(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define INPUT_CUR80MA		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define INPUT_CUR850MA		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define INPUT_CUR1000MA		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define INPUT_CUR1250MA		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define INPUT_CUR1500MA		(0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define INPUT_CUR1750MA		(0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define INPUT_CUR2000MA		(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define INPUT_CUR2250MA		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define INPUT_CUR2500MA		(0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define INPUT_CUR2750MA		(0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define INPUT_CUR3000MA		(0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*CHRG_VOL_SEL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CHRG_VOL4050MV		(0x00 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CHRG_VOL4100MV		(0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CHRG_VOL4150MV		(0x02 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CHRG_VOL4200MV		(0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CHRG_VOL4300MV		(0x04 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CHRG_VOL4350MV		(0x05 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /*CHRG_CUR_SEL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CHRG_CUR1000MA		(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CHRG_CUR1200MA		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CHRG_CUR1400MA		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CHRG_CUR1600MA		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CHRG_CUR1800MA		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CHRG_CUR2000MA		(0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CHRG_CUR2200MA		(0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CHRG_CUR2400MA		(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CHRG_CUR2600MA		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CHRG_CUR2800MA		(0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CHRG_CUR3000MA		(0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*THREAML_REG*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEMP_85C		(0x00 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEMP_95C		(0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEMP_105C		(0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEMP_115C		(0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*CHRG_CTRL_REG2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CHG_CCCV_4HOUR		(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CHG_CCCV_5HOUR		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CHG_CCCV_6HOUR		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CHG_CCCV_8HOUR		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CHG_CCCV_10HOUR		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CHG_CCCV_12HOUR		(0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CHG_CCCV_14HOUR		(0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CHG_CCCV_16HOUR		(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define FINISH_100MA		(0x00 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define FINISH_150MA		(0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define FINISH_200MA		(0x02 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FINISH_250MA		(0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*CHRG_CTRL_REG3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CHRG_TERM_ANA_SIGNAL	(0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CHRG_TERM_DIG_SIGNAL	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CHRG_TIMER_CCCV_EN	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CHRG_EN			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BOOST_OTG_MASK		((0x3 << 5) | (0x3 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BOOST_OTG_ON		((0x3 << 5) | (0x3 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BOOST_OTG_OFF		((0x3 << 5) | (0x0 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BOOST_OFF_OTG_ON	((0x3 << 5) | (0x2 << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OTG_BOOST_SLP_ON	(0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* MISC_MARK_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FG_INIT			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FG_RESET_LATE		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define FG_RESET_NOW		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ALGO_REST_MODE_MSK	(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ALGO_REST_MODE_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FB_TEMP_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CHRG_VOL_SEL_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CHRG_CRU_INPUT_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CHRG_CRU_SEL_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CHRG_CCCV_HOUR_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define	OCV_CALIB_SHIFT		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PLUG_IN_STS		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DRIVER_VERSION		"1.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TIMER_MS_COUNTS		1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MAX_PERCENTAGE		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MAX_INT			0x7FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MAX_INTERPOLATE		1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct temp_chrg_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int temp_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int temp_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 chrg_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u8 set_chrg_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct battery_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u32 *ocv_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	u32 *zero_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct temp_chrg_table *tc_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u32 tc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u32 table_t[4][21];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int temp_t[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	u32 temp_t_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u32 *ntc_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u32 ocv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u32 ntc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int ntc_degree_from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 ntc_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 max_input_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 max_chrg_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 max_chrg_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u32 pwroff_vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u32 monitor_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u32 zero_algorithm_vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u32 zero_reserve_dsoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	u32 bat_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u32 design_capacity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u32 design_qmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u32 sleep_enter_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	u32 sleep_exit_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	u32 sleep_filter_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u32 power_dc2otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 max_soc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 bat_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u32 fb_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 energy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	u32 cccv_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u32 dc_det_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	int dc_det_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u8  dc_det_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	int otg5v_suspend_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u32 sample_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	bool extcon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum work_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	MODE_ZERO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	MODE_FINISH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	MODE_SMOOTH_CHRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	MODE_SMOOTH_DISCHRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	MODE_SMOOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) enum bat_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	MODE_BATTARY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	MODE_VIRTUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) enum charger_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	USB_TYPE_UNKNOWN_CHARGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	USB_TYPE_NONE_CHARGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	USB_TYPE_USB_CHARGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	USB_TYPE_AC_CHARGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	USB_TYPE_CDP_CHARGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	DC_TYPE_DC_CHARGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	DC_TYPE_NONE_CHARGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) enum charger_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	OFFLINE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ONLINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const u16 FEED_BACK_TEMP[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	85, 95, 105, 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const u16 CHRG_VOL_SEL[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	4050, 4100, 4150, 4200, 4250, 4300, 4350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * If sample resistor changes, we need caculate a new CHRG_CUR_SEL[] table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * Calculation method:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * 1. find 20mR(default) current charge table, that is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  *	20mR: [1000, 1200, 1400, 1600, 1800, 2000, 2250, 2400]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * 2. caculate Rfac(not care much, just using it) by sample resistor(ie. Rsam);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  *	Rsam = 20mR: Rfac = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  *	Rsam > 20mR: Rfac = Rsam * 10 / 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  *	Rsam < 20mR: Rfac = 20 * 10 / Rsam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * 3. from step2, we get Rfac, then we can get new charge current table by 20mR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  *    charge table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  *	Iorg: member from 20mR charge table; Inew: new member for charge table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  *	Rsam > 20mR: Inew = Iorg * 10 / Rfac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  *	Rsam < 20mR: Inew = Iorg * Rfac / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * Notice: Inew should round up if it is not a integer!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  * Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  *	10mR: [2000, 2400, 2800, 3200, 3600, 4000, 4500, 4800]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  *	20mR: [1000, 1200, 1400, 1600, 1800, 2000, 2250, 2400]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  *	40mR: [500,  600,  700,  800,  900,  1000, 1125, 1200]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  *	50mR: [400,  480,  560,  640,  720,  800,  900,  960]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  *	60mR: [334,  400,  467,  534,  600,  667,  750,  800]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * You should add property 'sample_res = <Rsam>' at battery node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const u16 CHRG_CUR_SEL[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	1000, 1200, 1400, 1600, 1800, 2000, 2250, 2400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const u16 CHRG_CUR_INPUT[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	450, 80, 850, 1000, 1250, 1500, 1750, 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void kernel_power_off(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif