^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * PM2301 power supply interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef PM2301_CHARGER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PM2301_CHARGER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Watchdog timeout constant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define WD_TIMER 0x30 /* 4min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define WD_KICK_INTERVAL (30 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PM2XXX_NUM_INT_REG 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Constant voltage/current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PM2XXX_CONST_CURR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PM2XXX_CONST_VOLT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Lowest charger voltage is 3.39V -> 0x4E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LOW_VOLT_REG 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PM2XXX_BATT_CTRL_REG1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PM2XXX_BATT_CTRL_REG2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PM2XXX_BATT_CTRL_REG3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PM2XXX_BATT_CTRL_REG4 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PM2XXX_BATT_CTRL_REG5 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PM2XXX_BATT_CTRL_REG6 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PM2XXX_BATT_CTRL_REG7 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PM2XXX_BATT_CTRL_REG8 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PM2XXX_NTC_CTRL_REG1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PM2XXX_NTC_CTRL_REG2 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PM2XXX_BATT_CTRL_REG9 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PM2XXX_BATT_STAT_REG1 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PM2XXX_INP_VOLT_VPWR2 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PM2XXX_INP_DROP_VPWR2 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PM2XXX_INP_VOLT_VPWR1 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PM2XXX_INP_DROP_VPWR1 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PM2XXX_INP_MODE_VPWR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PM2XXX_BATT_WD_KICK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PM2XXX_DEV_VER_STAT 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PM2XXX_THERM_WARN_CTRL_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PM2XXX_BATT_DISC_REG 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PM2XXX_BATT_LOW_LEV_COMP_REG 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PM2XXX_BATT_LOW_LEV_VAL_REG 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PM2XXX_I2C_PAD_CTRL_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PM2XXX_SW_CTRL_REG 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PM2XXX_LED_CTRL_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PM2XXX_REG_INT1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PM2XXX_MASK_REG_INT1 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PM2XXX_SRCE_REG_INT1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PM2XXX_REG_INT2 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PM2XXX_MASK_REG_INT2 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PM2XXX_SRCE_REG_INT2 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PM2XXX_REG_INT3 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PM2XXX_MASK_REG_INT3 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PM2XXX_SRCE_REG_INT3 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PM2XXX_REG_INT4 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PM2XXX_MASK_REG_INT4 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PM2XXX_SRCE_REG_INT4 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PM2XXX_REG_INT5 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PM2XXX_MASK_REG_INT5 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PM2XXX_SRCE_REG_INT5 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PM2XXX_REG_INT6 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PM2XXX_MASK_REG_INT6 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PM2XXX_SRCE_REG_INT6 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VPWR_OVV 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VSYSTEM_OVV 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* control Reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PM2XXX_CH_RESUME_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PM2XXX_CH_RESUME_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* control Reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PM2XXX_CH_AUTO_RESUME_EN 0X2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PM2XXX_CH_AUTO_RESUME_DIS 0X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PM2XXX_CHARGER_ENA 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PM2XXX_CHARGER_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* control Reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PM2XXX_CH_WD_CC_PHASE_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PM2XXX_CH_WD_CC_PHASE_5MIN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PM2XXX_CH_WD_CC_PHASE_10MIN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PM2XXX_CH_WD_CC_PHASE_30MIN 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PM2XXX_CH_WD_CC_PHASE_60MIN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PM2XXX_CH_WD_CC_PHASE_120MIN 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PM2XXX_CH_WD_CC_PHASE_240MIN 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PM2XXX_CH_WD_CC_PHASE_360MIN 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PM2XXX_CH_WD_CV_PHASE_OFF (0x0<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PM2XXX_CH_WD_CV_PHASE_5MIN (0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PM2XXX_CH_WD_CV_PHASE_10MIN (0x2<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PM2XXX_CH_WD_CV_PHASE_30MIN (0x3<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PM2XXX_CH_WD_CV_PHASE_60MIN (0x4<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PM2XXX_CH_WD_CV_PHASE_120MIN (0x5<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PM2XXX_CH_WD_CV_PHASE_240MIN (0x6<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PM2XXX_CH_WD_CV_PHASE_360MIN (0x7<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* control Reg 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PM2XXX_CH_WD_PRECH_PHASE_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PM2XXX_CH_WD_PRECH_PHASE_1MIN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PM2XXX_CH_WD_PRECH_PHASE_5MIN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PM2XXX_CH_WD_PRECH_PHASE_10MIN 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PM2XXX_CH_WD_PRECH_PHASE_30MIN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PM2XXX_CH_WD_PRECH_PHASE_60MIN 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PM2XXX_CH_WD_PRECH_PHASE_120MIN 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PM2XXX_CH_WD_PRECH_PHASE_240MIN 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* control Reg 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PM2XXX_CH_WD_AUTO_TIMEOUT_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* control Reg 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PM2XXX_DIR_CH_CC_CURRENT_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PM2XXX_DIR_CH_CC_CURRENT_200MA 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PM2XXX_DIR_CH_CC_CURRENT_400MA 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PM2XXX_DIR_CH_CC_CURRENT_600MA 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PM2XXX_DIR_CH_CC_CURRENT_800MA 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PM2XXX_DIR_CH_CC_CURRENT_1000MA 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PM2XXX_DIR_CH_CC_CURRENT_1200MA 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PM2XXX_DIR_CH_CC_CURRENT_1400MA 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PM2XXX_DIR_CH_CC_CURRENT_1600MA 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PM2XXX_DIR_CH_CC_CURRENT_1800MA 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PM2XXX_DIR_CH_CC_CURRENT_2000MA 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PM2XXX_DIR_CH_CC_CURRENT_2200MA 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PM2XXX_DIR_CH_CC_CURRENT_2400MA 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PM2XXX_DIR_CH_CC_CURRENT_2600MA 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PM2XXX_DIR_CH_CC_CURRENT_2800MA 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PM2XXX_DIR_CH_CC_CURRENT_3000MA 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PM2XXX_CH_PRECH_CURRENT_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PM2XXX_CH_PRECH_CURRENT_25MA (0x0<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PM2XXX_CH_PRECH_CURRENT_50MA (0x1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PM2XXX_CH_PRECH_CURRENT_75MA (0x2<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PM2XXX_CH_PRECH_CURRENT_100MA (0x3<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PM2XXX_CH_EOC_CURRENT_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PM2XXX_CH_EOC_CURRENT_100MA (0x0<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PM2XXX_CH_EOC_CURRENT_150MA (0x1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PM2XXX_CH_EOC_CURRENT_300MA (0x2<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PM2XXX_CH_EOC_CURRENT_400MA (0x3<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* control Reg 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PM2XXX_CH_PRECH_VOL_2_5 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PM2XXX_CH_PRECH_VOL_2_7 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PM2XXX_CH_PRECH_VOL_2_9 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PM2XXX_CH_PRECH_VOL_3_1 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PM2XXX_CH_VRESUME_VOL_3_2 (0x0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PM2XXX_CH_VRESUME_VOL_3_4 (0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PM2XXX_CH_VRESUME_VOL_3_6 (0x2<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PM2XXX_CH_VRESUME_VOL_3_8 (0x3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* control Reg 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PM2XXX_CH_VOLT_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PM2XXX_CH_VOLT_3_5 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PM2XXX_CH_VOLT_3_5225 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PM2XXX_CH_VOLT_3_6 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PM2XXX_CH_VOLT_3_7 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PM2XXX_CH_VOLT_4_0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PM2XXX_CH_VOLT_4_175 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PM2XXX_CH_VOLT_4_2 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PM2XXX_CH_VOLT_4_275 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PM2XXX_CH_VOLT_4_3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*NTC control register 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PM2XXX_BTEMP_HIGH_TH_45 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PM2XXX_BTEMP_HIGH_TH_50 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PM2XXX_BTEMP_HIGH_TH_55 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PM2XXX_BTEMP_HIGH_TH_60 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PM2XXX_BTEMP_HIGH_TH_65 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PM2XXX_BTEMP_LOW_TH_N5 (0x0<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PM2XXX_BTEMP_LOW_TH_0 (0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PM2XXX_BTEMP_LOW_TH_5 (0x2<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PM2XXX_BTEMP_LOW_TH_10 (0x3<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*NTC control register 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PM2XXX_NTC_BETA_COEFF_3477 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PM2XXX_NTC_BETA_COEFF_3964 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PM2XXX_NTC_RES_10K (0x0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PM2XXX_NTC_RES_47K (0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PM2XXX_NTC_RES_100K (0x2<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PM2XXX_NTC_RES_NO_NTC (0x3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* control Reg 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PM2XXX_CH_CC_MODEDROP_EN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PM2XXX_CH_CC_MODEDROP_DIS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PM2XXX_CH_CC_REDUCED_CURRENT_100MA (0x0<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PM2XXX_CH_CC_REDUCED_CURRENT_200MA (0x1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PM2XXX_CH_CC_REDUCED_CURRENT_400MA (0x2<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PM2XXX_CH_CC_REDUCED_CURRENT_IDENT (0x3<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PM2XXX_CHARCHING_INFO_DIS (0<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PM2XXX_CHARCHING_INFO_EN (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PM2XXX_CH_150MV_DROP_300MV (0<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PM2XXX_CH_150MV_DROP_150MV (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* charger status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PM2XXX_CHG_STATUS_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PM2XXX_CHG_STATUS_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PM2XXX_CHG_STATUS_FULL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PM2XXX_CHG_STATUS_ERR 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PM2XXX_CHG_STATUS_WAIT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PM2XXX_CHG_STATUS_NOBAT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Input charger voltage VPWR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PM2XXX_VPWR2_OVV_6_0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PM2XXX_VPWR2_OVV_6_3 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PM2XXX_VPWR2_OVV_10 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PM2XXX_VPWR2_OVV_NONE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Input charger drop VPWR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PM2XXX_VPWR2_HW_OPT_EN (0x1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PM2XXX_VPWR2_HW_OPT_DIS (0x0<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PM2XXX_VPWR2_VALID_EN (0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PM2XXX_VPWR2_VALID_DIS (0x0<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PM2XXX_VPWR2_DROP_EN (0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PM2XXX_VPWR2_DROP_DIS (0x0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Input charger voltage VPWR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PM2XXX_VPWR1_OVV_6_0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PM2XXX_VPWR1_OVV_6_3 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PM2XXX_VPWR1_OVV_10 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PM2XXX_VPWR1_OVV_NONE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Input charger drop VPWR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PM2XXX_VPWR1_HW_OPT_EN (0x1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PM2XXX_VPWR1_HW_OPT_DIS (0x0<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PM2XXX_VPWR1_VALID_EN (0x1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PM2XXX_VPWR1_VALID_DIS (0x0<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PM2XXX_VPWR1_DROP_EN (0x1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PM2XXX_VPWR1_DROP_DIS (0x0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Battery low level comparator control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PM2XXX_VBAT_LOW_MONITORING_DIS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PM2XXX_VBAT_LOW_MONITORING_ENA 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Battery low level value control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PM2XXX_VBAT_LOW_LEVEL_2_3 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define PM2XXX_VBAT_LOW_LEVEL_2_4 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PM2XXX_VBAT_LOW_LEVEL_2_5 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PM2XXX_VBAT_LOW_LEVEL_2_6 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PM2XXX_VBAT_LOW_LEVEL_2_7 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PM2XXX_VBAT_LOW_LEVEL_2_8 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PM2XXX_VBAT_LOW_LEVEL_2_9 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PM2XXX_VBAT_LOW_LEVEL_3_0 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PM2XXX_VBAT_LOW_LEVEL_3_1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define PM2XXX_VBAT_LOW_LEVEL_3_2 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define PM2XXX_VBAT_LOW_LEVEL_3_3 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PM2XXX_VBAT_LOW_LEVEL_3_4 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PM2XXX_VBAT_LOW_LEVEL_3_5 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PM2XXX_VBAT_LOW_LEVEL_3_6 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PM2XXX_VBAT_LOW_LEVEL_3_7 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PM2XXX_VBAT_LOW_LEVEL_3_8 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PM2XXX_VBAT_LOW_LEVEL_3_9 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PM2XXX_VBAT_LOW_LEVEL_4_0 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PM2XXX_VBAT_LOW_LEVEL_4_1 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PM2XXX_VBAT_LOW_LEVEL_4_2 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* SW CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PM2XXX_SWCTRL_HW 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define PM2XXX_SWCTRL_SW 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* LED Driver Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PM2XXX_LED_CURRENT_MASK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PM2XXX_LED_CURRENT_2_5MA (0X0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PM2XXX_LED_CURRENT_1MA (0X1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PM2XXX_LED_CURRENT_5MA (0X2<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PM2XXX_LED_CURRENT_10MA (0X3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PM2XXX_LED_SELECT_MASK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PM2XXX_LED_SELECT_EN (0X0<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PM2XXX_LED_SELECT_DIS (0X1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PM2XXX_ANTI_OVERSHOOT_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PM2XXX_ANTI_OVERSHOOT_DIS 0X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define PM2XXX_ANTI_OVERSHOOT_EN 0X1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) enum pm2xxx_reg_int1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PM2XXX_INT1_ITVBATDISCONNECT = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PM2XXX_INT1_ITVBATLOWR = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PM2XXX_INT1_ITVBATLOWF = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) enum pm2xxx_mask_reg_int1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PM2XXX_INT1_M_ITVBATDISCONNECT = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PM2XXX_INT1_M_ITVBATLOWR = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PM2XXX_INT1_M_ITVBATLOWF = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) enum pm2xxx_source_reg_int1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PM2XXX_INT1_S_ITVBATDISCONNECT = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PM2XXX_INT1_S_ITVBATLOWR = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PM2XXX_INT1_S_ITVBATLOWF = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) enum pm2xxx_reg_int2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PM2XXX_INT2_ITVPWR2PLUG = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PM2XXX_INT2_ITVPWR2UNPLUG = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PM2XXX_INT2_ITVPWR1PLUG = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PM2XXX_INT2_ITVPWR1UNPLUG = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) enum pm2xxx_mask_reg_int2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PM2XXX_INT2_M_ITVPWR2PLUG = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PM2XXX_INT2_M_ITVPWR2UNPLUG = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PM2XXX_INT2_M_ITVPWR1PLUG = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PM2XXX_INT2_M_ITVPWR1UNPLUG = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) enum pm2xxx_source_reg_int2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PM2XXX_INT2_S_ITVPWR2PLUG = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PM2XXX_INT2_S_ITVPWR1PLUG = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) enum pm2xxx_reg_int3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PM2XXX_INT3_ITCHPRECHARGEWD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PM2XXX_INT3_ITCHCCWD = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PM2XXX_INT3_ITCHCVWD = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PM2XXX_INT3_ITAUTOTIMEOUTWD = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) enum pm2xxx_mask_reg_int3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PM2XXX_INT3_M_ITCHPRECHARGEWD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PM2XXX_INT3_M_ITCHCCWD = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PM2XXX_INT3_M_ITCHCVWD = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PM2XXX_INT3_M_ITAUTOTIMEOUTWD = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum pm2xxx_source_reg_int3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PM2XXX_INT3_S_ITCHPRECHARGEWD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PM2XXX_INT3_S_ITCHCCWD = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PM2XXX_INT3_S_ITCHCVWD = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PM2XXX_INT3_S_ITAUTOTIMEOUTWD = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) enum pm2xxx_reg_int4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PM2XXX_INT4_ITBATTEMPCOLD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PM2XXX_INT4_ITBATTEMPHOT = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PM2XXX_INT4_ITVPWR2OVV = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PM2XXX_INT4_ITVPWR1OVV = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PM2XXX_INT4_ITCHARGINGON = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PM2XXX_INT4_ITVRESUME = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PM2XXX_INT4_ITBATTFULL = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PM2XXX_INT4_ITCVPHASE = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) enum pm2xxx_mask_reg_int4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PM2XXX_INT4_M_ITBATTEMPCOLD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PM2XXX_INT4_M_ITBATTEMPHOT = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PM2XXX_INT4_M_ITVPWR2OVV = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PM2XXX_INT4_M_ITVPWR1OVV = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PM2XXX_INT4_M_ITCHARGINGON = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PM2XXX_INT4_M_ITVRESUME = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PM2XXX_INT4_M_ITBATTFULL = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PM2XXX_INT4_M_ITCVPHASE = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) enum pm2xxx_source_reg_int4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PM2XXX_INT4_S_ITBATTEMPCOLD = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PM2XXX_INT4_S_ITBATTEMPHOT = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PM2XXX_INT4_S_ITVPWR2OVV = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PM2XXX_INT4_S_ITVPWR1OVV = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PM2XXX_INT4_S_ITCHARGINGON = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PM2XXX_INT4_S_ITVRESUME = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PM2XXX_INT4_S_ITBATTFULL = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PM2XXX_INT4_S_ITCVPHASE = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) enum pm2xxx_reg_int5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PM2XXX_INT5_ITTHERMALSHUTDOWNRISE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PM2XXX_INT5_ITTHERMALSHUTDOWNFALL = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PM2XXX_INT5_ITTHERMALWARNINGRISE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PM2XXX_INT5_ITTHERMALWARNINGFALL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PM2XXX_INT5_ITVSYSTEMOVV = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) enum pm2xxx_mask_reg_int5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PM2XXX_INT5_M_ITTHERMALWARNINGRISE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PM2XXX_INT5_M_ITTHERMALWARNINGFALL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PM2XXX_INT5_M_ITVSYSTEMOVV = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) enum pm2xxx_source_reg_int5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PM2XXX_INT5_S_ITTHERMALWARNINGRISE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PM2XXX_INT5_S_ITTHERMALWARNINGFALL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PM2XXX_INT5_S_ITVSYSTEMOVV = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum pm2xxx_reg_int6 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PM2XXX_INT6_ITVPWR2DROP = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PM2XXX_INT6_ITVPWR1DROP = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PM2XXX_INT6_ITVPWR2VALIDRISE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PM2XXX_INT6_ITVPWR2VALIDFALL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PM2XXX_INT6_ITVPWR1VALIDRISE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PM2XXX_INT6_ITVPWR1VALIDFALL = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) enum pm2xxx_mask_reg_int6 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PM2XXX_INT6_M_ITVPWR2DROP = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PM2XXX_INT6_M_ITVPWR1DROP = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PM2XXX_INT6_M_ITVPWR2VALIDRISE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PM2XXX_INT6_M_ITVPWR2VALIDFALL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PM2XXX_INT6_M_ITVPWR1VALIDRISE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PM2XXX_INT6_M_ITVPWR1VALIDFALL = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) enum pm2xxx_source_reg_int6 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PM2XXX_INT6_S_ITVPWR2DROP = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PM2XXX_INT6_S_ITVPWR1DROP = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PM2XXX_INT6_S_ITVPWR2VALIDRISE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PM2XXX_INT6_S_ITVPWR2VALIDFALL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PM2XXX_INT6_S_ITVPWR1VALIDRISE = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PM2XXX_INT6_S_ITVPWR1VALIDFALL = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct pm2xxx_charger_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int charger_connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int charger_online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int cv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) bool wd_expired;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct pm2xxx_charger_event_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) bool mainextchnotok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bool main_thermal_prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) bool ovv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) bool chgwdexp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct pm2xxx_interrupts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 reg[PM2XXX_NUM_INT_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int (*handler[PM2XXX_NUM_INT_REG])(void *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct pm2xxx_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct i2c_client *pm2xxx_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct i2c_device_id *pm2xxx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct pm2xxx_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) irqreturn_t (*isr)(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct pm2xxx_charger {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u8 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) bool vddadc_en_ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct pm2xxx_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bool ac_conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int gpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int vbat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int old_vbat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int failure_case;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int failure_input_ovv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unsigned int lpn_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct pm2xxx_interrupts *pm2_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct regulator *regu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct pm2xxx_bm_data *bat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct ab8500 *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct pm2xxx_charger_info ac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct pm2xxx_charger_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct workqueue_struct *charger_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct delayed_work check_vbat_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct work_struct ac_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct work_struct check_main_thermal_prot_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct delayed_work check_hw_failure_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct ux500_charger ac_chg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct power_supply_desc ac_chg_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct pm2xxx_charger_event_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #endif /* PM2301_CHARGER_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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