^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DA9150 Fuel-Gauge Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Dialog Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/power_supply.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/da9150/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/da9150/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Core2Wire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DA9150_QIF_READ (0x0 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DA9150_QIF_WRITE (0x1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DA9150_QIF_CODE_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DA9150_QIF_BYTE_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DA9150_QIF_BYTE_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DA9150_QIF_SHORT_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DA9150_QIF_LONG_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* QIF Codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DA9150_QIF_UAVG 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DA9150_QIF_UAVG_SIZE DA9150_QIF_LONG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DA9150_QIF_IAVG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DA9150_QIF_IAVG_SIZE DA9150_QIF_LONG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DA9150_QIF_NTCAVG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DA9150_QIF_NTCAVG_SIZE DA9150_QIF_LONG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DA9150_QIF_SHUNT_VAL 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DA9150_QIF_SHUNT_VAL_SIZE DA9150_QIF_SHORT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DA9150_QIF_SD_GAIN 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DA9150_QIF_SD_GAIN_SIZE DA9150_QIF_LONG_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DA9150_QIF_FCC_MAH 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DA9150_QIF_FCC_MAH_SIZE DA9150_QIF_SHORT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DA9150_QIF_SOC_PCT 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DA9150_QIF_SOC_PCT_SIZE DA9150_QIF_SHORT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DA9150_QIF_CHARGE_LIMIT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DA9150_QIF_CHARGE_LIMIT_SIZE DA9150_QIF_SHORT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DA9150_QIF_DISCHARGE_LIMIT 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DA9150_QIF_DISCHARGE_LIMIT_SIZE DA9150_QIF_SHORT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DA9150_QIF_FW_MAIN_VER 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DA9150_QIF_FW_MAIN_VER_SIZE DA9150_QIF_SHORT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DA9150_QIF_E_FG_STATUS 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DA9150_QIF_E_FG_STATUS_SIZE DA9150_QIF_SHORT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DA9150_QIF_SYNC 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DA9150_QIF_SYNC_SIZE DA9150_QIF_SHORT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DA9150_QIF_MAX_CODES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* QIF Sync Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DA9150_QIF_SYNC_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DA9150_QIF_SYNC_RETRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* QIF E_FG_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DA9150_FG_IRQ_LOW_SOC_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DA9150_FG_IRQ_HIGH_SOC_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DA9150_FG_IRQ_SOC_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (DA9150_FG_IRQ_LOW_SOC_MASK | DA9150_FG_IRQ_HIGH_SOC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct da9150_fg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct da9150 *da9150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct mutex io_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct power_supply *battery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct delayed_work work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int warn_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int crit_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Battery Properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static u32 da9150_fg_read_attr(struct da9150_fg *fg, u8 code, u8 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 buf[DA9150_QIF_LONG_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Set QIF code (READ mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) read_addr = (code & DA9150_QIF_CODE_MASK) | DA9150_QIF_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) da9150_read_qif(fg->da9150, read_addr, size, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (i = 0; i < size; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) res |= (buf[i] << (i * DA9150_QIF_BYTE_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void da9150_fg_write_attr(struct da9150_fg *fg, u8 code, u8 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 buf[DA9150_QIF_LONG_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 write_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Set QIF code (WRITE mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) write_addr = (code & DA9150_QIF_CODE_MASK) | DA9150_QIF_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (i = 0; i < size; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) buf[i] = (val >> (i * DA9150_QIF_BYTE_SIZE)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DA9150_QIF_BYTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) da9150_write_qif(fg->da9150, write_addr, size, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Trigger QIF Sync to update QIF readable data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void da9150_fg_read_sync_start(struct da9150_fg *fg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mutex_lock(&fg->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Check if QIF sync already requested, and write to sync if not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) res = da9150_fg_read_attr(fg, DA9150_QIF_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DA9150_QIF_SYNC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (res > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) da9150_fg_write_attr(fg, DA9150_QIF_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DA9150_QIF_SYNC_SIZE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Wait for sync to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) while ((res == 0) && (i++ < DA9150_QIF_SYNC_RETRIES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) usleep_range(DA9150_QIF_SYNC_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DA9150_QIF_SYNC_TIMEOUT * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) res = da9150_fg_read_attr(fg, DA9150_QIF_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DA9150_QIF_SYNC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Check if sync completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (res == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err(fg->dev, "Failed to perform QIF read sync!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Should always be called after QIF sync read has been performed, and all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * attributes required have been accessed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline void da9150_fg_read_sync_end(struct da9150_fg *fg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mutex_unlock(&fg->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Sync read of single QIF attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static u32 da9150_fg_read_attr_sync(struct da9150_fg *fg, u8 code, u8 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) da9150_fg_read_sync_start(fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val = da9150_fg_read_attr(fg, code, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) da9150_fg_read_sync_end(fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Wait for QIF Sync, write QIF data and wait for ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void da9150_fg_write_attr_sync(struct da9150_fg *fg, u8 code, u8 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 res = 0, sync_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mutex_lock(&fg->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Check if QIF sync already requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) res = da9150_fg_read_attr(fg, DA9150_QIF_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DA9150_QIF_SYNC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Wait for an existing sync to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) while ((res == 0) && (i++ < DA9150_QIF_SYNC_RETRIES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) usleep_range(DA9150_QIF_SYNC_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DA9150_QIF_SYNC_TIMEOUT * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) res = da9150_fg_read_attr(fg, DA9150_QIF_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DA9150_QIF_SYNC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (res == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(fg->dev, "Timeout waiting for existing QIF sync!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mutex_unlock(&fg->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Write value for QIF code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) da9150_fg_write_attr(fg, code, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Wait for write acknowledgment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) sync_val = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) while ((res == sync_val) && (i++ < DA9150_QIF_SYNC_RETRIES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) usleep_range(DA9150_QIF_SYNC_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) DA9150_QIF_SYNC_TIMEOUT * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) res = da9150_fg_read_attr(fg, DA9150_QIF_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DA9150_QIF_SYNC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mutex_unlock(&fg->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Check write was actually successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (res != (sync_val + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dev_err(fg->dev, "Error performing QIF sync write for code %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Power Supply attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int da9150_fg_capacity(struct da9150_fg *fg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val->intval = da9150_fg_read_attr_sync(fg, DA9150_QIF_SOC_PCT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) DA9150_QIF_SOC_PCT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (val->intval > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val->intval = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int da9150_fg_current_avg(struct da9150_fg *fg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 iavg, sd_gain, shunt_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u64 div, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) da9150_fg_read_sync_start(fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) iavg = da9150_fg_read_attr(fg, DA9150_QIF_IAVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DA9150_QIF_IAVG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) shunt_val = da9150_fg_read_attr(fg, DA9150_QIF_SHUNT_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DA9150_QIF_SHUNT_VAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) sd_gain = da9150_fg_read_attr(fg, DA9150_QIF_SD_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DA9150_QIF_SD_GAIN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) da9150_fg_read_sync_end(fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) div = (u64) (sd_gain * shunt_val * 65536ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) do_div(div, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) res = (u64) (iavg * 1000000ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) do_div(res, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val->intval = (int) res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int da9150_fg_voltage_avg(struct da9150_fg *fg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u64 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) val->intval = da9150_fg_read_attr_sync(fg, DA9150_QIF_UAVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DA9150_QIF_UAVG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) res = (u64) (val->intval * 186ULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) do_div(res, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val->intval = (int) res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int da9150_fg_charge_full(struct da9150_fg *fg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val->intval = da9150_fg_read_attr_sync(fg, DA9150_QIF_FCC_MAH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DA9150_QIF_FCC_MAH_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) val->intval = val->intval * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Temperature reading from device is only valid if battery/system provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * valid NTC to associated pin of DA9150 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int da9150_fg_temp(struct da9150_fg *fg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val->intval = da9150_fg_read_attr_sync(fg, DA9150_QIF_NTCAVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) DA9150_QIF_NTCAVG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) val->intval = (val->intval * 10) / 1048576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static enum power_supply_property da9150_fg_props[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) POWER_SUPPLY_PROP_CAPACITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) POWER_SUPPLY_PROP_CURRENT_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) POWER_SUPPLY_PROP_VOLTAGE_AVG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) POWER_SUPPLY_PROP_CHARGE_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) POWER_SUPPLY_PROP_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int da9150_fg_get_prop(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) enum power_supply_property psp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct da9150_fg *fg = dev_get_drvdata(psy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) switch (psp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case POWER_SUPPLY_PROP_CAPACITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = da9150_fg_capacity(fg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case POWER_SUPPLY_PROP_CURRENT_AVG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = da9150_fg_current_avg(fg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case POWER_SUPPLY_PROP_VOLTAGE_AVG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = da9150_fg_voltage_avg(fg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case POWER_SUPPLY_PROP_CHARGE_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = da9150_fg_charge_full(fg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case POWER_SUPPLY_PROP_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ret = da9150_fg_temp(fg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Repeated SOC check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static bool da9150_fg_soc_changed(struct da9150_fg *fg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) union power_supply_propval val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) da9150_fg_capacity(fg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (val.intval != fg->soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) fg->soc = val.intval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void da9150_fg_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct da9150_fg *fg = container_of(work, struct da9150_fg, work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Report if SOC has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (da9150_fg_soc_changed(fg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) power_supply_changed(fg->battery);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) schedule_delayed_work(&fg->work, msecs_to_jiffies(fg->interval));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* SOC level event configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void da9150_fg_soc_event_config(struct da9150_fg *fg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) soc = da9150_fg_read_attr_sync(fg, DA9150_QIF_SOC_PCT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DA9150_QIF_SOC_PCT_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (soc > fg->warn_soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* If SOC > warn level, set discharge warn level event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) da9150_fg_write_attr_sync(fg, DA9150_QIF_DISCHARGE_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DA9150_QIF_DISCHARGE_LIMIT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) fg->warn_soc + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } else if ((soc <= fg->warn_soc) && (soc > fg->crit_soc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * If SOC <= warn level, set discharge crit level event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * and set charge warn level event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) da9150_fg_write_attr_sync(fg, DA9150_QIF_DISCHARGE_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DA9150_QIF_DISCHARGE_LIMIT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) fg->crit_soc + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) da9150_fg_write_attr_sync(fg, DA9150_QIF_CHARGE_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DA9150_QIF_CHARGE_LIMIT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) fg->warn_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) } else if (soc <= fg->crit_soc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* If SOC <= crit level, set charge crit level event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) da9150_fg_write_attr_sync(fg, DA9150_QIF_CHARGE_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DA9150_QIF_CHARGE_LIMIT_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) fg->crit_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static irqreturn_t da9150_fg_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct da9150_fg *fg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 e_fg_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Read FG IRQ status info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) e_fg_status = da9150_fg_read_attr(fg, DA9150_QIF_E_FG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DA9150_QIF_E_FG_STATUS_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Handle warning/critical threhold events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (e_fg_status & DA9150_FG_IRQ_SOC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) da9150_fg_soc_event_config(fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Clear any FG IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) da9150_fg_write_attr(fg, DA9150_QIF_E_FG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DA9150_QIF_E_FG_STATUS_SIZE, e_fg_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct da9150_fg_pdata *da9150_fg_dt_pdata(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct device_node *fg_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct da9150_fg_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pdata = devm_kzalloc(dev, sizeof(struct da9150_fg_pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) of_property_read_u32(fg_node, "dlg,update-interval",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &pdata->update_interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) of_property_read_u8(fg_node, "dlg,warn-soc-level",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) &pdata->warn_soc_lvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) of_property_read_u8(fg_node, "dlg,crit-soc-level",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) &pdata->crit_soc_lvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct power_supply_desc fg_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .name = "da9150-fg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .type = POWER_SUPPLY_TYPE_BATTERY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .properties = da9150_fg_props,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .num_properties = ARRAY_SIZE(da9150_fg_props),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .get_property = da9150_fg_get_prop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int da9150_fg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct da9150 *da9150 = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct da9150_fg_pdata *fg_pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct da9150_fg *fg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int ver, irq, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) fg = devm_kzalloc(dev, sizeof(*fg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (fg == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) platform_set_drvdata(pdev, fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) fg->da9150 = da9150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) fg->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mutex_init(&fg->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Enable QIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) da9150_set_bits(da9150, DA9150_CORE2WIRE_CTRL_A, DA9150_FG_QIF_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DA9150_FG_QIF_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fg->battery = devm_power_supply_register(dev, &fg_desc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (IS_ERR(fg->battery)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = PTR_ERR(fg->battery);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ver = da9150_fg_read_attr(fg, DA9150_QIF_FW_MAIN_VER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DA9150_QIF_FW_MAIN_VER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_info(dev, "Version: 0x%x\n", ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Handle DT data if provided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) fg_pdata = da9150_fg_dt_pdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev->platform_data = fg_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Handle any pdata provided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (fg_pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) fg->interval = fg_pdata->update_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (fg_pdata->warn_soc_lvl > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_warn(dev, "Invalid SOC warning level provided, Ignoring");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) fg->warn_soc = fg_pdata->warn_soc_lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if ((fg_pdata->crit_soc_lvl > 100) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) (fg_pdata->crit_soc_lvl >= fg_pdata->warn_soc_lvl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_warn(dev, "Invalid SOC critical level provided, Ignoring");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fg->crit_soc = fg_pdata->crit_soc_lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Configure initial SOC level events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) da9150_fg_soc_event_config(fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * If an interval period has been provided then setup repeating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * work for reporting data updates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (fg->interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) INIT_DELAYED_WORK(&fg->work, da9150_fg_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) schedule_delayed_work(&fg->work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) msecs_to_jiffies(fg->interval));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Register IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) irq = platform_get_irq_byname(pdev, "FG");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(dev, "Failed to get IRQ FG: %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) goto irq_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = devm_request_threaded_irq(dev, irq, NULL, da9150_fg_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) IRQF_ONESHOT, "FG", fg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_err(dev, "Failed to request IRQ %d: %d\n", irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) goto irq_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) irq_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (fg->interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cancel_delayed_work(&fg->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int da9150_fg_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct da9150_fg *fg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (fg->interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) cancel_delayed_work(&fg->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int da9150_fg_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct da9150_fg *fg = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Trigger SOC check to happen now so as to indicate any value change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * since last check before suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (fg->interval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) flush_delayed_work(&fg->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static struct platform_driver da9150_fg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .name = "da9150-fuel-gauge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .probe = da9150_fg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .remove = da9150_fg_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .resume = da9150_fg_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) module_platform_driver(da9150_fg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MODULE_DESCRIPTION("Fuel-Gauge Driver for DA9150");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MODULE_AUTHOR("Adam Thomson <Adam.Thomson.Opensource@diasemi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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