^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Chrager driver for cw221x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Xu Shengfei <xsf@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/power_supply.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Module parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) module_param_named(debug, debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_PARM_DESC(debug, "Set to one to enable debugging messages.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define cw_printk(fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pr_info("FG_CW221X: %s-%d:" fmt, __func__, __LINE__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CW_PROPERTIES "cw221X-bat"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_CHIP_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_VCELL_H 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_VCELL_L 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_SOC_INT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_SOC_DECIMAL 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_TEMP 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_MODE_CONFIG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_GPIO_CONFIG 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_SOC_ALERT 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_TEMP_MAX 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_TEMP_MIN 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_CURRENT_H 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_CURRENT_L 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_T_HOST_H 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_T_HOST_L 0xA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_USER_CONF 0xA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_CYCLE_H 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_CYCLE_L 0xA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_SOH 0xA6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_IC_STATE 0xA7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_FW_VERSION 0xAB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_BAT_PROFILE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CONFIG_MODE_RESTART 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CONFIG_MODE_ACTIVE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CONFIG_MODE_SLEEP 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CONFIG_UPDATE_FLG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IC_VCHIP_ID 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IC_READY_MARK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_ENABLE_MIN_TEMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_ENABLE_MAX_TEMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPIO_ENABLE_SOC_CHANGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPIO_SOC_IRQ_VALUE 0x0 /* 0x7F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DEFINED_MAX_TEMP 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DEFINED_MIN_TEMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CWFG_NAME "cw221X"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SIZE_OF_PROFILE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* mhom rsense * 1000 for convenience calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define USER_RSENSE 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define queue_delayed_work_time 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define queue_start_work_time 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CW_SLEEP_20MS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CW_SLEEP_10MS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CW_UI_FULL 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define COMPLEMENT_CODE_U16 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CW_SLEEP_100MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CW_SLEEP_200MS 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CW_SLEEP_COUNTS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CW_TRUE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CW_RETRY_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CW_VOL_UNIT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CW_LOW_VOLTAGE_REF 2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CW_LOW_VOLTAGE 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CW_LOW_VOLTAGE_STEP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CW221X_NOT_ACTIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CW221X_PROFILE_NOT_READY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CW221X_PROFILE_NEED_UPDATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CW2215_MARK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CW2217_MARK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CW2218_MARK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static unsigned char config_profile_info[SIZE_OF_PROFILE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC1, 0xCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0xC7, 0xC5, 0xBE, 0xA6, 0xA7, 0x9A, 0x36, 0x9D, 0x91, 0x85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x7E, 0x5C, 0x54, 0x4D, 0x49, 0x43, 0x3C, 0x36, 0x8C, 0xD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x6E, 0xE7, 0xCE, 0x8B, 0x67, 0x89, 0xC1, 0xD2, 0xCD, 0xC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0xB1, 0xC3, 0xB9, 0xBE, 0xC3, 0xC2, 0xC0, 0xC6, 0xCD, 0xC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0xCC, 0xE4, 0xDD, 0xF4, 0xFF, 0x71, 0x80, 0x00, 0xAB, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x00, 0x90, 0xA0, 0x00, 0x00, 0x00, 0x64, 0x13, 0xB3, 0xC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct cw_battery {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct workqueue_struct *cwfg_workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct delayed_work battery_delay_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct power_supply *cw_bat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 *bat_profile;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int ic_soc_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int ic_soc_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ui_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) long cw_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int soh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* CW221X iic read function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int cw_read(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned char buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = i2c_smbus_read_i2c_block_data(client, reg, 1, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(&client->dev, "IIC error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* CW221X iic write function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int cw_write(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned char const buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = i2c_smbus_write_i2c_block_data(client, reg, 1, &buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(&client->dev, "IIC error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* CW221X iic read word function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int cw_read_word(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned char buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned char reg_val[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int temp_val_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int temp_val_second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = i2c_smbus_read_i2c_block_data(client, reg, 2, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_err(&client->dev, "IIC error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) temp_val_buff = (reg_val[0] << 8) + reg_val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) msleep(CW_SLEEP_10MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = i2c_smbus_read_i2c_block_data(client, reg, 2, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(&client->dev, "IIC error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) temp_val_second = (reg_val[0] << 8) + reg_val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (temp_val_buff != temp_val_second) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) msleep(CW_SLEEP_10MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = i2c_smbus_read_i2c_block_data(client, reg, 2, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(&client->dev, "IIC error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) buf[0] = reg_val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) buf[1] = reg_val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* CW221X iic write profile function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int cw_write_profile(struct i2c_client *client, unsigned char const buf[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (i = 0; i < SIZE_OF_PROFILE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = cw_write(client, REG_BAT_PROFILE + i, &buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(&client->dev, "IIC error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * CW221X Active function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * The CONFIG register is used for the host MCU to configure the fuel gauge IC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * The default value is 0xF0, SLEEP and RESTART bits are set. To power up the IC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * the host MCU needs to write 0x30 to exit shutdown mode, and then write 0x00 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * restart the gauge to enter active mode. To reset the IC, the host MCU needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * to write 0xF0, 0x30 and 0x00 in sequence to this register to complete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * restart procedure. The CW221X will reload relevant parameters and settings and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * restart SOC calculation. Note that the SOC may be a different value after reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * operation since it is a brand-new calculation based on the latest battery status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * CONFIG [3:0] is reserved. Don't do any operation with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int cw221X_active(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned char reg_val = CONFIG_MODE_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = cw_write(cw_bat->client, REG_MODE_CONFIG, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) msleep(CW_SLEEP_20MS); /* Here delay must >= 20 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) reg_val = CONFIG_MODE_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = cw_write(cw_bat->client, REG_MODE_CONFIG, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) msleep(CW_SLEEP_10MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * CW221X Sleep function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * The CONFIG register is used for the host MCU to configure the fuel gauge IC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * The default value is 0xF0,SLEEP and RESTART bits are set. To power up the IC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * the host MCU needs to write 0x30 to exit shutdown mode, and then write 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * to restart the gauge to enter active mode. To reset the IC, the host MCU needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * to write 0xF0, 0x30 and 0x00 in sequence to this register to complete the restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * procedure. The CW221X will reload relevant parameters and settings and restart SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * calculation. Note that the SOC may be a different value after reset operation since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * it is a brand-new calculation based on the latest battery status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * CONFIG [3:0] is reserved. Don't do any operation with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int cw221X_sleep(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned char reg_val = CONFIG_MODE_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = cw_write(cw_bat->client, REG_MODE_CONFIG, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) msleep(CW_SLEEP_20MS); /* Here delay must >= 20 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) reg_val = CONFIG_MODE_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = cw_write(cw_bat->client, REG_MODE_CONFIG, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) msleep(CW_SLEEP_10MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * The 0x00 register is an UNSIGNED 8bit read-only register. Its value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * fixed to 0xA0 in shutdown mode and active mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int cw_get_chip_id(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned char reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = cw_read(cw_bat->client, REG_CHIP_ID, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) chip_id = reg_val; /* This value must be 0xA0! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pr_info("CW: chip_id = 0x%x\n", chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) cw_bat->chip_id = chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * The VCELL register(0x02 0x03) is an UNSIGNED 14bit read-only register that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * updates the battery voltage continuously. Battery voltage is measured between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * the VCELL pin and VSS pin, which is the ground reference. A 14bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * sigma-delta A/D converter is used and the voltage resolution is 312.5uV. (0.3125mV is *5/16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int cw_get_voltage(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned char reg_val[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = cw_read_word(cw_bat->client, REG_VCELL_H, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) voltage = (reg_val[0] << 8) + reg_val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) voltage = voltage * 5 / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) cw_bat->voltage = voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * The SOC register(0x04 0x05) is an UNSIGNED 16bit read-only register that indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * the SOC of the battery. The SOC shows in % format, which means how much percent of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * the battery's total available capacity is remaining in the battery now. The SOC can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * intrinsically adjust itself to cater to the change of battery status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * including load, temperature and aging etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * The high byte(0x04) contains the SOC in 1% unit which can be directly used if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * this resolution is good enough for the application. The low byte(0x05) provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * more accurate fractional part of the SOC and its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * LSB is (1/256) %.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int cw_get_capacity(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned char reg_val[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int ui_100 = CW_UI_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int ui_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int soc_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int soc_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = cw_read_word(cw_bat->client, REG_SOC_INT, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) soc_h = reg_val[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) soc_l = reg_val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ui_soc = ((soc_h * 256 + soc_l) * 100) / (ui_100 * 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* remainder = (((soc_h * 256 + soc_l) * 100 * 100) / (ui_100 * 256)) % 100; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ui_soc >= 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cw_printk("CW221x[%d]: UI_SOC = %d larger 100!\n", __LINE__, ui_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ui_soc = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) cw_bat->ic_soc_h = soc_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) cw_bat->ic_soc_l = soc_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cw_bat->ui_soc = ui_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * The TEMP register is an UNSIGNED 8bit read only register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * It reports the real-time battery temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * measured at TS pin. The scope is from -40 to 87.5 degrees Celsius,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * LSB is 0.5 degree Celsius. TEMP(C) = - 40 + Value(0x06 Reg) / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int cw_get_temp(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned char reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = cw_read(cw_bat->client, REG_TEMP, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) temp = (int)reg_val * 10 / 2 - 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) cw_bat->temp = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* get complement code function, unsigned short must be U16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static long get_complement_code(unsigned short raw_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) long complement_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (0 != (raw_code & COMPLEMENT_CODE_U16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dir = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) raw_code = (0xFFFF - raw_code) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dir = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) complement_code = (long)raw_code * dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return complement_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * CURRENT is a SIGNED 16bit register(0x0E 0x0F) that reports current A/D converter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * result of the voltage across the current sense resistor, 10mohm typical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * The result is stored as a two's complement value to show positive and negative current.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Voltages outside the minimum and maximum register values are reported as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * minimum or maximum value. The register value should be divided by the sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * resistance to convert to amperes. The value of the sense resistor determines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * the resolution and the full-scale range of the current readings. The LSB of 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * is (52.4/32768)uV for CW2215 and CW2217. The LSB of 0x0F is (125/32768)uV for CW2218.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * The default value is 0x0000, stands for 0mA. 0x7FFF stands for the maximum charging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * current and 0x8001 stands for the maximum discharging current.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int cw_get_current(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned char reg_val[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned short current_reg; /* unsigned short must u16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) long long cw_current; /* use long long type to guarantee 8 bytes space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = cw_read_word(cw_bat->client, REG_CURRENT_H, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) current_reg = (reg_val[0] << 8) + reg_val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cw_current = get_complement_code(current_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (((cw_bat->fw_version & CW2215_MARK) != 0) || ((cw_bat->fw_version & CW2217_MARK) != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cw_current = cw_current * 1600 / USER_RSENSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) else if ((cw_bat->fw_version != 0) && ((cw_bat->fw_version & 0xC0) == CW2218_MARK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) cw_current = cw_current * 3815 / USER_RSENSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) cw_bat->cw_current = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(cw_bat->dev, "error! cw221x firmware read error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) cw_bat->cw_current = cw_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * CYCLECNT is an UNSIGNED 16bit register(0xA4 0xA5) that counts cycle life of the battery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * The LSB of 0xA5 stands for 1/16 cycle. This register will be clear after enters shutdown mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int cw_get_cycle_count(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned char reg_val[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = cw_read_word(cw_bat->client, REG_CYCLE_H, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cycle = (reg_val[0] << 8) + reg_val[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) cw_bat->cycle = cycle / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * SOH (State of Health) is an UNSIGNED 8bit register(0xA6) that represents the level of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * battery aging by tracking battery internal impedance increment. When the device enters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * active mode, this register refresh to 0x64 by default. Its range is 0x00 to 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * indicating 0 to 100%. This register will be clear after enters shutdown mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int cw_get_soh(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned char reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int soh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = cw_read(cw_bat->client, REG_SOH, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) soh = reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) cw_bat->soh = soh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * FW_VERSION register reports the firmware (FW) running in the chip. It is fixed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * 0x00 when the chip is in shutdown mode. When in active mode, Bit [7:6] = '01' stand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * for the CW2217, Bit [7:6] = '00' stand for the CW2218 and Bit [7:6] = '10' stand for CW2215.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Bit[5:0] stand for the FW version running in the chip. Note that the FW version is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * subject to update and contact sales office for confirmation when necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int cw_get_fw_version(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned char reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = cw_read(cw_bat->client, REG_FW_VERSION, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) fw_version = reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) cw_bat->fw_version = fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int cw_update_data(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret += cw_get_voltage(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ret += cw_get_capacity(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret += cw_get_temp(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret += cw_get_current(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret += cw_get_cycle_count(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret += cw_get_soh(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cw_printk("vol = %d current = %ld cap = %d temp = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cw_bat->voltage, cw_bat->cw_current, cw_bat->ui_soc, cw_bat->temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int cw_init_data(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = cw_get_fw_version(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret += cw_get_chip_id(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret += cw_get_voltage(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret += cw_get_capacity(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret += cw_get_temp(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret += cw_get_current(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret += cw_get_cycle_count(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret += cw_get_soh(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cw_printk("chip_id = %d vol = %d cur = %ld cap = %d temp = %d fw_version = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cw_bat->chip_id, cw_bat->voltage, cw_bat->cw_current,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cw_bat->ui_soc, cw_bat->temp, cw_bat->fw_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int cw221x_parse_properties(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct device *dev = cw_bat->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) length = device_property_count_u8(dev, "cellwise,battery-profile");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (length < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_warn(cw_bat->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "No battery-profile found, using current flash contents\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) } else if (length != SIZE_OF_PROFILE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(cw_bat->dev, "battery-profile must be %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SIZE_OF_PROFILE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) cw_bat->bat_profile = devm_kzalloc(dev, length, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!cw_bat->bat_profile)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = device_property_read_u8_array(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "cellwise,battery-profile",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) cw_bat->bat_profile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*CW221X update profile function, Often called during initialization*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int cw_config_start_ic(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned char reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = cw221X_sleep(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = cw221x_parse_properties(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* update new battery info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = cw_write_profile(cw_bat->client, config_profile_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = cw_write_profile(cw_bat->client, cw_bat->bat_profile);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* set UPDATE_FLAG AND SOC INTTERRUP VALUE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) reg_val = CONFIG_UPDATE_FLG | GPIO_SOC_IRQ_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = cw_write(cw_bat->client, REG_SOC_ALERT, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* close all interruptes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = cw_write(cw_bat->client, REG_GPIO_CONFIG, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = cw221X_active(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) while (CW_TRUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) msleep(CW_SLEEP_100MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) cw_read(cw_bat->client, REG_IC_STATE, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (IC_READY_MARK == (reg_val & IC_READY_MARK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (count >= CW_SLEEP_COUNTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) cw221X_sleep(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Get the cw221X running state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * Determine whether the profile needs to be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int cw221X_get_state(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned char reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int reg_profile;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = cw_read(cw_bat->client, REG_MODE_CONFIG, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (reg_val != CONFIG_MODE_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return CW221X_NOT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = cw_read(cw_bat->client, REG_SOC_ALERT, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (0x00 == (reg_val & CONFIG_UPDATE_FLG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return CW221X_PROFILE_NOT_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) for (i = 0; i < SIZE_OF_PROFILE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = cw_read(cw_bat->client, (REG_BAT_PROFILE + i), ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) reg_profile = REG_BAT_PROFILE + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) cw_printk("0x%2x = 0x%2x\n", reg_profile, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (config_profile_info[i] != reg_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (i != SIZE_OF_PROFILE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return CW221X_PROFILE_NEED_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* CW221X init function, Often called during initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int cw_init(struct cw_battery *cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = cw_get_chip_id(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_err(cw_bat->dev, "iic read write error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (cw_bat->chip_id != IC_VCHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_err(cw_bat->dev, "not cw221X\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ret = cw221X_get_state(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(cw_bat->dev, "iic read write error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = cw_config_start_ic(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) cw_printk("cw221X init success!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static void cw_bat_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct delayed_work *delay_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct cw_battery *cw_bat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) delay_work = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct delayed_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) cw_bat = container_of(delay_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct cw_battery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) battery_delay_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = cw_update_data(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_err(cw_bat->dev, "i2c read error when update data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) power_supply_changed(cw_bat->cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) queue_delayed_work(cw_bat->cwfg_workqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) &cw_bat->battery_delay_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) msecs_to_jiffies(queue_delayed_work_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int cw_battery_set_property(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) enum power_supply_property psp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) const union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* struct cw_battery *cw_bat = power_supply_get_drvdata(psy); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) switch (psp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int cw_battery_get_property(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) enum power_supply_property psp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct cw_battery *cw_bat = power_supply_get_drvdata(psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) switch (psp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case POWER_SUPPLY_PROP_CYCLE_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val->intval = cw_bat->cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case POWER_SUPPLY_PROP_CAPACITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) val->intval = cw_bat->ui_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case POWER_SUPPLY_PROP_HEALTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) val->intval = POWER_SUPPLY_HEALTH_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case POWER_SUPPLY_PROP_PRESENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) val->intval = (cw_bat->voltage <= 0) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) case POWER_SUPPLY_PROP_VOLTAGE_NOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) val->intval = cw_bat->voltage * CW_VOL_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case POWER_SUPPLY_PROP_CURRENT_NOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) val->intval = cw_bat->cw_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case POWER_SUPPLY_PROP_TECHNOLOGY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case POWER_SUPPLY_PROP_TEMP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) val->intval = cw_bat->temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static enum power_supply_property cw_battery_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) POWER_SUPPLY_PROP_CYCLE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) POWER_SUPPLY_PROP_CAPACITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) POWER_SUPPLY_PROP_HEALTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) POWER_SUPPLY_PROP_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) POWER_SUPPLY_PROP_VOLTAGE_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) POWER_SUPPLY_PROP_CURRENT_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) POWER_SUPPLY_PROP_TECHNOLOGY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) POWER_SUPPLY_PROP_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int cw221X_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct power_supply_config psy_cfg = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct power_supply_desc *psy_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct cw_battery *cw_bat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) cw_bat = devm_kzalloc(&client->dev, sizeof(*cw_bat), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!cw_bat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) i2c_set_clientdata(client, cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) cw_bat->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) cw_bat->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = cw_init(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) while ((loop++ < CW_RETRY_COUNT) && (ret != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) msleep(CW_SLEEP_200MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = cw_init(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dev_err(cw_bat->dev, "cw221X init fail!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = cw_init_data(cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_err(cw_bat->dev, "cw221X init data fail!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) psy_desc = devm_kzalloc(&client->dev, sizeof(*psy_desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!psy_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) psy_cfg.drv_data = cw_bat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) psy_desc->name = CW_PROPERTIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) psy_desc->type = POWER_SUPPLY_TYPE_BATTERY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) psy_desc->properties = cw_battery_properties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) psy_desc->num_properties = ARRAY_SIZE(cw_battery_properties);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) psy_desc->get_property = cw_battery_get_property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) psy_desc->set_property = cw_battery_set_property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) cw_bat->cw_bat = devm_power_supply_register(&client->dev, psy_desc, &psy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (IS_ERR(cw_bat->cw_bat)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = PTR_ERR(cw_bat->cw_bat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_err(cw_bat->dev, "failed to register battery: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) cw_bat->cwfg_workqueue = create_singlethread_workqueue("cwfg_gauge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) INIT_DELAYED_WORK(&cw_bat->battery_delay_work, cw_bat_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) queue_delayed_work(cw_bat->cwfg_workqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &cw_bat->battery_delay_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) msecs_to_jiffies(queue_start_work_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) cw_printk("cw221X driver probe success!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int cw221X_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct cw_battery *cw_bat = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) cancel_delayed_work_sync(&cw_bat->battery_delay_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) destroy_workqueue(cw_bat->cwfg_workqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int cw_bat_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct cw_battery *cw_bat = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) cancel_delayed_work(&cw_bat->battery_delay_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int cw_bat_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct cw_battery *cw_bat = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) queue_delayed_work(cw_bat->cwfg_workqueue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &cw_bat->battery_delay_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) msecs_to_jiffies(20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const struct dev_pm_ops cw_bat_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .suspend = cw_bat_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .resume = cw_bat_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const struct i2c_device_id cw221X_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) { CWFG_NAME, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MODULE_DEVICE_TABLE(i2c, cw221X_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const struct of_device_id cw221X_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) { .compatible = "cellwise,cw221X", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) MODULE_DEVICE_TABLE(of, cw221X_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static struct i2c_driver cw221X_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .name = CWFG_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .pm = &cw_bat_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .of_match_table = of_match_ptr(cw221X_match_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .probe = cw221X_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .remove = cw221X_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .id_table = cw221X_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) module_i2c_driver(cw221X_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) MODULE_DESCRIPTION("CW221X FGADC Device Driver V0.1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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