^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef BQ25980_CHARGER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define BQ25980_CHARGER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define BQ25980_MANUFACTURER "Texas Instruments"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define BQ25980_BATOVP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BQ25980_BATOVP_ALM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BQ25980_BATOCP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BQ25980_BATOCP_ALM 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BQ25980_BATUCP_ALM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BQ25980_CHRGR_CTRL_1 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BQ25980_BUSOVP 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BQ25980_BUSOVP_ALM 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BQ25980_BUSOCP 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BQ25980_BUSOCP_ALM 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BQ25980_TEMP_CONTROL 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BQ25980_TDIE_ALM 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BQ25980_TSBUS_FLT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BQ25980_TSBAT_FLG 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BQ25980_VAC_CONTROL 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BQ25980_CHRGR_CTRL_2 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BQ25980_CHRGR_CTRL_3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BQ25980_CHRGR_CTRL_4 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BQ25980_CHRGR_CTRL_5 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BQ25980_STAT1 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BQ25980_STAT2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BQ25980_STAT3 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BQ25980_STAT4 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BQ25980_STAT5 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BQ25980_FLAG1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BQ25980_FLAG2 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BQ25980_FLAG3 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BQ25980_FLAG4 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BQ25980_FLAG5 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BQ25980_MASK1 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BQ25980_MASK2 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BQ25980_MASK3 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BQ25980_MASK4 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BQ25980_MASK5 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BQ25980_DEVICE_INFO 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BQ25980_ADC_CONTROL1 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BQ25980_ADC_CONTROL2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BQ25980_IBUS_ADC_MSB 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BQ25980_IBUS_ADC_LSB 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BQ25980_VBUS_ADC_MSB 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BQ25980_VBUS_ADC_LSB 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BQ25980_VAC1_ADC_MSB 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BQ25980_VAC1_ADC_LSB 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BQ25980_VAC2_ADC_MSB 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BQ25980_VAC2_ADC_LSB 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BQ25980_VOUT_ADC_MSB 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BQ25980_VOUT_ADC_LSB 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BQ25980_VBAT_ADC_MSB 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BQ25980_VBAT_ADC_LSB 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BQ25980_IBAT_ADC_MSB 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BQ25980_IBAT_ADC_LSB 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BQ25980_TSBUS_ADC_MSB 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BQ25980_TSBUS_ADC_LSB 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BQ25980_TSBAT_ADC_MSB 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BQ25980_TSBAT_ADC_LSB 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BQ25980_TDIE_ADC_MSB 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BQ25980_TDIE_ADC_LSB 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BQ25980_DEGLITCH_TIME 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BQ25980_CHRGR_CTRL_6 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BQ25980_BUSOCP_STEP_uA 250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BQ25980_BUSOCP_OFFSET_uA 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BQ25980_BUSOCP_DFLT_uA 4250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BQ25975_BUSOCP_DFLT_uA 4250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BQ25960_BUSOCP_DFLT_uA 3250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BQ25980_BUSOCP_MIN_uA 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BQ25980_BUSOCP_SC_MAX_uA 5750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BQ25975_BUSOCP_SC_MAX_uA 5750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BQ25960_BUSOCP_SC_MAX_uA 3750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BQ25980_BUSOCP_BYP_MAX_uA 8500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BQ25975_BUSOCP_BYP_MAX_uA 8500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BQ25960_BUSOCP_BYP_MAX_uA 5750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BQ25980_BUSOVP_SC_STEP_uV 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BQ25975_BUSOVP_SC_STEP_uV 50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BQ25960_BUSOVP_SC_STEP_uV 50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BQ25980_BUSOVP_SC_OFFSET_uV 14000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BQ25975_BUSOVP_SC_OFFSET_uV 7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BQ25960_BUSOVP_SC_OFFSET_uV 7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BQ25980_BUSOVP_BYP_STEP_uV 50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BQ25975_BUSOVP_BYP_STEP_uV 25000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BQ25960_BUSOVP_BYP_STEP_uV 25000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BQ25980_BUSOVP_BYP_OFFSET_uV 7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BQ25975_BUSOVP_BYP_OFFSET_uV 3500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BQ25960_BUSOVP_BYP_OFFSET_uV 3500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BQ25980_BUSOVP_DFLT_uV 17800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BQ25980_BUSOVP_BYPASS_DFLT_uV 8900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BQ25975_BUSOVP_DFLT_uV 8900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BQ25975_BUSOVP_BYPASS_DFLT_uV 4450000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BQ25960_BUSOVP_DFLT_uV 8900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BQ25980_BUSOVP_SC_MIN_uV 14000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BQ25975_BUSOVP_SC_MIN_uV 7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BQ25960_BUSOVP_SC_MIN_uV 7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BQ25980_BUSOVP_BYP_MIN_uV 7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BQ25975_BUSOVP_BYP_MIN_uV 3500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BQ25960_BUSOVP_BYP_MIN_uV 3500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BQ25980_BUSOVP_SC_MAX_uV 22000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BQ25975_BUSOVP_SC_MAX_uV 12750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BQ25960_BUSOVP_SC_MAX_uV 12750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BQ25980_BUSOVP_BYP_MAX_uV 12750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BQ25975_BUSOVP_BYP_MAX_uV 6500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BQ25960_BUSOVP_BYP_MAX_uV 6500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BQ25980_BATOVP_STEP_uV 20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BQ25975_BATOVP_STEP_uV 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BQ25960_BATOVP_STEP_uV 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BQ25980_BATOVP_OFFSET_uV 7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BQ25975_BATOVP_OFFSET_uV 3500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BQ25960_BATOVP_OFFSET_uV 3500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BQ25980_BATOVP_DFLT_uV 14000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BQ25975_BATOVP_DFLT_uV 8900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BQ25960_BATOVP_DFLT_uV 8900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BQ25980_BATOVP_MIN_uV 7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BQ25975_BATOVP_MIN_uV 3500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BQ25960_BATOVP_MIN_uV 3500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BQ25980_BATOVP_MAX_uV 9540000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BQ25975_BATOVP_MAX_uV 4770000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BQ25960_BATOVP_MAX_uV 4770000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define BQ25980_BATOCP_STEP_uA 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BQ25980_BATOCP_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BQ25980_BATOCP_DFLT_uA 8100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BQ25960_BATOCP_DFLT_uA 6100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BQ25980_BATOCP_MIN_uA 2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BQ25980_BATOCP_MAX_uA 11000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BQ25975_BATOCP_MAX_uA 11000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BQ25960_BATOCP_MAX_uA 7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BQ25980_ENABLE_HIZ 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BQ25980_DISABLE_HIZ 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BQ25980_EN_BYPASS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BQ25980_STAT1_OVP_MASK (BIT(6) | BIT(5) | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BQ25980_STAT3_OVP_MASK (BIT(7) | BIT(6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BQ25980_STAT1_OCP_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BQ25980_STAT2_OCP_MASK (BIT(6) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BQ25980_STAT4_TFLT_MASK GENMASK(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BQ25980_WD_STAT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BQ25980_PRESENT_MASK GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BQ25980_CHG_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BQ25980_EN_HIZ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define BQ25980_ADC_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define BQ25980_ADC_VOLT_STEP_uV 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BQ25980_ADC_CURR_STEP_uA 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BQ25980_ADC_POLARITY_BIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BQ25980_WATCHDOG_MASK GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BQ25980_WATCHDOG_DIS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BQ25980_WATCHDOG_MAX 300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BQ25980_WATCHDOG_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BQ25980_NUM_WD_VAL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif /* BQ25980_CHARGER_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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