^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // BQ25980 Battery Charger Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/power_supply.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "bq25980_charger.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct bq25980_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) bool dischg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) bool ovp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) bool ocp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) bool wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) bool tflt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) bool online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) bool ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) bool hiz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 vbat_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 vsys_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 ibat_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum bq25980_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) BQ25980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) BQ25975,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) BQ25960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct bq25980_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int model_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct regmap_config *regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int busocp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int busocp_sc_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int busocp_byp_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int busocp_sc_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int busocp_byp_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int busovp_sc_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int busovp_byp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int busovp_sc_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int busovp_sc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int busovp_byp_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int busovp_byp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int busovp_sc_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int busovp_sc_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int busovp_byp_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int busovp_byp_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int batovp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int batovp_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int batovp_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int batovp_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int batovp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int batocp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int batocp_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct bq25980_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 ichg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 bypass_ilim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 sc_ilim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 iterm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 iprechg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 bypass_vlim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 sc_vlim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 ichg_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 vreg_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct bq25980_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct power_supply *charger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct power_supply *battery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) char model_name[I2C_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct bq25980_init_data init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct bq25980_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct bq25980_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int watchdog_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct reg_default bq25980_reg_defs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {BQ25980_BATOVP, 0x5A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {BQ25980_BATOVP_ALM, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {BQ25980_BATOCP, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {BQ25980_BATOCP_ALM, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {BQ25980_BATUCP_ALM, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {BQ25980_CHRGR_CTRL_1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {BQ25980_BUSOVP, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {BQ25980_BUSOVP_ALM, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {BQ25980_BUSOCP, 0xD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {BQ25980_BUSOCP_ALM, 0xC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {BQ25980_TEMP_CONTROL, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {BQ25980_TDIE_ALM, 0xC8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {BQ25980_TSBUS_FLT, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {BQ25980_TSBAT_FLG, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {BQ25980_VAC_CONTROL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {BQ25980_CHRGR_CTRL_2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {BQ25980_CHRGR_CTRL_3, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {BQ25980_CHRGR_CTRL_4, 0x1D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {BQ25980_CHRGR_CTRL_5, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {BQ25980_STAT1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {BQ25980_STAT2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {BQ25980_STAT3, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {BQ25980_STAT4, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {BQ25980_STAT5, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {BQ25980_FLAG1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {BQ25980_FLAG2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {BQ25980_FLAG3, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {BQ25980_FLAG4, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {BQ25980_FLAG5, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {BQ25980_MASK1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {BQ25980_MASK2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {BQ25980_MASK3, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {BQ25980_MASK4, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {BQ25980_MASK5, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {BQ25980_DEVICE_INFO, 0x8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {BQ25980_ADC_CONTROL1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {BQ25980_ADC_CONTROL2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {BQ25980_IBUS_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {BQ25980_IBUS_ADC_MSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {BQ25980_VBUS_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {BQ25980_VBUS_ADC_MSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {BQ25980_VAC1_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {BQ25980_VAC2_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {BQ25980_VOUT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {BQ25980_VBAT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {BQ25980_IBAT_ADC_MSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {BQ25980_IBAT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {BQ25980_TSBUS_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {BQ25980_TSBAT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {BQ25980_TDIE_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {BQ25980_DEGLITCH_TIME, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {BQ25980_CHRGR_CTRL_6, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct reg_default bq25975_reg_defs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {BQ25980_BATOVP, 0x5A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {BQ25980_BATOVP_ALM, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {BQ25980_BATOCP, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {BQ25980_BATOCP_ALM, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {BQ25980_BATUCP_ALM, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {BQ25980_CHRGR_CTRL_1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {BQ25980_BUSOVP, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {BQ25980_BUSOVP_ALM, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {BQ25980_BUSOCP, 0xD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {BQ25980_BUSOCP_ALM, 0xC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {BQ25980_TEMP_CONTROL, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {BQ25980_TDIE_ALM, 0xC8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {BQ25980_TSBUS_FLT, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {BQ25980_TSBAT_FLG, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {BQ25980_VAC_CONTROL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {BQ25980_CHRGR_CTRL_2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {BQ25980_CHRGR_CTRL_3, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {BQ25980_CHRGR_CTRL_4, 0x1D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {BQ25980_CHRGR_CTRL_5, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {BQ25980_STAT1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {BQ25980_STAT2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {BQ25980_STAT3, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {BQ25980_STAT4, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {BQ25980_STAT5, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {BQ25980_FLAG1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {BQ25980_FLAG2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {BQ25980_FLAG3, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {BQ25980_FLAG4, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {BQ25980_FLAG5, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {BQ25980_MASK1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {BQ25980_MASK2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {BQ25980_MASK3, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {BQ25980_MASK4, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {BQ25980_MASK5, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {BQ25980_DEVICE_INFO, 0x8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {BQ25980_ADC_CONTROL1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {BQ25980_ADC_CONTROL2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {BQ25980_IBUS_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {BQ25980_IBUS_ADC_MSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {BQ25980_VBUS_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {BQ25980_VBUS_ADC_MSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {BQ25980_VAC1_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {BQ25980_VAC2_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {BQ25980_VOUT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {BQ25980_VBAT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {BQ25980_IBAT_ADC_MSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {BQ25980_IBAT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {BQ25980_TSBUS_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {BQ25980_TSBAT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {BQ25980_TDIE_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {BQ25980_DEGLITCH_TIME, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {BQ25980_CHRGR_CTRL_6, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct reg_default bq25960_reg_defs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {BQ25980_BATOVP, 0x5A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {BQ25980_BATOVP_ALM, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {BQ25980_BATOCP, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {BQ25980_BATOCP_ALM, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {BQ25980_BATUCP_ALM, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {BQ25980_CHRGR_CTRL_1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {BQ25980_BUSOVP, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {BQ25980_BUSOVP_ALM, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {BQ25980_BUSOCP, 0xD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {BQ25980_BUSOCP_ALM, 0xC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {BQ25980_TEMP_CONTROL, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {BQ25980_TDIE_ALM, 0xC8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {BQ25980_TSBUS_FLT, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {BQ25980_TSBAT_FLG, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {BQ25980_VAC_CONTROL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {BQ25980_CHRGR_CTRL_2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {BQ25980_CHRGR_CTRL_3, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {BQ25980_CHRGR_CTRL_4, 0x1D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {BQ25980_CHRGR_CTRL_5, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {BQ25980_STAT1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {BQ25980_STAT2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {BQ25980_STAT3, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {BQ25980_STAT4, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {BQ25980_STAT5, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {BQ25980_FLAG1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {BQ25980_FLAG2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {BQ25980_FLAG3, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {BQ25980_FLAG4, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {BQ25980_FLAG5, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {BQ25980_MASK1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {BQ25980_MASK2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {BQ25980_MASK3, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {BQ25980_MASK4, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {BQ25980_MASK5, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {BQ25980_DEVICE_INFO, 0x8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {BQ25980_ADC_CONTROL1, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {BQ25980_ADC_CONTROL2, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {BQ25980_IBUS_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {BQ25980_IBUS_ADC_MSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {BQ25980_VBUS_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {BQ25980_VBUS_ADC_MSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {BQ25980_VAC1_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {BQ25980_VAC2_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {BQ25980_VOUT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {BQ25980_VBAT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {BQ25980_IBAT_ADC_MSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {BQ25980_IBAT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {BQ25980_TSBUS_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {BQ25980_TSBAT_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {BQ25980_TDIE_ADC_LSB, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {BQ25980_DEGLITCH_TIME, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {BQ25980_CHRGR_CTRL_6, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int bq25980_watchdog_time[BQ25980_NUM_WD_VAL] = {5000, 10000, 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 300000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int bq25980_get_input_curr_lim(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int busocp_reg_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = regmap_read(bq->regmap, BQ25980_BUSOCP, &busocp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return (busocp_reg_code * BQ25980_BUSOCP_STEP_uA) + BQ25980_BUSOCP_OFFSET_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int bq25980_set_hiz(struct bq25980_device *bq, int setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) BQ25980_EN_HIZ, setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int bq25980_set_input_curr_lim(struct bq25980_device *bq, int busocp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int busocp_reg_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!busocp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return bq25980_set_hiz(bq, BQ25980_ENABLE_HIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bq25980_set_hiz(bq, BQ25980_DISABLE_HIZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (busocp < BQ25980_BUSOCP_MIN_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) busocp = BQ25980_BUSOCP_MIN_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (bq->state.bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) busocp = min(busocp, bq->chip_info->busocp_sc_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) busocp = min(busocp, bq->chip_info->busocp_byp_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) busocp_reg_code = (busocp - BQ25980_BUSOCP_OFFSET_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) / BQ25980_BUSOCP_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = regmap_write(bq->regmap, BQ25980_BUSOCP, busocp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return regmap_write(bq->regmap, BQ25980_BUSOCP_ALM, busocp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int bq25980_get_input_volt_lim(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int busovp_reg_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int busovp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int busovp_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (bq->state.bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) busovp_step = bq->chip_info->busovp_byp_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) busovp_offset = bq->chip_info->busovp_byp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) busovp_step = bq->chip_info->busovp_sc_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) busovp_offset = bq->chip_info->busovp_sc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = regmap_read(bq->regmap, BQ25980_BUSOVP, &busovp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return (busovp_reg_code * busovp_step) + busovp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int bq25980_set_input_volt_lim(struct bq25980_device *bq, int busovp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int busovp_reg_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned int busovp_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned int busovp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (bq->state.bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) busovp_step = bq->chip_info->busovp_byp_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) busovp_offset = bq->chip_info->busovp_byp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (busovp > bq->chip_info->busovp_byp_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) busovp = bq->chip_info->busovp_byp_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else if (busovp < bq->chip_info->busovp_byp_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) busovp = bq->chip_info->busovp_byp_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) busovp_step = bq->chip_info->busovp_sc_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) busovp_offset = bq->chip_info->busovp_sc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (busovp > bq->chip_info->busovp_sc_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) busovp = bq->chip_info->busovp_sc_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) else if (busovp < bq->chip_info->busovp_sc_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) busovp = bq->chip_info->busovp_sc_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) busovp_reg_code = (busovp - busovp_offset) / busovp_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = regmap_write(bq->regmap, BQ25980_BUSOVP, busovp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return regmap_write(bq->regmap, BQ25980_BUSOVP_ALM, busovp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int bq25980_get_const_charge_curr(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int batocp_reg_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = regmap_read(bq->regmap, BQ25980_BATOCP, &batocp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return (batocp_reg_code & BQ25980_BATOCP_MASK) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) BQ25980_BATOCP_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int bq25980_set_const_charge_curr(struct bq25980_device *bq, int batocp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int batocp_reg_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) batocp = max(batocp, BQ25980_BATOCP_MIN_uA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) batocp = min(batocp, bq->chip_info->batocp_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) batocp_reg_code = batocp / BQ25980_BATOCP_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = regmap_update_bits(bq->regmap, BQ25980_BATOCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) BQ25980_BATOCP_MASK, batocp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return regmap_update_bits(bq->regmap, BQ25980_BATOCP_ALM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) BQ25980_BATOCP_MASK, batocp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int bq25980_get_const_charge_volt(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int batovp_reg_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = regmap_read(bq->regmap, BQ25980_BATOVP, &batovp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return ((batovp_reg_code * bq->chip_info->batovp_step) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bq->chip_info->batovp_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int bq25980_set_const_charge_volt(struct bq25980_device *bq, int batovp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int batovp_reg_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (batovp < bq->chip_info->batovp_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) batovp = bq->chip_info->batovp_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (batovp > bq->chip_info->batovp_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) batovp = bq->chip_info->batovp_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) batovp_reg_code = (batovp - bq->chip_info->batovp_offset) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) bq->chip_info->batovp_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = regmap_write(bq->regmap, BQ25980_BATOVP, batovp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return regmap_write(bq->regmap, BQ25980_BATOVP_ALM, batovp_reg_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int bq25980_set_bypass(struct bq25980_device *bq, bool en_bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (en_bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) BQ25980_EN_BYPASS, BQ25980_EN_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) BQ25980_EN_BYPASS, en_bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) bq->state.bypass = en_bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return bq->state.bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int bq25980_set_chg_en(struct bq25980_device *bq, bool en_chg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (en_chg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) BQ25980_CHG_EN, BQ25980_CHG_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) BQ25980_CHG_EN, en_chg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) bq->state.ce = en_chg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int bq25980_get_adc_ibus(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int ibus_adc_lsb, ibus_adc_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u16 ibus_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = regmap_read(bq->regmap, BQ25980_IBUS_ADC_MSB, &ibus_adc_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = regmap_read(bq->regmap, BQ25980_IBUS_ADC_LSB, &ibus_adc_lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ibus_adc = (ibus_adc_msb << 8) | ibus_adc_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ibus_adc_msb & BQ25980_ADC_POLARITY_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return ((ibus_adc ^ 0xffff) + 1) * BQ25980_ADC_CURR_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ibus_adc * BQ25980_ADC_CURR_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int bq25980_get_adc_vbus(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int vbus_adc_lsb, vbus_adc_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u16 vbus_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = regmap_read(bq->regmap, BQ25980_VBUS_ADC_MSB, &vbus_adc_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = regmap_read(bq->regmap, BQ25980_VBUS_ADC_LSB, &vbus_adc_lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) vbus_adc = (vbus_adc_msb << 8) | vbus_adc_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return vbus_adc * BQ25980_ADC_VOLT_STEP_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int bq25980_get_ibat_adc(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int ibat_adc_lsb, ibat_adc_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int ibat_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = regmap_read(bq->regmap, BQ25980_IBAT_ADC_MSB, &ibat_adc_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = regmap_read(bq->regmap, BQ25980_IBAT_ADC_LSB, &ibat_adc_lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ibat_adc = (ibat_adc_msb << 8) | ibat_adc_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ibat_adc_msb & BQ25980_ADC_POLARITY_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return ((ibat_adc ^ 0xffff) + 1) * BQ25980_ADC_CURR_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ibat_adc * BQ25980_ADC_CURR_STEP_uA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int bq25980_get_adc_vbat(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int vsys_adc_lsb, vsys_adc_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u16 vsys_adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = regmap_read(bq->regmap, BQ25980_VBAT_ADC_MSB, &vsys_adc_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = regmap_read(bq->regmap, BQ25980_VBAT_ADC_LSB, &vsys_adc_lsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) vsys_adc = (vsys_adc_msb << 8) | vsys_adc_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return vsys_adc * BQ25980_ADC_VOLT_STEP_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int bq25980_get_state(struct bq25980_device *bq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct bq25980_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned int chg_ctrl_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned int stat1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned int stat2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned int stat3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned int stat4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned int ibat_adc_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = regmap_read(bq->regmap, BQ25980_STAT1, &stat1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = regmap_read(bq->regmap, BQ25980_STAT2, &stat2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = regmap_read(bq->regmap, BQ25980_STAT3, &stat3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = regmap_read(bq->regmap, BQ25980_STAT4, &stat4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = regmap_read(bq->regmap, BQ25980_CHRGR_CTRL_2, &chg_ctrl_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = regmap_read(bq->regmap, BQ25980_IBAT_ADC_MSB, &ibat_adc_msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) state->dischg = ibat_adc_msb & BQ25980_ADC_POLARITY_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) state->ovp = (stat1 & BQ25980_STAT1_OVP_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) (stat3 & BQ25980_STAT3_OVP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) state->ocp = (stat1 & BQ25980_STAT1_OCP_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (stat2 & BQ25980_STAT2_OCP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) state->tflt = stat4 & BQ25980_STAT4_TFLT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) state->wdt = stat4 & BQ25980_WD_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) state->online = stat3 & BQ25980_PRESENT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) state->ce = chg_ctrl_2 & BQ25980_CHG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) state->hiz = chg_ctrl_2 & BQ25980_EN_HIZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) state->bypass = chg_ctrl_2 & BQ25980_EN_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int bq25980_get_battery_property(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) enum power_supply_property psp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct bq25980_device *bq = power_supply_get_drvdata(psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) switch (psp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) val->intval = bq->init_data.ichg_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val->intval = bq->init_data.vreg_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case POWER_SUPPLY_PROP_CURRENT_NOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = bq25980_get_ibat_adc(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) val->intval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) case POWER_SUPPLY_PROP_VOLTAGE_NOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = bq25980_get_adc_vbat(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) val->intval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int bq25980_set_charger_property(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) enum power_supply_property prop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) const union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct bq25980_device *bq = power_supply_get_drvdata(psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) switch (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = bq25980_set_input_curr_lim(bq, val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = bq25980_set_input_volt_lim(bq, val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case POWER_SUPPLY_PROP_CHARGE_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = bq25980_set_bypass(bq, val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) case POWER_SUPPLY_PROP_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = bq25980_set_chg_en(bq, val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ret = bq25980_set_const_charge_curr(bq, val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = bq25980_set_const_charge_volt(bq, val->intval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int bq25980_get_charger_property(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) enum power_supply_property psp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) union power_supply_propval *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct bq25980_device *bq = power_supply_get_drvdata(psy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct bq25980_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) mutex_lock(&bq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = bq25980_get_state(bq, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) mutex_unlock(&bq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) switch (psp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case POWER_SUPPLY_PROP_MANUFACTURER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) val->strval = BQ25980_MANUFACTURER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case POWER_SUPPLY_PROP_MODEL_NAME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) val->strval = bq->model_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case POWER_SUPPLY_PROP_ONLINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) val->intval = state.online;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ret = bq25980_get_input_volt_lim(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) val->intval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = bq25980_get_input_curr_lim(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) val->intval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case POWER_SUPPLY_PROP_HEALTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) val->intval = POWER_SUPPLY_HEALTH_GOOD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (state.tflt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) val->intval = POWER_SUPPLY_HEALTH_OVERHEAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) else if (state.ovp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) val->intval = POWER_SUPPLY_HEALTH_OVERVOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) else if (state.ocp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) val->intval = POWER_SUPPLY_HEALTH_OVERCURRENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) else if (state.wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) val->intval =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) POWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) case POWER_SUPPLY_PROP_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if ((state.ce) && (!state.hiz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) val->intval = POWER_SUPPLY_STATUS_CHARGING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) else if (state.dischg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) else if (!state.ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case POWER_SUPPLY_PROP_CHARGE_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) val->intval = POWER_SUPPLY_CHARGE_TYPE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!state.ce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) else if (state.bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) val->intval = POWER_SUPPLY_CHARGE_TYPE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) else if (!state.bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) val->intval = POWER_SUPPLY_CHARGE_TYPE_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case POWER_SUPPLY_PROP_CURRENT_NOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = bq25980_get_adc_ibus(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) val->intval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case POWER_SUPPLY_PROP_VOLTAGE_NOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret = bq25980_get_adc_vbus(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) val->intval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ret = bq25980_get_const_charge_curr(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) val->intval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = bq25980_get_const_charge_volt(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) val->intval = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static bool bq25980_state_changed(struct bq25980_device *bq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct bq25980_state *new_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct bq25980_state old_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mutex_lock(&bq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) old_state = bq->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mutex_unlock(&bq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return (old_state.dischg != new_state->dischg ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) old_state.ovp != new_state->ovp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) old_state.ocp != new_state->ocp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) old_state.online != new_state->online ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) old_state.wdt != new_state->wdt ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) old_state.tflt != new_state->tflt ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) old_state.ce != new_state->ce ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) old_state.hiz != new_state->hiz ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) old_state.bypass != new_state->bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static irqreturn_t bq25980_irq_handler_thread(int irq, void *private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct bq25980_device *bq = private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct bq25980_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = bq25980_get_state(bq, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) goto irq_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (!bq25980_state_changed(bq, &state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) goto irq_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mutex_lock(&bq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) bq->state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mutex_unlock(&bq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) power_supply_changed(bq->charger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) irq_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static enum power_supply_property bq25980_power_supply_props[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) POWER_SUPPLY_PROP_MANUFACTURER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) POWER_SUPPLY_PROP_MODEL_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) POWER_SUPPLY_PROP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) POWER_SUPPLY_PROP_ONLINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) POWER_SUPPLY_PROP_HEALTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) POWER_SUPPLY_PROP_CHARGE_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) POWER_SUPPLY_PROP_CURRENT_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) POWER_SUPPLY_PROP_VOLTAGE_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static enum power_supply_property bq25980_battery_props[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) POWER_SUPPLY_PROP_CURRENT_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) POWER_SUPPLY_PROP_VOLTAGE_NOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static char *bq25980_charger_supplied_to[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) "main-battery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int bq25980_property_is_writeable(struct power_supply *psy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) enum power_supply_property prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) switch (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case POWER_SUPPLY_PROP_CHARGE_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case POWER_SUPPLY_PROP_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const struct power_supply_desc bq25980_power_supply_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .name = "bq25980-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .type = POWER_SUPPLY_TYPE_MAINS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .properties = bq25980_power_supply_props,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .num_properties = ARRAY_SIZE(bq25980_power_supply_props),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .get_property = bq25980_get_charger_property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .set_property = bq25980_set_charger_property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .property_is_writeable = bq25980_property_is_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static struct power_supply_desc bq25980_battery_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .name = "bq25980-battery",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .type = POWER_SUPPLY_TYPE_BATTERY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .get_property = bq25980_get_battery_property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .properties = bq25980_battery_props,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .num_properties = ARRAY_SIZE(bq25980_battery_props),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .property_is_writeable = bq25980_property_is_writeable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static bool bq25980_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case BQ25980_CHRGR_CTRL_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) case BQ25980_STAT1...BQ25980_FLAG5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) case BQ25980_ADC_CONTROL1...BQ25980_TDIE_ADC_LSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static const struct regmap_config bq25980_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .max_register = BQ25980_CHRGR_CTRL_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .reg_defaults = bq25980_reg_defs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .num_reg_defaults = ARRAY_SIZE(bq25980_reg_defs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .volatile_reg = bq25980_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const struct regmap_config bq25975_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .max_register = BQ25980_CHRGR_CTRL_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .reg_defaults = bq25975_reg_defs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .num_reg_defaults = ARRAY_SIZE(bq25975_reg_defs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .volatile_reg = bq25980_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const struct regmap_config bq25960_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .max_register = BQ25980_CHRGR_CTRL_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .reg_defaults = bq25960_reg_defs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .num_reg_defaults = ARRAY_SIZE(bq25960_reg_defs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .volatile_reg = bq25980_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static const struct bq25980_chip_info bq25980_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) [BQ25980] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .model_id = BQ25980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .regmap_config = &bq25980_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .busocp_def = BQ25980_BUSOCP_DFLT_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .busocp_sc_min = BQ25960_BUSOCP_SC_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .busocp_sc_max = BQ25980_BUSOCP_SC_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .busocp_byp_max = BQ25980_BUSOCP_BYP_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .busocp_byp_min = BQ25980_BUSOCP_MIN_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .busovp_sc_def = BQ25980_BUSOVP_DFLT_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .busovp_byp_def = BQ25980_BUSOVP_BYPASS_DFLT_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .busovp_sc_step = BQ25980_BUSOVP_SC_STEP_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .busovp_sc_offset = BQ25980_BUSOVP_SC_OFFSET_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .busovp_byp_step = BQ25980_BUSOVP_BYP_STEP_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .busovp_byp_offset = BQ25980_BUSOVP_BYP_OFFSET_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .busovp_sc_min = BQ25980_BUSOVP_SC_MIN_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .busovp_sc_max = BQ25980_BUSOVP_SC_MAX_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .busovp_byp_min = BQ25980_BUSOVP_BYP_MIN_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .busovp_byp_max = BQ25980_BUSOVP_BYP_MAX_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .batovp_def = BQ25980_BATOVP_DFLT_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .batovp_max = BQ25980_BATOVP_MAX_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .batovp_min = BQ25980_BATOVP_MIN_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .batovp_step = BQ25980_BATOVP_STEP_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .batovp_offset = BQ25980_BATOVP_OFFSET_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .batocp_def = BQ25980_BATOCP_DFLT_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .batocp_max = BQ25980_BATOCP_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [BQ25975] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .model_id = BQ25975,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .regmap_config = &bq25975_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .busocp_def = BQ25975_BUSOCP_DFLT_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .busocp_sc_min = BQ25975_BUSOCP_SC_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .busocp_sc_max = BQ25975_BUSOCP_SC_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .busocp_byp_min = BQ25980_BUSOCP_MIN_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .busocp_byp_max = BQ25975_BUSOCP_BYP_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .busovp_sc_def = BQ25975_BUSOVP_DFLT_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .busovp_byp_def = BQ25975_BUSOVP_BYPASS_DFLT_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .busovp_sc_step = BQ25975_BUSOVP_SC_STEP_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .busovp_sc_offset = BQ25975_BUSOVP_SC_OFFSET_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .busovp_byp_step = BQ25975_BUSOVP_BYP_STEP_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .busovp_byp_offset = BQ25975_BUSOVP_BYP_OFFSET_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .busovp_sc_min = BQ25975_BUSOVP_SC_MIN_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .busovp_sc_max = BQ25975_BUSOVP_SC_MAX_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .busovp_byp_min = BQ25975_BUSOVP_BYP_MIN_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .busovp_byp_max = BQ25975_BUSOVP_BYP_MAX_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .batovp_def = BQ25975_BATOVP_DFLT_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .batovp_max = BQ25975_BATOVP_MAX_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .batovp_min = BQ25975_BATOVP_MIN_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .batovp_step = BQ25975_BATOVP_STEP_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .batovp_offset = BQ25975_BATOVP_OFFSET_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .batocp_def = BQ25980_BATOCP_DFLT_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .batocp_max = BQ25980_BATOCP_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [BQ25960] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .model_id = BQ25960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .regmap_config = &bq25960_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .busocp_def = BQ25960_BUSOCP_DFLT_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .busocp_sc_min = BQ25960_BUSOCP_SC_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .busocp_sc_max = BQ25960_BUSOCP_SC_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .busocp_byp_min = BQ25960_BUSOCP_SC_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .busocp_byp_max = BQ25960_BUSOCP_BYP_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .busovp_sc_def = BQ25975_BUSOVP_DFLT_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .busovp_byp_def = BQ25975_BUSOVP_BYPASS_DFLT_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .busovp_sc_step = BQ25960_BUSOVP_SC_STEP_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .busovp_sc_offset = BQ25960_BUSOVP_SC_OFFSET_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .busovp_byp_step = BQ25960_BUSOVP_BYP_STEP_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .busovp_byp_offset = BQ25960_BUSOVP_BYP_OFFSET_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .busovp_sc_min = BQ25960_BUSOVP_SC_MIN_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .busovp_sc_max = BQ25960_BUSOVP_SC_MAX_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .busovp_byp_min = BQ25960_BUSOVP_BYP_MIN_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .busovp_byp_max = BQ25960_BUSOVP_BYP_MAX_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .batovp_def = BQ25960_BATOVP_DFLT_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .batovp_max = BQ25960_BATOVP_MAX_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .batovp_min = BQ25960_BATOVP_MIN_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .batovp_step = BQ25960_BATOVP_STEP_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .batovp_offset = BQ25960_BATOVP_OFFSET_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .batocp_def = BQ25960_BATOCP_DFLT_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .batocp_max = BQ25960_BATOCP_MAX_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int bq25980_power_supply_init(struct bq25980_device *bq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct power_supply_config psy_cfg = { .drv_data = bq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .of_node = dev->of_node, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) psy_cfg.supplied_to = bq25980_charger_supplied_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) psy_cfg.num_supplicants = ARRAY_SIZE(bq25980_charger_supplied_to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) bq->charger = devm_power_supply_register(bq->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) &bq25980_power_supply_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) &psy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (IS_ERR(bq->charger))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) bq->battery = devm_power_supply_register(bq->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) &bq25980_battery_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) &psy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (IS_ERR(bq->battery))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int bq25980_hw_init(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct power_supply_battery_info bat_info = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int wd_reg_val = BQ25980_WATCHDOG_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) int wd_max_val = BQ25980_NUM_WD_VAL - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int curr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) int volt_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (bq->watchdog_timer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (bq->watchdog_timer >= bq25980_watchdog_time[wd_max_val])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) wd_reg_val = wd_max_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) for (i = 0; i < wd_max_val; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (bq->watchdog_timer > bq25980_watchdog_time[i] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) bq->watchdog_timer < bq25980_watchdog_time[i + 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) wd_reg_val = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) BQ25980_WATCHDOG_MASK, wd_reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = power_supply_get_battery_info(bq->charger, &bat_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dev_warn(bq->dev, "battery info missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) bq->init_data.ichg_max = bat_info.constant_charge_current_max_ua;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) bq->init_data.vreg_max = bat_info.constant_charge_voltage_max_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (bq->state.bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = regmap_update_bits(bq->regmap, BQ25980_CHRGR_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) BQ25980_EN_BYPASS, BQ25980_EN_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) curr_val = bq->init_data.bypass_ilim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) volt_val = bq->init_data.bypass_vlim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) curr_val = bq->init_data.sc_ilim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) volt_val = bq->init_data.sc_vlim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = bq25980_set_input_curr_lim(bq, curr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ret = bq25980_set_input_volt_lim(bq, volt_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return regmap_update_bits(bq->regmap, BQ25980_ADC_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) BQ25980_ADC_EN, BQ25980_ADC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int bq25980_parse_dt(struct bq25980_device *bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ret = device_property_read_u32(bq->dev, "ti,watchdog-timeout-ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) &bq->watchdog_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) bq->watchdog_timer = BQ25980_WATCHDOG_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (bq->watchdog_timer > BQ25980_WATCHDOG_MAX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) bq->watchdog_timer < BQ25980_WATCHDOG_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ret = device_property_read_u32(bq->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) "ti,sc-ovp-limit-microvolt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) &bq->init_data.sc_vlim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) bq->init_data.sc_vlim = bq->chip_info->busovp_sc_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (bq->init_data.sc_vlim > bq->chip_info->busovp_sc_max ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) bq->init_data.sc_vlim < bq->chip_info->busovp_sc_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dev_err(bq->dev, "SC ovp limit is out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret = device_property_read_u32(bq->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) "ti,sc-ocp-limit-microamp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) &bq->init_data.sc_ilim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) bq->init_data.sc_ilim = bq->chip_info->busocp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (bq->init_data.sc_ilim > bq->chip_info->busocp_sc_max ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) bq->init_data.sc_ilim < bq->chip_info->busocp_sc_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) dev_err(bq->dev, "SC ocp limit is out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ret = device_property_read_u32(bq->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) "ti,bypass-ovp-limit-microvolt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) &bq->init_data.bypass_vlim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) bq->init_data.bypass_vlim = bq->chip_info->busovp_byp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (bq->init_data.bypass_vlim > bq->chip_info->busovp_byp_max ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) bq->init_data.bypass_vlim < bq->chip_info->busovp_byp_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dev_err(bq->dev, "Bypass ovp limit is out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ret = device_property_read_u32(bq->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) "ti,bypass-ocp-limit-microamp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) &bq->init_data.bypass_ilim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) bq->init_data.bypass_ilim = bq->chip_info->busocp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (bq->init_data.bypass_ilim > bq->chip_info->busocp_byp_max ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) bq->init_data.bypass_ilim < bq->chip_info->busocp_byp_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dev_err(bq->dev, "Bypass ocp limit is out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) bq->state.bypass = device_property_read_bool(bq->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) "ti,bypass-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int bq25980_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct bq25980_device *bq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) bq = devm_kzalloc(dev, sizeof(*bq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (!bq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) bq->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) bq->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) mutex_init(&bq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) strncpy(bq->model_name, id->name, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) bq->chip_info = &bq25980_chip_info_tbl[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) bq->regmap = devm_regmap_init_i2c(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) bq->chip_info->regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (IS_ERR(bq->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) dev_err(dev, "Failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return PTR_ERR(bq->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) i2c_set_clientdata(client, bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret = bq25980_parse_dt(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_err(dev, "Failed to read device tree properties%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = devm_request_threaded_irq(dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) bq25980_irq_handler_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) IRQF_TRIGGER_FALLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dev_name(&client->dev), bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ret = bq25980_power_supply_init(bq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dev_err(dev, "Failed to register power supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ret = bq25980_hw_init(bq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) dev_err(dev, "Cannot initialize the chip.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static const struct i2c_device_id bq25980_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) { "bq25980", BQ25980 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) { "bq25975", BQ25975 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) { "bq25975", BQ25975 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) MODULE_DEVICE_TABLE(i2c, bq25980_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const struct of_device_id bq25980_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) { .compatible = "ti,bq25980", .data = (void *)BQ25980 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) { .compatible = "ti,bq25975", .data = (void *)BQ25975 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) { .compatible = "ti,bq25960", .data = (void *)BQ25960 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) MODULE_DEVICE_TABLE(of, bq25980_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static struct i2c_driver bq25980_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .name = "bq25980-charger",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .of_match_table = bq25980_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .probe = bq25980_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .id_table = bq25980_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) module_i2c_driver(bq25980_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) MODULE_AUTHOR("Ricardo Rivera-Matos <r-rivera-matos@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) MODULE_DESCRIPTION("bq25980 charger driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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