^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Microsemi MIPS SoC reset driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License: Dual MIT/GPL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017 Microsemi Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct reset_props {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) const char *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 protect_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 vcore_protect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 if_si_owner_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct ocelot_reset_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct regmap *cpu_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const struct reset_props *props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct notifier_block restart_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SOFT_CHIP_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IF_SI_OWNER_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IF_SI_OWNER_SISL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IF_SI_OWNER_SIBM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IF_SI_OWNER_SIMC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int ocelot_restart_handle(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned long mode, void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct ocelot_reset_context *ctx = container_of(this, struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ocelot_reset_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) restart_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 if_si_owner_bit = ctx->props->if_si_owner_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Make sure the core is not protected from reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ctx->props->vcore_protect, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Make the SI back to boot mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) IF_SI_OWNER_MASK << if_si_owner_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) IF_SI_OWNER_SIBM << if_si_owner_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pr_emerg("Resetting SoC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writel(SOFT_CHIP_RST, ctx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pr_emerg("Unable to restart system\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int ocelot_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct ocelot_reset_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ctx->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (IS_ERR(ctx->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return PTR_ERR(ctx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ctx->props = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible(ctx->props->syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (IS_ERR(ctx->cpu_ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_err(dev, "No syscon map: %s\n", ctx->props->syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return PTR_ERR(ctx->cpu_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ctx->restart_handler.notifier_call = ocelot_restart_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ctx->restart_handler.priority = 192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) err = register_restart_handler(&ctx->restart_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_err(dev, "can't register restart notifier (err=%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct reset_props reset_props_ocelot = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .syscon = "mscc,ocelot-cpu-syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .protect_reg = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .vcore_protect = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .if_si_owner_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct reset_props reset_props_sparx5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .syscon = "microchip,sparx5-cpu-syscon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .protect_reg = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .vcore_protect = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .if_si_owner_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct of_device_id ocelot_reset_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .compatible = "mscc,ocelot-chip-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .data = &reset_props_ocelot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .compatible = "microchip,sparx5-chip-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .data = &reset_props_sparx5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { /*sentinel*/ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct platform_driver ocelot_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .probe = ocelot_reset_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "ocelot-chip-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .of_match_table = ocelot_reset_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) builtin_platform_driver(ocelot_reset_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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