Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Atmel SAMA5D2-Compatible Shutdown Controller (SHDWC) driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Found on some SoCs as the sama5d2 (obviously).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Atmel Corporation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *                    Nicolas Ferre <nicolas.ferre@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Evolved from driver at91-poweroff.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * - addition to status of other wake-up inputs [1 - 15]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * - Analog Comparator wake-up alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * - Serial RX wake-up alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * - low power debouncer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <soc/at91/at91sam9_ddrsdr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SLOW_CLOCK_FREQ	32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AT91_SHDW_CR	0x00		/* Shut Down Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AT91_SHDW_SHDW		BIT(0)			/* Shut Down command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AT91_SHDW_KEY		(0xa5UL << 24)		/* KEY Password */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AT91_SHDW_MR	0x04		/* Shut Down Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AT91_SHDW_WKUPDBC_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AT91_SHDW_WKUPDBC_MASK	GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AT91_SHDW_WKUPDBC(x)	(((x) << AT91_SHDW_WKUPDBC_SHIFT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 						& AT91_SHDW_WKUPDBC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AT91_SHDW_SR	0x08		/* Shut Down Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AT91_SHDW_WKUPIS_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AT91_SHDW_WKUPIS_MASK	GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AT91_SHDW_WKUPIS(x)	((1 << (x)) << AT91_SHDW_WKUPIS_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 						& AT91_SHDW_WKUPIS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define AT91_SHDW_WUIR	0x0c		/* Shutdown Wake-up Inputs Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AT91_SHDW_WKUPEN_MASK	GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define AT91_SHDW_WKUPEN(x)	((1 << (x)) & AT91_SHDW_WKUPEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AT91_SHDW_WKUPT_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AT91_SHDW_WKUPT_MASK	GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AT91_SHDW_WKUPT(x)	((1 << (x)) << AT91_SHDW_WKUPT_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 						& AT91_SHDW_WKUPT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SHDW_WK_PIN(reg, cfg)	((reg) & AT91_SHDW_WKUPIS((cfg)->wkup_pin_input))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SHDW_RTCWK(reg, cfg)	(((reg) >> ((cfg)->sr_rtcwk_shift)) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SHDW_RTTWK(reg, cfg)	(((reg) >> ((cfg)->sr_rttwk_shift)) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SHDW_RTCWKEN(cfg)	(1 << ((cfg)->mr_rtcwk_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SHDW_RTTWKEN(cfg)	(1 << ((cfg)->mr_rttwk_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DBC_PERIOD_US(x)	DIV_ROUND_UP_ULL((1000000 * (x)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 							SLOW_CLOCK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SHDW_CFG_NOT_USED	(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) struct shdwc_reg_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8 wkup_pin_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u8 mr_rtcwk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u8 mr_rttwk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u8 sr_rtcwk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u8 sr_rttwk_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) struct pmc_reg_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 mckr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) struct reg_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct shdwc_reg_config shdwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct pmc_reg_config pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) struct shdwc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	const struct reg_config *rcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	void __iomem *shdwc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	void __iomem *mpddrc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	void __iomem *pmc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * Hold configuration here, cannot be more than one instance of the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * since pm_power_off itself is global.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static struct shdwc *at91_shdwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const unsigned long long sdwc_dbc_period[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	0, 3, 32, 512, 4096, 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void __init at91_wakeup_status(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct shdwc *shdw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	const struct reg_config *rcfg = shdw->rcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	char *reason = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	reg = readl(shdw->shdwc_base + AT91_SHDW_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	dev_dbg(&pdev->dev, "%s: status = %#x\n", __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* Simple power-on, just bail out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (SHDW_WK_PIN(reg, &rcfg->shdwc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		reason = "WKUP pin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	else if (SHDW_RTCWK(reg, &rcfg->shdwc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		reason = "RTC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	else if (SHDW_RTTWK(reg, &rcfg->shdwc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		reason = "RTT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	pr_info("AT91: Wake-Up source: %s\n", reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void at91_poweroff(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		/* Align to cache lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		".balign 32\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		/* Ensure AT91_SHDW_CR is in the TLB by reading it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		"	ldr	r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		/* Power down SDRAM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		"	tst	%0, #0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		"	beq	1f\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		"	str	%1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		/* Switch the master clock source to slow clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		"1:	ldr	r6, [%4, %5]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		"	bic	r6, r6,  #" __stringify(AT91_PMC_CSS) "\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		"	str	r6, [%4, %5]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		/* Wait for clock switch. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		"2:	ldr	r6, [%4, #" __stringify(AT91_PMC_SR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		"	tst	r6, #"	    __stringify(AT91_PMC_MCKRDY) "\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		"	beq	2b\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/* Shutdown CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		"	str	%3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		"	b	.\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		: "r" (at91_shdwc->mpddrc_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		  "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		  "r" (at91_shdwc->shdwc_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		  "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		  "r" (at91_shdwc->pmc_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		  "r" (at91_shdwc->rcfg->pmc.mckr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		: "r6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static u32 at91_shdwc_debouncer_value(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				      u32 in_period_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	int max_idx = ARRAY_SIZE(sdwc_dbc_period) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	unsigned long long period_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	unsigned long long max_period_us = DBC_PERIOD_US(sdwc_dbc_period[max_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (in_period_us > max_period_us) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			 "debouncer period %u too big, reduced to %llu us\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			 in_period_us, max_period_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return max_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	for (i = max_idx - 1; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		period_us = DBC_PERIOD_US(sdwc_dbc_period[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		dev_dbg(&pdev->dev, "%s: ref[%d] = %llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 						__func__, i, period_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		if (in_period_us > period_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static u32 at91_shdwc_get_wakeup_input(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				       struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct device_node *cnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 wk_input_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 wuir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u32 wk_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	for_each_child_of_node(np, cnp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (of_property_read_u32(cnp, "reg", &wk_input)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				 cnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		wk_input_mask = 1 << wk_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (!(wk_input_mask & AT91_SHDW_WKUPEN_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				 "wake-up input %d out of bounds ignore\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				 wk_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		wuir |= wk_input_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		if (of_property_read_bool(cnp, "atmel,wakeup-active-high"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			wuir |= AT91_SHDW_WKUPT(wk_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		dev_dbg(&pdev->dev, "%s: (child %d) wuir = %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 						__func__, wk_input, wuir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return wuir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void at91_shdwc_dt_configure(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct shdwc *shdw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	const struct reg_config *rcfg = shdw->rcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	u32 mode = 0, tmp, input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		dev_err(&pdev->dev, "device node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (!of_property_read_u32(np, "debounce-delay-us", &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		mode |= AT91_SHDW_WKUPDBC(at91_shdwc_debouncer_value(pdev, tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		mode |= SHDW_RTCWKEN(&rcfg->shdwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		mode |= SHDW_RTTWKEN(&rcfg->shdwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	dev_dbg(&pdev->dev, "%s: mode = %#x\n", __func__, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	writel(mode, shdw->shdwc_base + AT91_SHDW_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	input = at91_shdwc_get_wakeup_input(pdev, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	writel(input, shdw->shdwc_base + AT91_SHDW_WUIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct reg_config sama5d2_reg_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.shdwc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.wkup_pin_input = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.mr_rtcwk_shift = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.mr_rttwk_shift	= SHDW_CFG_NOT_USED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.sr_rtcwk_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.sr_rttwk_shift = SHDW_CFG_NOT_USED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.pmc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.mckr		= 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct reg_config sam9x60_reg_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.shdwc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.wkup_pin_input = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.mr_rtcwk_shift = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.mr_rttwk_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.sr_rtcwk_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.sr_rttwk_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.pmc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.mckr		= 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct of_device_id at91_shdwc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.compatible = "atmel,sama5d2-shdwc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.data = &sama5d2_reg_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.compatible = "microchip,sam9x60-shdwc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.data = &sam9x60_reg_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		/*sentinel*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_DEVICE_TABLE(of, at91_shdwc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct of_device_id at91_pmc_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	{ .compatible = "atmel,sama5d2-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	{ .compatible = "microchip,sam9x60-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	{ /* Sentinel. */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int __init at91_shdwc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	u32 ddr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (!pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (at91_shdwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	at91_shdwc = devm_kzalloc(&pdev->dev, sizeof(*at91_shdwc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (!at91_shdwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	platform_set_drvdata(pdev, at91_shdwc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	at91_shdwc->shdwc_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (IS_ERR(at91_shdwc->shdwc_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		dev_err(&pdev->dev, "Could not map reset controller address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		return PTR_ERR(at91_shdwc->shdwc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	match = of_match_node(at91_shdwc_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	at91_shdwc->rcfg = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	at91_shdwc->sclk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (IS_ERR(at91_shdwc->sclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return PTR_ERR(at91_shdwc->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	ret = clk_prepare_enable(at91_shdwc->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		dev_err(&pdev->dev, "Could not enable slow clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	at91_wakeup_status(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	at91_shdwc_dt_configure(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	np = of_find_matching_node(NULL, at91_pmc_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	at91_shdwc->pmc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (!at91_shdwc->pmc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	at91_shdwc->mpddrc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (!at91_shdwc->mpddrc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	pm_power_off = at91_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			 AT91_DDRSDRC_MD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	    ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		iounmap(at91_shdwc->mpddrc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		at91_shdwc->mpddrc_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	iounmap(at91_shdwc->pmc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	clk_disable_unprepare(at91_shdwc->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int __exit at91_shdwc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	struct shdwc *shdw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (pm_power_off == at91_poweroff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		pm_power_off = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	/* Reset values to disable wake-up features  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	writel(0, shdw->shdwc_base + AT91_SHDW_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	writel(0, shdw->shdwc_base + AT91_SHDW_WUIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (shdw->mpddrc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		iounmap(shdw->mpddrc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	iounmap(shdw->pmc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	clk_disable_unprepare(shdw->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static struct platform_driver at91_shdwc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.remove = __exit_p(at91_shdwc_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		.name = "at91-shdwc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		.of_match_table = at91_shdwc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) module_platform_driver_probe(at91_shdwc_driver, at91_shdwc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MODULE_DESCRIPTION("Atmel shutdown controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MODULE_LICENSE("GPL v2");