Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Atmel AT91 SAM9 & SAMA5 SoCs reset code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007 Atmel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) BitBox Ltd 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2014 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <soc/at91/at91sam9_ddrsdr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <soc/at91/at91sam9_sdramc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AT91_RSTC_CR	0x00		/* Reset Controller Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AT91_RSTC_PROCRST	BIT(0)		/* Processor Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AT91_RSTC_PERRST	BIT(2)		/* Peripheral Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AT91_RSTC_EXTRST	BIT(3)		/* External Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AT91_RSTC_KEY		(0xa5 << 24)	/* KEY Password */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AT91_RSTC_SR	0x04		/* Reset Controller Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AT91_RSTC_URSTS		BIT(0)		/* User Reset Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AT91_RSTC_RSTTYP	GENMASK(10, 8)	/* Reset Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AT91_RSTC_NRSTL		BIT(16)		/* NRST Pin Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AT91_RSTC_SRCMP		BIT(17)		/* Software Reset Command in Progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AT91_RSTC_MR	0x08		/* Reset Controller Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AT91_RSTC_URSTEN	BIT(0)		/* User Reset Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AT91_RSTC_URSTASYNC	BIT(2)		/* User Reset Asynchronous Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AT91_RSTC_URSTIEN	BIT(4)		/* User Reset Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AT91_RSTC_ERSTL		GENMASK(11, 8)	/* External Reset Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) enum reset_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	RESET_TYPE_GENERAL	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	RESET_TYPE_WAKEUP	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	RESET_TYPE_WATCHDOG	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	RESET_TYPE_SOFTWARE	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	RESET_TYPE_USER		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	RESET_TYPE_CPU_FAIL	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	RESET_TYPE_XTAL_FAIL	= 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	RESET_TYPE_ULP2		= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) struct at91_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	void __iomem *rstc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	void __iomem *ramc_base[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 ramc_lpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) * unless the SDRAM is cleanly shutdown before we hit the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) * reset register it can be left driving the data bus and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) * killing the chance of a subsequent boot from NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int at91_reset(struct notifier_block *this, unsigned long mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		      void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct at91_reset *reset = container_of(this, struct at91_reset, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		/* Align to cache lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		".balign 32\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		/* Disable SDRAM0 accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		"	tst	%0, #0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		"	beq	1f\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		"	str	%3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		/* Power down SDRAM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		"	str	%4, [%0, %6]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		/* Disable SDRAM1 accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		"1:	tst	%1, #0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		"	beq	2f\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		"	strne	%3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		/* Power down SDRAM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		"	strne	%4, [%1, %6]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		/* Reset CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		"2:	str	%5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		"	b	.\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		: "r" (reset->ramc_base[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		  "r" (reset->ramc_base[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		  "r" (reset->rstc_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		  "r" (1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		  "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		  "r" (reset->args),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		  "r" (reset->ramc_lpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		: "r4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void __init at91_reset_status(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				     void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	const char *reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u32 reg = readl(base + AT91_RSTC_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	switch ((reg & AT91_RSTC_RSTTYP) >> 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case RESET_TYPE_GENERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		reason = "general reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	case RESET_TYPE_WAKEUP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		reason = "wakeup";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	case RESET_TYPE_WATCHDOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		reason = "watchdog reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	case RESET_TYPE_SOFTWARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		reason = "software reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	case RESET_TYPE_USER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		reason = "user reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case RESET_TYPE_CPU_FAIL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		reason = "CPU clock failure detection";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case RESET_TYPE_XTAL_FAIL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		reason = "32.768 kHz crystal failure detection";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	case RESET_TYPE_ULP2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		reason = "ULP2 reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		reason = "unknown reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	dev_info(&pdev->dev, "Starting after %s\n", reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct of_device_id at91_ramc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.compatible = "atmel,at91sam9260-sdramc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.data = (void *)AT91_SDRAMC_LPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.compatible = "atmel,at91sam9g45-ddramc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.data = (void *)AT91_DDRSDRC_LPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct of_device_id at91_reset_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.compatible = "atmel,at91sam9260-rstc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				 AT91_RSTC_PROCRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.compatible = "atmel,at91sam9g45-rstc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				 AT91_RSTC_PROCRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.compatible = "atmel,sama5d3-rstc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				 AT91_RSTC_PROCRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.compatible = "atmel,samx7-rstc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.compatible = "microchip,sam9x60-rstc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_DEVICE_TABLE(of, at91_reset_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int __init at91_reset_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct at91_reset *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int ret, idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (!reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	reset->rstc_base = of_iomap(pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (!reset->rstc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		dev_err(&pdev->dev, "Could not map reset controller address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		/* we need to shutdown the ddr controller, so get ramc base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		for_each_matching_node_and_match(np, at91_ramc_of_match, &match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			reset->ramc_lpr = (u32)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			reset->ramc_base[idx] = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			if (!reset->ramc_base[idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				dev_err(&pdev->dev, "Could not map ram controller address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	match = of_match_node(at91_reset_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	reset->nb.notifier_call = at91_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	reset->nb.priority = 192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	reset->args = (u32)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	reset->sclk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (IS_ERR(reset->sclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return PTR_ERR(reset->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ret = clk_prepare_enable(reset->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		dev_err(&pdev->dev, "Could not enable slow clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	platform_set_drvdata(pdev, reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		u32 val = readl(reset->rstc_base + AT91_RSTC_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		       reset->rstc_base + AT91_RSTC_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	ret = register_restart_handler(&reset->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		clk_disable_unprepare(reset->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	at91_reset_status(pdev, reset->rstc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int __exit at91_reset_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct at91_reset *reset = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	unregister_restart_handler(&reset->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	clk_disable_unprepare(reset->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct platform_driver at91_reset_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.remove = __exit_p(at91_reset_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.name = "at91-reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.of_match_table = at91_reset_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) module_platform_driver_probe(at91_reset_driver, at91_reset_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_AUTHOR("Atmel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_DESCRIPTION("Reset driver for Atmel SoCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_LICENSE("GPL v2");