Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Atmel AT91 SAM9 SoCs reset code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007 Atmel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2014 Free Electrons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <soc/at91/at91sam9_ddrsdr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AT91_SHDW_CR	0x00		/* Shut Down Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AT91_SHDW_SHDW		BIT(0)			/* Shut Down command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AT91_SHDW_KEY		(0xa5 << 24)		/* KEY Password */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AT91_SHDW_MR	0x04		/* Shut Down Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AT91_SHDW_WKMODE0	GENMASK(2, 0)		/* Wake-up 0 Mode Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AT91_SHDW_CPTWK0_MAX	0xf			/* Maximum Counter On Wake Up 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AT91_SHDW_CPTWK0	(AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AT91_SHDW_CPTWK0_(x)	((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AT91_SHDW_RTTWKEN	BIT(16)			/* Real Time Timer Wake-up Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AT91_SHDW_RTCWKEN	BIT(17)			/* Real Time Clock Wake-up Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AT91_SHDW_SR	0x08		/* Shut Down Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AT91_SHDW_WAKEUP0	BIT(0)			/* Wake-up 0 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AT91_SHDW_RTTWK		BIT(16)			/* Real-time Timer Wake-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AT91_SHDW_RTCWK		BIT(17)			/* Real-time Clock Wake-up [SAM9RL] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) enum wakeup_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	AT91_SHDW_WKMODE0_NONE		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	AT91_SHDW_WKMODE0_HIGH		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	AT91_SHDW_WKMODE0_LOW		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	AT91_SHDW_WKMODE0_ANYLEVEL	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static const char *shdwc_wakeup_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	[AT91_SHDW_WKMODE0_NONE]	= "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	[AT91_SHDW_WKMODE0_HIGH]	= "high",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	[AT91_SHDW_WKMODE0_LOW]		= "low",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	[AT91_SHDW_WKMODE0_ANYLEVEL]	= "any",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static struct shdwc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	void __iomem *shdwc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	void __iomem *mpddrc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) } at91_shdwc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static void __init at91_wakeup_status(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	const char *reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u32 reg = readl(at91_shdwc.shdwc_base + AT91_SHDW_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* Simple power-on, just bail out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (reg & AT91_SHDW_RTTWK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		reason = "RTT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	else if (reg & AT91_SHDW_RTCWK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		reason = "RTC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		reason = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	dev_info(&pdev->dev, "Wake-Up source: %s\n", reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void at91_poweroff(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		/* Align to cache lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		".balign 32\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		/* Ensure AT91_SHDW_CR is in the TLB by reading it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		"	ldr	r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		/* Power down SDRAM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		"	tst	%0, #0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		"	beq	1f\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		"	str	%1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/* Shutdown CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		"1:	str	%3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		"	b	.\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		: "r" (at91_shdwc.mpddrc_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		  "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		  "r" (at91_shdwc.shdwc_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		  "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		: "r6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int at91_poweroff_get_wakeup_mode(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	const char *pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return AT91_SHDW_WKMODE0_ANYLEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int wakeup_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 mode = 0, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	wakeup_mode = at91_poweroff_get_wakeup_mode(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (wakeup_mode < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		dev_warn(&pdev->dev, "shdwc unknown wakeup mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (!of_property_read_u32(np, "atmel,wakeup-counter", &tmp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		if (tmp > AT91_SHDW_CPTWK0_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 				 "shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				 tmp, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			tmp = AT91_SHDW_CPTWK0_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		mode |= AT91_SHDW_CPTWK0_(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			mode |= AT91_SHDW_RTCWKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			mode |= AT91_SHDW_RTTWKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	writel(wakeup_mode | mode, at91_shdwc.shdwc_base + AT91_SHDW_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int __init at91_poweroff_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u32 ddr_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	at91_shdwc.shdwc_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (IS_ERR(at91_shdwc.shdwc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return PTR_ERR(at91_shdwc.shdwc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (IS_ERR(at91_shdwc.sclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return PTR_ERR(at91_shdwc.sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ret = clk_prepare_enable(at91_shdwc.sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		dev_err(&pdev->dev, "Could not enable slow clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	at91_wakeup_status(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		at91_poweroff_dt_set_wakeup_mode(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		at91_shdwc.mpddrc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (!at91_shdwc.mpddrc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		ddr_type = readl(at91_shdwc.mpddrc_base + AT91_DDRSDRC_MDR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				 AT91_DDRSDRC_MD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		    ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			iounmap(at91_shdwc.mpddrc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			at91_shdwc.mpddrc_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	pm_power_off = at91_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	clk_disable_unprepare(at91_shdwc.sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int __exit at91_poweroff_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (pm_power_off == at91_poweroff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		pm_power_off = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (at91_shdwc.mpddrc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		iounmap(at91_shdwc.mpddrc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	clk_disable_unprepare(at91_shdwc.sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct of_device_id at91_poweroff_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	{ .compatible = "atmel,at91sam9260-shdwc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	{ .compatible = "atmel,at91sam9rl-shdwc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	{ .compatible = "atmel,at91sam9x5-shdwc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	{ /*sentinel*/ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MODULE_DEVICE_TABLE(of, at91_poweroff_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct platform_driver at91_poweroff_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.remove = __exit_p(at91_poweroff_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.name = "at91-poweroff",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.of_match_table = at91_poweroff_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) module_platform_driver_probe(at91_poweroff_driver, at91_poweroff_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MODULE_AUTHOR("Atmel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MODULE_DESCRIPTION("Shutdown driver for Atmel SoCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MODULE_LICENSE("GPL v2");