Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  This file contains quirk handling code for PnP devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Some devices do not report all their resources, and need to have extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  resources added. This is most easily accomplished at initialisation time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  when building up the resource structure for the first time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Copyright (c) 2000 Peter Denison <peterd@pnd-pc.demon.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *	Bjorn Helgaas <bjorn.helgaas@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  Heavily based on PCI quirks handling which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *  Copyright (c) 1999 Martin Mares <mj@ucw.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pnp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "base.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static void quirk_awe32_add_ports(struct pnp_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 				  struct pnp_option *option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 				  unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct pnp_option *new_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	new_option = kmalloc(sizeof(struct pnp_option), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (!new_option) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		dev_err(&dev->dev, "couldn't add ioport region to option set "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			"%d\n", pnp_option_set(option));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	*new_option = *option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	new_option->u.port.min += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	new_option->u.port.max += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	list_add(&new_option->list, &option->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	dev_info(&dev->dev, "added ioport region %#llx-%#llx to set %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		(unsigned long long) new_option->u.port.min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		(unsigned long long) new_option->u.port.max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		pnp_option_set(option));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void quirk_awe32_resources(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct pnp_option *option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned int set = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 * Add two extra ioport regions (at offset 0x400 and 0x800 from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 * one given) to every dependent option set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	list_for_each_entry(option, &dev->options, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		if (pnp_option_is_dependent(option) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		    pnp_option_set(option) != set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			set = pnp_option_set(option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			quirk_awe32_add_ports(dev, option, 0x800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			quirk_awe32_add_ports(dev, option, 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static void quirk_cmi8330_resources(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct pnp_option *option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct pnp_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct pnp_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	list_for_each_entry(option, &dev->options, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		if (!pnp_option_is_dependent(option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		if (option->type == IORESOURCE_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			irq = &option->u.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			bitmap_zero(irq->map.bits, PNP_IRQ_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			__set_bit(5, irq->map.bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			__set_bit(7, irq->map.bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			__set_bit(10, irq->map.bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			dev_info(&dev->dev, "set possible IRQs in "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				 "option set %d to 5, 7, 10\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				 pnp_option_set(option));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		} else if (option->type == IORESOURCE_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			dma = &option->u.dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			if ((dma->flags & IORESOURCE_DMA_TYPE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 						IORESOURCE_DMA_8BIT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			    dma->map != 0x0A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				dev_info(&dev->dev, "changing possible "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 					 "DMA channel mask in option set %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 					 "from %#02x to 0x0A (1, 3)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 					 pnp_option_set(option), dma->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				dma->map = 0x0A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void quirk_sb16audio_resources(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct pnp_option *option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned int prev_option_flags = ~0, n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct pnp_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 * The default range on the OPL port for these devices is 0x388-0x388.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * Here we increase that range so that two such cards can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * auto-configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	list_for_each_entry(option, &dev->options, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		if (prev_option_flags != option->flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			prev_option_flags = option->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		if (pnp_option_is_dependent(option) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		    option->type == IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			port = &option->u.port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			if (n == 3 && port->min == port->max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				port->max += 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				dev_info(&dev->dev, "increased option port "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 					 "range from %#llx-%#llx to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 					 "%#llx-%#llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 					 (unsigned long long) port->min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 					 (unsigned long long) port->min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					 (unsigned long long) port->min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 					 (unsigned long long) port->max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct pnp_option *pnp_clone_dependent_set(struct pnp_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 						  unsigned int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct pnp_option *tail = NULL, *first_new_option = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct pnp_option *option, *new_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	list_for_each_entry(option, &dev->options, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (pnp_option_is_dependent(option))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			tail = option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (!tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		dev_err(&dev->dev, "no dependent option sets\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	flags = pnp_new_dependent_set(dev, PNP_RES_PRIORITY_FUNCTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	list_for_each_entry(option, &dev->options, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (pnp_option_is_dependent(option) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		    pnp_option_set(option) == set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			new_option = kmalloc(sizeof(struct pnp_option),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 					     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			if (!new_option) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				dev_err(&dev->dev, "couldn't clone dependent "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 					"set %d\n", set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			*new_option = *option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			new_option->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			if (!first_new_option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				first_new_option = new_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			list_add(&new_option->list, &tail->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			tail = new_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return first_new_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void quirk_add_irq_optional_dependent_sets(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct pnp_option *new_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned int num_sets, i, set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct pnp_irq *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	num_sets = dev->num_dependent_sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	for (i = 0; i < num_sets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		new_option = pnp_clone_dependent_set(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		if (!new_option)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		set = pnp_option_set(new_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		while (new_option && pnp_option_set(new_option) == set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			if (new_option->type == IORESOURCE_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				irq = &new_option->u.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				irq->flags |= IORESOURCE_IRQ_OPTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			dbg_pnp_show_option(dev, new_option);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			new_option = list_entry(new_option->list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 						struct pnp_option, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		dev_info(&dev->dev, "added dependent option set %d (same as "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			 "set %d except IRQ optional)\n", set, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void quirk_ad1815_mpu_resources(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct pnp_option *option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct pnp_irq *irq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	unsigned int independent_irqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	list_for_each_entry(option, &dev->options, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		if (option->type == IORESOURCE_IRQ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		    !pnp_option_is_dependent(option)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			independent_irqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			irq = &option->u.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (independent_irqs != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	irq->flags |= IORESOURCE_IRQ_OPTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	dev_info(&dev->dev, "made independent IRQ optional\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void quirk_system_pci_resources(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct pci_dev *pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	resource_size_t pnp_start, pnp_end, pci_start, pci_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * Some BIOSes have PNP motherboard devices with resources that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * partially overlap PCI BARs.  The PNP system driver claims these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * motherboard resources, which prevents the normal PCI driver from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * requesting them later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * This patch disables the PNP resources that conflict with PCI BARs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * so they won't be claimed by the PNP system driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	for_each_pci_dev(pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			unsigned long flags, type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			flags = pci_resource_flags(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			type = flags & (IORESOURCE_IO | IORESOURCE_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			if (!type || pci_resource_len(pdev, i) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			if (flags & IORESOURCE_UNSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			pci_start = pci_resource_start(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			pci_end = pci_resource_end(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			for (j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			     (res = pnp_get_resource(dev, type, j)); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				if (res->start == 0 && res->end == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 					continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				pnp_start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				pnp_end = res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				 * If the PNP region doesn't overlap the PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 				 * region at all, there's no problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 				 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				if (pnp_end < pci_start || pnp_start > pci_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 					continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 				/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				 * If the PNP region completely encloses (or is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				 * at least as large as) the PCI region, that's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				 * also OK.  For example, this happens when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				 * PNP device describes a bridge with PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				 * behind it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 				if (pnp_start <= pci_start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				    pnp_end >= pci_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 					continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 				/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 				 * Otherwise, the PNP region overlaps *part* of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				 * the PCI region, and that might prevent a PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				 * driver from requesting its resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 				 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				dev_warn(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 					 "disabling %pR because it overlaps "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 					 "%s BAR %d %pR\n", res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 					 pci_name(pdev), i, &pdev->resource[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				res->flags |= IORESOURCE_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #ifdef CONFIG_AMD_NB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #include <asm/amd_nb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void quirk_amd_mmconfig_area(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	resource_size_t start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct pnp_resource *pnp_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct resource mmconfig_res, *mmconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	mmconfig = amd_get_mmconfig_range(&mmconfig_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (!mmconfig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	list_for_each_entry(pnp_res, &dev->resources, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		res = &pnp_res->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		if (res->end < mmconfig->start || res->start > mmconfig->end ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		    (res->start == mmconfig->start && res->end == mmconfig->end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		dev_info(&dev->dev, FW_BUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			 "%pR covers only part of AMD MMCONFIG area %pR; adding more reservations\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			 res, mmconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		if (mmconfig->start < res->start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			start = mmconfig->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			end = res->start - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			pnp_add_mem_resource(dev, start, end, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		if (mmconfig->end > res->end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			start = res->end + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			end = mmconfig->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			pnp_add_mem_resource(dev, start, end, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Device IDs of parts that have 32KB MCH space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const unsigned int mch_quirk_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	0x0154,	/* Ivy Bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	0x0a04, /* Haswell-ULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	0x0c00,	/* Haswell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	0x1604, /* Broadwell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct pci_dev *get_intel_host(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct pci_dev *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 				      NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		if (host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			return host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void quirk_intel_mch(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct pci_dev *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	u32 addr_lo, addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	struct pci_bus_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct resource mch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	struct pnp_resource *pnp_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	host = get_intel_host();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	 * MCHBAR is not an architected PCI BAR, so MCH space is usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	 * reported as a PNP0C02 resource.  The MCH space was originally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	 * 16KB, but is 32KB in newer parts.  Some BIOSes still report a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	 * PNP0C02 resource that is only 16KB, which means the rest of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	 * MCH space is consumed but unreported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	 * Read MCHBAR for Host Member Mapped Register Range Base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	 * https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	 * Sec 3.1.12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	pci_read_config_dword(host, 0x48, &addr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	region.start = addr_lo & ~0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	pci_read_config_dword(host, 0x4c, &addr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	region.start |= (u64) addr_hi << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	region.end = region.start + 32*1024 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	memset(&mch, 0, sizeof(mch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	mch.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	pcibios_bus_to_resource(host->bus, &mch, &region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	list_for_each_entry(pnp_res, &dev->resources, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		res = &pnp_res->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		if (res->end < mch.start || res->start > mch.end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			continue;	/* no overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		if (res->start == mch.start && res->end == mch.end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 			continue;	/* exact match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			 res, pci_name(host), &mch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		res->start = mch.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		res->end = mch.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	pci_dev_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)  *  PnP Quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)  *  Cards or devices that need some tweaking due to incomplete resource info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static struct pnp_fixup pnp_fixups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	/* Soundblaster awe io port quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	{"CTL0021", quirk_awe32_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	{"CTL0022", quirk_awe32_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	{"CTL0023", quirk_awe32_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	/* CMI 8330 interrupt and dma fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	{"@X@0001", quirk_cmi8330_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	/* Soundblaster audio device io port range quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	{"CTL0001", quirk_sb16audio_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	{"CTL0031", quirk_sb16audio_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	{"CTL0041", quirk_sb16audio_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	{"CTL0042", quirk_sb16audio_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	{"CTL0043", quirk_sb16audio_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	{"CTL0044", quirk_sb16audio_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	{"CTL0045", quirk_sb16audio_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	/* Add IRQ-optional MPU options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	{"ADS7151", quirk_ad1815_mpu_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	{"ADS7181", quirk_add_irq_optional_dependent_sets},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{"AZT0002", quirk_add_irq_optional_dependent_sets},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	/* PnP resources that might overlap PCI BARs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	{"PNP0c01", quirk_system_pci_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	{"PNP0c02", quirk_system_pci_resources},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #ifdef CONFIG_AMD_NB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	{"PNP0c01", quirk_amd_mmconfig_area},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	{"PNP0c02", quirk_intel_mch},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	{""}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) void pnp_fixup_device(struct pnp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	struct pnp_fixup *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	for (f = pnp_fixups; *f->id; f++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		if (!compare_pnp_id(dev->id, f->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		pnp_dbg(&dev->dev, "%s: calling %pS\n", f->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 			f->quirk_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		f->quirk_function(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }