^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * dcdbas.h: Definitions for Dell Systems Management Base driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995-2005 Dell Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DCDBAS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DCDBAS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MAX_SMI_DATA_BUF_SIZE (256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HC_ACTION_NONE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HC_ACTION_HOST_CONTROL_POWEROFF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HC_ACTION_HOST_CONTROL_POWERCYCLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HC_SMITYPE_NONE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HC_SMITYPE_TYPE1 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HC_SMITYPE_TYPE2 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HC_SMITYPE_TYPE3 (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ESM_APM_CMD (0x0A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ESM_APM_POWER_CYCLE (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ESM_STATUS_CMD_UNSUCCESSFUL (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CMOS_BASE_PORT (0x070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CMOS_PAGE1_INDEX_PORT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMOS_PAGE1_DATA_PORT (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMOS_PAGE2_INDEX_PORT_PIIX4 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMOS_PAGE2_DATA_PORT_PIIX4 (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PE1400_APM_CONTROL_PORT (0x0B0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCAT_APM_CONTROL_PORT (0x0B2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCAT_APM_STATUS_PORT (0x0B3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PE1300_CMOS_CMD_STRUCT_PTR (0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PE1400_CMOS_CMD_STRUCT_PTR (0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX_SYSMGMT_LONGCMD_SGENTRY_NUM (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TIMEOUT_USEC_SHORT_SEMA_BLOCKING (10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EXPIRED_TIMER (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SMI_CMD_MAGIC (0x534D4931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SMM_EPS_SIG "$SCB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DCDBAS_DEV_ATTR_RW(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEVICE_ATTR(_name,0600,_name##_show,_name##_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DCDBAS_DEV_ATTR_RO(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEVICE_ATTR(_name,0400,_name##_show,NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DCDBAS_DEV_ATTR_WO(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEVICE_ATTR(_name,0200,NULL,_name##_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DCDBAS_BIN_ATTR_RW(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct bin_attribute bin_attr_##_name = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .attr = { .name = __stringify(_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .mode = 0600 }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .read = _name##_read, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .write = _name##_write, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct smi_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __u32 ebx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __u32 ecx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __u16 command_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __u8 command_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __u8 command_buffer[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct apm_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __u8 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __s8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u8 parm[MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) } __attribute__ ((packed)) shortreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __u16 num_sg_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } __attribute__ ((packed))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) sglist[MAX_SYSMGMT_LONGCMD_SGENTRY_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } __attribute__ ((packed)) longreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } __attribute__ ((packed)) parameters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int dcdbas_smi_request(struct smi_cmd *smi_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct smm_eps_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) char smm_comm_buff_anchor[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u64 smm_comm_buff_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u64 num_of_4k_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif /* _DCDBAS_H_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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