Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Mellanox register access driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Mellanox Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2018 Vadim Pasternak <vadimp@mellanox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_data/mlxreg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* Attribute parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MLXREG_IO_ATT_SIZE	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MLXREG_IO_ATT_NUM	48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * struct mlxreg_io_priv_data - driver's private data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * @pdev: platform device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * @pdata: platform data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * @hwmon: hwmon device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * @mlxreg_io_attr: sysfs attributes array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * @mlxreg_io_dev_attr: sysfs sensor device attribute array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * @group: sysfs attribute group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * @groups: list of sysfs attribute group for hwmon registration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @regsize: size of a register value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct mlxreg_io_priv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct mlxreg_core_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct device *hwmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct attribute *mlxreg_io_attr[MLXREG_IO_ATT_NUM + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct sensor_device_attribute mlxreg_io_dev_attr[MLXREG_IO_ATT_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct attribute_group group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	const struct attribute_group *groups[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int regsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) mlxreg_io_get_reg(void *regmap, struct mlxreg_core_data *data, u32 in_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		  bool rw_flag, int regsize, u32 *regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int i, val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	ret = regmap_read(regmap, data->reg, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		goto access_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 * There are four kinds of attributes: single bit, full register's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * bits, bit sequence, bits in few registers For the first kind field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 * mask indicates which bits are not related and field bit is set zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * For the second kind field mask is set to zero and field bit is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 * with all bits one. No special handling for such kind of attributes -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * pass value as is. For the third kind, the field mask indicates which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * bits are related and the field bit is set to the first bit number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * (from 1 to 32) is the bit sequence. For the fourth kind - the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * of registers which should be read for getting an attribute are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * specified through 'data->regnum' field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (!data->bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		/* Single bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		if (rw_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			/* For show: expose effective bit value as 0 or 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			*regval = !!(*regval & ~data->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			/* For store: set effective bit value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			*regval &= data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			if (in_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 				*regval |= ~data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	} else if (data->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		/* Bit sequence. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		if (rw_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			/* For show: mask and shift right. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			*regval = ror32(*regval & data->mask, (data->bit - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			/* For store: shift to the position and mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			in_val = rol32(in_val, data->bit - 1) & data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			/* Clear relevant bits and set them to new value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			*regval = (*regval & ~data->mask) | in_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		 * Some attributes could occupied few registers in case regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		 * bit size is 8 or 16. Compose such attributes from 'regnum'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		 * registers. Such attributes contain read-only data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		for (i = 1; i < data->regnum; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			ret = regmap_read(regmap, data->reg + i, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				goto access_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			*regval |= rol32(val, regsize * i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) access_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mlxreg_io_attr_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		    char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct mlxreg_io_priv_data *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int index = to_sensor_dev_attr(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct mlxreg_core_data *data = priv->pdata->data + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ret = mlxreg_io_get_reg(priv->pdata->regmap, data, 0, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				priv->regsize, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		goto access_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return sprintf(buf, "%u\n", regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) access_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mlxreg_io_attr_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		     const char *buf, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct mlxreg_io_priv_data *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int index = to_sensor_dev_attr(attr)->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct mlxreg_core_data *data = priv->pdata->data + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32 input_val, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (len > MLXREG_IO_ATT_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* Convert buffer to input value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ret = kstrtou32(buf, 0, &input_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	ret = mlxreg_io_get_reg(priv->pdata->regmap, data, input_val, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				priv->regsize, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		goto access_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ret = regmap_write(priv->pdata->regmap, data->reg, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		goto access_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) access_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	dev_err(&priv->pdev->dev, "Bus access error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct device_attribute mlxreg_io_devattr_rw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.show	= mlxreg_io_attr_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.store	= mlxreg_io_attr_store,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int mlxreg_io_attr_init(struct mlxreg_io_priv_data *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	priv->group.attrs = devm_kcalloc(&priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 					 priv->pdata->counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 					 sizeof(struct attribute *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 					 GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (!priv->group.attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	for (i = 0; i < priv->pdata->counter; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		priv->mlxreg_io_attr[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				&priv->mlxreg_io_dev_attr[i].dev_attr.attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		memcpy(&priv->mlxreg_io_dev_attr[i].dev_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		       &mlxreg_io_devattr_rw, sizeof(struct device_attribute));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		/* Set attribute name as a label. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		priv->mlxreg_io_attr[i]->name =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				devm_kasprintf(&priv->pdev->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 					       priv->pdata->data[i].label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		if (!priv->mlxreg_io_attr[i]->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			dev_err(&priv->pdev->dev, "Memory allocation failed for sysfs attribute %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		priv->mlxreg_io_dev_attr[i].dev_attr.attr.mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 						priv->pdata->data[i].mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		priv->mlxreg_io_dev_attr[i].dev_attr.attr.name =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 					priv->mlxreg_io_attr[i]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		priv->mlxreg_io_dev_attr[i].index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		sysfs_attr_init(&priv->mlxreg_io_dev_attr[i].dev_attr.attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	priv->group.attrs = priv->mlxreg_io_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	priv->groups[0] = &priv->group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	priv->groups[1] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int mlxreg_io_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct mlxreg_io_priv_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	priv->pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (!priv->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		dev_err(&pdev->dev, "Failed to get platform data.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	priv->regsize = regmap_get_val_bytes(priv->pdata->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (priv->regsize < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return priv->regsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	err = mlxreg_io_attr_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		dev_err(&priv->pdev->dev, "Failed to allocate attributes: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	priv->hwmon = devm_hwmon_device_register_with_groups(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 							     "mlxreg_io",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 							      priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 							      priv->groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (IS_ERR(priv->hwmon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		dev_err(&pdev->dev, "Failed to register hwmon device %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			PTR_ERR(priv->hwmon));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return PTR_ERR(priv->hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	dev_set_drvdata(&pdev->dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct platform_driver mlxreg_io_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	    .name = "mlxreg-io",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.probe = mlxreg_io_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) module_platform_driver(mlxreg_io_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MODULE_DESCRIPTION("Mellanox regmap I/O access driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MODULE_ALIAS("platform:mlxreg-io");