Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2019, Mellanox Technologies. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __MLXBF_TMFIFO_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __MLXBF_TMFIFO_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MLXBF_TMFIFO_TX_DATA				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MLXBF_TMFIFO_TX_STS				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MLXBF_TMFIFO_TX_STS__LENGTH			0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MLXBF_TMFIFO_TX_STS__COUNT_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MLXBF_TMFIFO_TX_STS__COUNT_WIDTH		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MLXBF_TMFIFO_TX_STS__COUNT_RESET_VAL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK		GENMASK_ULL(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MLXBF_TMFIFO_TX_STS__COUNT_MASK			GENMASK_ULL(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MLXBF_TMFIFO_TX_CTL				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MLXBF_TMFIFO_TX_CTL__LENGTH			0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MLXBF_TMFIFO_TX_CTL__LWM_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MLXBF_TMFIFO_TX_CTL__LWM_WIDTH			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MLXBF_TMFIFO_TX_CTL__LWM_RESET_VAL		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK			GENMASK_ULL(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MLXBF_TMFIFO_TX_CTL__LWM_MASK			GENMASK_ULL(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MLXBF_TMFIFO_TX_CTL__HWM_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MLXBF_TMFIFO_TX_CTL__HWM_WIDTH			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MLXBF_TMFIFO_TX_CTL__HWM_RESET_VAL		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK			GENMASK_ULL(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MLXBF_TMFIFO_TX_CTL__HWM_MASK			GENMASK_ULL(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_SHIFT		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_WIDTH		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RESET_VAL	256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_RMASK		GENMASK_ULL(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MLXBF_TMFIFO_TX_CTL__MAX_ENTRIES_MASK		GENMASK_ULL(40, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MLXBF_TMFIFO_RX_DATA				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MLXBF_TMFIFO_RX_STS				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MLXBF_TMFIFO_RX_STS__LENGTH			0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MLXBF_TMFIFO_RX_STS__COUNT_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MLXBF_TMFIFO_RX_STS__COUNT_WIDTH		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MLXBF_TMFIFO_RX_STS__COUNT_RESET_VAL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK		GENMASK_ULL(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MLXBF_TMFIFO_RX_STS__COUNT_MASK			GENMASK_ULL(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MLXBF_TMFIFO_RX_CTL				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MLXBF_TMFIFO_RX_CTL__LENGTH			0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MLXBF_TMFIFO_RX_CTL__LWM_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MLXBF_TMFIFO_RX_CTL__LWM_WIDTH			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MLXBF_TMFIFO_RX_CTL__LWM_RESET_VAL		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MLXBF_TMFIFO_RX_CTL__LWM_RMASK			GENMASK_ULL(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MLXBF_TMFIFO_RX_CTL__LWM_MASK			GENMASK_ULL(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MLXBF_TMFIFO_RX_CTL__HWM_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MLXBF_TMFIFO_RX_CTL__HWM_WIDTH			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MLXBF_TMFIFO_RX_CTL__HWM_RESET_VAL		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MLXBF_TMFIFO_RX_CTL__HWM_RMASK			GENMASK_ULL(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MLXBF_TMFIFO_RX_CTL__HWM_MASK			GENMASK_ULL(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_SHIFT		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_WIDTH		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RESET_VAL	256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_RMASK		GENMASK_ULL(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MLXBF_TMFIFO_RX_CTL__MAX_ENTRIES_MASK		GENMASK_ULL(40, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif /* !defined(__MLXBF_TMFIFO_REGS_H__) */