^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019, Mellanox Technologies. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __MLXBF_BOOTCTL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __MLXBF_BOOTCTL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Request that the on-chip watchdog be enabled, or disabled, after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the next chip soft reset. This call does not affect the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * status of the on-chip watchdog. If non-zero, the argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * specifies the watchdog interval in seconds. If zero, the watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * will not be enabled after the next soft reset. Non-zero errors are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * returned as documented below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MLXBF_BOOTCTL_SET_POST_RESET_WDOG 0x82000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Query the status which has been requested for the on-chip watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * after the next chip soft reset. Returns the interval as set by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * MLXBF_BOOTCTL_SET_POST_RESET_WDOG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MLXBF_BOOTCTL_GET_POST_RESET_WDOG 0x82000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Request that a specific boot action be taken at the next soft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * reset. By default, the boot action is set by external chip pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * which are sampled on hard reset. Note that the boot action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * requested by this call will persist on subsequent resets unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * this service, or the MLNX_SET_SECOND_RESET_ACTION service, is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * invoked. See below for the available MLNX_BOOT_xxx parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * values. Non-zero errors are returned as documented below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MLXBF_BOOTCTL_SET_RESET_ACTION 0x82000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Return the specific boot action which will be taken at the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * soft reset. Returns the reset action (see below for the parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * values for MLXBF_BOOTCTL_SET_RESET_ACTION).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MLXBF_BOOTCTL_GET_RESET_ACTION 0x82000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Request that a specific boot action be taken at the soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * after the next soft reset. For a specified valid boot mode, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * effect of this call is identical to that of invoking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * MLXBF_BOOTCTL_SET_RESET_ACTION after the next chip soft reset; in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * particular, after that reset, the action for the now next reset can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * be queried with MLXBF_BOOTCTL_GET_RESET_ACTION and modified with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * MLXBF_BOOTCTL_SET_RESET_ACTION. You may also specify the parameter as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * MLNX_BOOT_NONE, which is equivalent to specifying that no call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * MLXBF_BOOTCTL_SET_RESET_ACTION be taken after the next chip soft reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * This call does not affect the action to be taken at the next soft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * reset. Non-zero errors are returned as documented below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MLXBF_BOOTCTL_SET_SECOND_RESET_ACTION 0x82000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Return the specific boot action which will be taken at the soft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * reset after the next soft reset; this will be one of the valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * actions for MLXBF_BOOTCTL_SET_SECOND_RESET_ACTION.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MLXBF_BOOTCTL_GET_SECOND_RESET_ACTION 0x82000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Return the fuse status of the current chip. The caller should specify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * with the second argument if the state of the lifecycle fuses or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * version of secure boot fuse keys left should be returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MLXBF_BOOTCTL_GET_TBB_FUSE_STATUS 0x82000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Reset eMMC by programming the RST_N register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MLXBF_BOOTCTL_SET_EMMC_RST_N 0x82000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MLXBF_BOOTCTL_GET_DIMM_INFO 0x82000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* SMC function IDs for SiP Service queries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MLXBF_BOOTCTL_SIP_SVC_CALL_COUNT 0x8200ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MLXBF_BOOTCTL_SIP_SVC_UID 0x8200ff01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MLXBF_BOOTCTL_SIP_SVC_VERSION 0x8200ff03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* ARM Standard Service Calls version numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MLXBF_BOOTCTL_SVC_VERSION_MAJOR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MLXBF_BOOTCTL_SVC_VERSION_MINOR 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Number of svc calls defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MLXBF_BOOTCTL_NUM_SVC_CALLS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Valid reset actions for MLXBF_BOOTCTL_SET_RESET_ACTION. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MLXBF_BOOTCTL_EXTERNAL 0 /* Not boot from eMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MLXBF_BOOTCTL_EMMC 1 /* From primary eMMC boot partition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MLNX_BOOTCTL_SWAP_EMMC 2 /* Swap eMMC boot partitions and reboot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MLXBF_BOOTCTL_EMMC_LEGACY 3 /* From primary eMMC in legacy mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Valid arguments for requesting the fuse status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MLXBF_BOOTCTL_FUSE_STATUS_LIFECYCLE 0 /* Return lifecycle status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MLXBF_BOOTCTL_FUSE_STATUS_KEYS 1 /* Return secure boot key status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Additional value to disable the MLXBF_BOOTCTL_SET_SECOND_RESET_ACTION. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MLXBF_BOOTCTL_NONE 0x7fffffff /* Don't change next boot action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif /* __MLXBF_BOOTCTL_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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