^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Sanechips Technology Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pinctrl-zx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TOP_REG0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TOP_REG1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TOP_REG2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TOP_REG3 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TOP_REG4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TOP_REG5 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TOP_REG6 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TOP_REG7 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TOP_REG8 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The pin numbering starts from AON pins with reserved ones included,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * so that register data like offset and bit position for AON pins can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * be calculated from pin number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum zx296718_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* aon_pmm_reg_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) I2C3_SCL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) I2C3_SDA = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) AON_RESERVED0 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) AON_RESERVED1 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SEC_EN = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) UART0_RXD = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) UART0_TXD = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) IR_IN = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SPI0_CLK = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SPI0_CS = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SPI0_TXD = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SPI0_RXD = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) KEY_COL0 = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) KEY_COL1 = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) KEY_COL2 = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) KEY_ROW0 = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* aon_pmm_reg_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) KEY_ROW1 = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) KEY_ROW2 = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) HDMI_SCL = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) HDMI_SDA = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) JTAG_TCK = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) JTAG_TRSTN = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) JTAG_TMS = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) JTAG_TDI = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) JTAG_TDO = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) I2C0_SCL = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) I2C0_SDA = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) I2C1_SCL = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) I2C1_SDA = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) AON_RESERVED2 = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) AON_RESERVED3 = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) AON_RESERVED4 = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* aon_pmm_reg_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SPI1_CLK = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SPI1_CS = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SPI1_TXD = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SPI1_RXD = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) AON_RESERVED5 = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) AON_RESERVED6 = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) AUDIO_DET = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SPDIF_OUT = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) HDMI_CEC = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) HDMI_HPD = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) GMAC_25M_OUT = 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) BOOT_SEL0 = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) BOOT_SEL1 = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BOOT_SEL2 = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DEEP_SLEEP_OUT_N = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) AON_RESERVED7 = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* top_pmm_reg_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GMII_GTX_CLK = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GMII_TX_CLK = 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GMII_TXD0 = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GMII_TXD1 = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GMII_TXD2 = 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) GMII_TXD3 = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) GMII_TXD4 = 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) GMII_TXD5 = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) GMII_TXD6 = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) GMII_TXD7 = 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) GMII_TX_ER = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) GMII_TX_EN = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) GMII_RX_CLK = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) GMII_RXD0 = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) GMII_RXD1 = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) GMII_RXD2 = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* top_pmm_reg_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) GMII_RXD3 = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GMII_RXD4 = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) GMII_RXD5 = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) GMII_RXD6 = 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) GMII_RXD7 = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) GMII_RX_ER = 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) GMII_RX_DV = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GMII_COL = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GMII_CRS = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GMII_MDC = 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) GMII_MDIO = 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SDIO1_CLK = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SDIO1_CMD = 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SDIO1_DATA0 = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SDIO1_DATA1 = 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SDIO1_DATA2 = 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* top_pmm_reg_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SDIO1_DATA3 = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SDIO1_CD = 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SDIO1_WP = 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) USIM1_CD = 83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) USIM1_CLK = 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) USIM1_RST = 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* top_pmm_reg_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) USIM1_DATA = 86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SDIO0_CLK = 87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SDIO0_CMD = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SDIO0_DATA0 = 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SDIO0_DATA1 = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SDIO0_DATA2 = 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SDIO0_DATA3 = 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SDIO0_CD = 93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SDIO0_WP = 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* top_pmm_reg_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) TSI0_DATA0 = 95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SPINOR_CLK = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) TSI2_DATA = 97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) TSI2_CLK = 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) TSI2_SYNC = 99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) TSI2_VALID = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) SPINOR_CS = 101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SPINOR_DQ0 = 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SPINOR_DQ1 = 103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SPINOR_DQ2 = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SPINOR_DQ3 = 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) VGA_HS = 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) VGA_VS = 107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) TSI3_DATA = 108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* top_pmm_reg_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TSI3_CLK = 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) TSI3_SYNC = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) TSI3_VALID = 111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) I2S1_WS = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) I2S1_BCLK = 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) I2S1_MCLK = 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) I2S1_DIN0 = 115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) I2S1_DOUT0 = 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SPI3_CLK = 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SPI3_CS = 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SPI3_TXD = 119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) NAND_LDO_MS18_SEL = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* top_pmm_reg_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SPI3_RXD = 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) I2S0_MCLK = 122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) I2S0_BCLK = 123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) I2S0_WS = 124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) I2S0_DIN0 = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) I2S0_DOUT0 = 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) I2C5_SCL = 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) I2C5_SDA = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SPI2_CLK = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SPI2_CS = 130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SPI2_TXD = 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* top_pmm_reg_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SPI2_RXD = 132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) NAND_WP_N = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) NAND_PAGE_SIZE0 = 134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) NAND_PAGE_SIZE1 = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) NAND_ADDR_CYCLE = 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) NAND_RB0 = 137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) NAND_RB1 = 138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) NAND_RB2 = 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) NAND_RB3 = 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* top_pmm_reg_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) GMAC_125M_IN = 141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) GMAC_50M_OUT = 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SPINOR_SSCLK_LOOPBACK = 143,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SPINOR_SDIO1CLK_LOOPBACK = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct pinctrl_pin_desc zx296718_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* aon_pmm_reg_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) AON_MUX(0x0, "ANMI"), /* anmi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) AON_MUX(0x1, "AGPIO"), /* agpio29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) AON_MUX(0x2, "nonAON"), /* pin0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) AON_MUX(0x3, "EXT_INT"), /* int4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) TOP_MUX(0x0, "I2C3"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) TOP_MUX(0x1, "SPI2"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TOP_MUX(0x2, "I2S1")), /* din0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) AON_MUX(0x0, "WD"), /* rst_b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) AON_MUX(0x1, "AGPIO"), /* agpio30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) AON_MUX(0x2, "nonAON"), /* pin1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) AON_MUX(0x3, "EXT_INT"), /* int5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) TOP_MUX(0x0, "I2C3"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) TOP_MUX(0x1, "SPI2"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) TOP_MUX(0x2, "I2S0")), /* mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ZX_RESERVED(AON_RESERVED0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ZX_RESERVED(AON_RESERVED1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) AON_MUX(0x0, "SEC"), /* en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) AON_MUX(0x1, "AGPIO"), /* agpio28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) AON_MUX(0x2, "nonAON"), /* pin3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) AON_MUX(0x3, "EXT_INT"), /* int7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) TOP_MUX(0x0, "I2C2"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) TOP_MUX(0x1, "SPI2")), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) AON_MUX(0x0, "UART0"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) AON_MUX(0x1, "AGPIO"), /* agpio20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) AON_MUX(0x2, "nonAON")), /* pin34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) AON_MUX(0x0, "UART0"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) AON_MUX(0x1, "AGPIO"), /* agpio21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) AON_MUX(0x2, "nonAON")), /* pin32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) AON_PIN(IR_IN, 0, 0, 0, 0x64, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) AON_MUX(0x0, "IR"), /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) AON_MUX(0x1, "AGPIO"), /* agpio0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) AON_MUX(0x2, "nonAON")), /* pin27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) AON_MUX(0x0, "EXT_INT"), /* int0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) AON_MUX(0x1, "AGPIO"), /* agpio23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) AON_MUX(0x2, "nonAON"), /* pin5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) AON_MUX(0x3, "PCU"), /* test6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) TOP_MUX(0x0, "SPI0"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) TOP_MUX(0x1, "ISP")), /* flash_trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) AON_MUX(0x0, "EXT_INT"), /* int1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) AON_MUX(0x1, "AGPIO"), /* agpio24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) AON_MUX(0x2, "nonAON"), /* pin6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) AON_MUX(0x3, "PCU"), /* test0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) TOP_MUX(0x0, "SPI0"), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) TOP_MUX(0x1, "ISP")), /* prelight_trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) AON_MUX(0x0, "EXT_INT"), /* int2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) AON_MUX(0x1, "AGPIO"), /* agpio25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) AON_MUX(0x2, "nonAON"), /* pin7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) AON_MUX(0x3, "PCU"), /* test1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) TOP_MUX(0x0, "SPI0"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) TOP_MUX(0x1, "ISP")), /* shutter_trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) AON_MUX(0x0, "EXT_INT"), /* int3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) AON_MUX(0x1, "AGPIO"), /* agpio26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) AON_MUX(0x2, "nonAON"), /* pin8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) AON_MUX(0x3, "PCU"), /* test2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) TOP_MUX(0x0, "SPI0"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) TOP_MUX(0x1, "ISP")), /* shutter_open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) AON_MUX(0x0, "KEY"), /* col0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) AON_MUX(0x1, "AGPIO"), /* agpio5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) AON_MUX(0x2, "nonAON"), /* pin9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) AON_MUX(0x3, "PCU"), /* test3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) TOP_MUX(0x0, "UART3"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) TOP_MUX(0x1, "I2S0")), /* din1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) AON_MUX(0x0, "KEY"), /* col1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) AON_MUX(0x1, "AGPIO"), /* agpio6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) AON_MUX(0x2, "nonAON"), /* pin10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) TOP_MUX(0x0, "UART3"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) TOP_MUX(0x1, "I2S0"), /* din2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) TOP_MUX(0x2, "VGA")), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) AON_MUX(0x0, "KEY"), /* col2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) AON_MUX(0x1, "AGPIO"), /* agpio7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) AON_MUX(0x2, "nonAON"), /* pin11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) TOP_MUX(0x0, "PWM"), /* out1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) TOP_MUX(0x1, "I2S0"), /* din3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) TOP_MUX(0x2, "VGA")), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) AON_MUX(0x0, "KEY"), /* row0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) AON_MUX(0x1, "AGPIO"), /* agpio8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) AON_MUX(0x2, "nonAON"), /* pin33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) AON_MUX(0x3, "WD")), /* rst_b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* aon_pmm_reg_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) AON_MUX(0x0, "KEY"), /* row1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) AON_MUX(0x1, "AGPIO"), /* agpio9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) AON_MUX(0x2, "nonAON"), /* pin12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) TOP_MUX(0x0, "LCD"), /* port0 lcd_te */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) TOP_MUX(0x1, "I2S0"), /* dout2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) TOP_MUX(0x2, "PWM"), /* out2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) TOP_MUX(0x3, "VGA")), /* hs1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) AON_MUX(0x0, "KEY"), /* row2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) AON_MUX(0x1, "AGPIO"), /* agpio10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) AON_MUX(0x2, "nonAON"), /* pin13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) TOP_MUX(0x0, "LCD"), /* port1 lcd_te */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) TOP_MUX(0x1, "I2S0"), /* dout3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) TOP_MUX(0x2, "PWM"), /* out3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) TOP_MUX(0x3, "VGA")), /* vs1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) AON_MUX(0x0, "PCU"), /* test7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) AON_MUX(0x1, "AGPIO"), /* agpio3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) AON_MUX(0x2, "nonAON"), /* pin14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) TOP_MUX(0x0, "HDMI"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) TOP_MUX(0x1, "UART3")), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) AON_MUX(0x0, "PCU"), /* test8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) AON_MUX(0x1, "AGPIO"), /* agpio4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) AON_MUX(0x2, "nonAON"), /* pin15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) TOP_MUX(0x0, "HDMI"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) TOP_MUX(0x1, "UART3")), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) AON_MUX(0x0, "JTAG"), /* tck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) AON_MUX(0x1, "AGPIO"), /* agpio11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) AON_MUX(0x2, "nonAON"), /* pin22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) AON_MUX(0x3, "EXT_INT"), /* int4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) TOP_MUX(0x0, "SPI4"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) TOP_MUX(0x1, "UART1")), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) AON_MUX(0x0, "JTAG"), /* trstn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) AON_MUX(0x1, "AGPIO"), /* agpio12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) AON_MUX(0x2, "nonAON"), /* pin23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) AON_MUX(0x3, "EXT_INT"), /* int5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) TOP_MUX(0x0, "SPI4"), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) TOP_MUX(0x1, "UART1")), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) AON_MUX(0x0, "JTAG"), /* tms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) AON_MUX(0x1, "AGPIO"), /* agpio13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) AON_MUX(0x2, "nonAON"), /* pin24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) AON_MUX(0x3, "EXT_INT"), /* int6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) TOP_MUX(0x0, "SPI4"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) TOP_MUX(0x1, "UART2")), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) AON_MUX(0x0, "JTAG"), /* tdi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) AON_MUX(0x1, "AGPIO"), /* agpio14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) AON_MUX(0x2, "nonAON"), /* pin25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) AON_MUX(0x3, "EXT_INT"), /* int7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) TOP_MUX(0x0, "SPI4"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) TOP_MUX(0x1, "UART2")), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) AON_MUX(0x0, "JTAG"), /* tdo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) AON_MUX(0x1, "AGPIO"), /* agpio15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) AON_MUX(0x2, "nonAON")), /* pin26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) AON_MUX(0x0, "I2C0"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) AON_MUX(0x1, "AGPIO"), /* agpio16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) AON_MUX(0x2, "nonAON")), /* pin28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) AON_MUX(0x0, "I2C0"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) AON_MUX(0x1, "AGPIO"), /* agpio17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) AON_MUX(0x2, "nonAON")), /* pin29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) AON_MUX(0x0, "I2C1"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) AON_MUX(0x1, "AGPIO"), /* agpio18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) AON_MUX(0x2, "nonAON"), /* pin30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) TOP_MUX(0x0, "LCD")), /* port0 lcd_te */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) AON_MUX(0x0, "I2C1"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) AON_MUX(0x1, "AGPIO"), /* agpio19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) AON_MUX(0x2, "nonAON"), /* pin31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) TOP_MUX(0x0, "LCD")), /* port1 lcd_te */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ZX_RESERVED(AON_RESERVED2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ZX_RESERVED(AON_RESERVED3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ZX_RESERVED(AON_RESERVED4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* aon_pmm_reg_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) AON_MUX(0x0, "EXT_INT"), /* int0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) AON_MUX(0x1, "PCU"), /* test12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) AON_MUX(0x2, "nonAON"), /* pin39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) TOP_MUX(0x0, "SPI1"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) TOP_MUX(0x1, "PCM"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) TOP_MUX(0x2, "BGPIO"), /* gpio35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) TOP_MUX(0x3, "I2C4"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) TOP_MUX(0x4, "I2S1"), /* mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) TOP_MUX(0x5, "ISP")), /* flash_trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) AON_MUX(0x0, "EXT_INT"), /* int1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) AON_MUX(0x1, "PCU"), /* test13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) AON_MUX(0x2, "nonAON"), /* pin40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) TOP_MUX(0x0, "SPI1"), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) TOP_MUX(0x1, "PCM"), /* fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) TOP_MUX(0x2, "BGPIO"), /* gpio36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) TOP_MUX(0x3, "I2C4"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) TOP_MUX(0x4, "I2S1"), /* bclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) TOP_MUX(0x5, "ISP")), /* prelight_trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) AON_MUX(0x0, "EXT_INT"), /* int2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) AON_MUX(0x1, "PCU"), /* test14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) AON_MUX(0x2, "nonAON"), /* pin41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) TOP_MUX(0x0, "SPI1"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) TOP_MUX(0x1, "PCM"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) TOP_MUX(0x2, "BGPIO"), /* gpio37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) TOP_MUX(0x3, "UART5"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) TOP_MUX(0x4, "I2S1"), /* ws */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) TOP_MUX(0x5, "ISP")), /* shutter_trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) AON_MUX(0x0, "EXT_INT"), /* int3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) AON_MUX(0x1, "PCU"), /* test15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) AON_MUX(0x2, "nonAON"), /* pin42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) TOP_MUX(0x0, "SPI1"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) TOP_MUX(0x1, "PCM"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) TOP_MUX(0x2, "BGPIO"), /* gpio38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) TOP_MUX(0x3, "UART5"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) TOP_MUX(0x4, "I2S1"), /* dout0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) TOP_MUX(0x5, "ISP")), /* shutter_open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ZX_RESERVED(AON_RESERVED5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ZX_RESERVED(AON_RESERVED6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) AON_MUX(0x0, "PCU"), /* test4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) AON_MUX(0x1, "AGPIO"), /* agpio27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) AON_MUX(0x2, "nonAON"), /* pin2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) AON_MUX(0x3, "EXT_INT"), /* int16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) TOP_MUX(0x0, "AUDIO"), /* detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) TOP_MUX(0x1, "I2C2"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) TOP_MUX(0x2, "SPI2")), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) AON_MUX(0x0, "PCU"), /* test5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) AON_MUX(0x1, "AGPIO"), /* agpio22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) AON_MUX(0x2, "nonAON"), /* pin4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) TOP_MUX(0x0, "SPDIF"), /* out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) TOP_MUX(0x1, "PWM"), /* out0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) TOP_MUX(0x2, "ISP")), /* fl_trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) AON_MUX(0x0, "PCU"), /* test9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) AON_MUX(0x1, "AGPIO"), /* agpio1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) AON_MUX(0x2, "nonAON")), /* pin16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) AON_MUX(0x0, "PCU"), /* test10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) AON_MUX(0x1, "AGPIO"), /* agpio2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) AON_MUX(0x2, "nonAON")), /* pin17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) AON_MUX(0x0, "PCU"), /* test11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) AON_MUX(0x1, "AGPIO"), /* agpio31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) AON_MUX(0x2, "nonAON")), /* pin43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) AON_MUX(0x0, "BOOT"), /* sel0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) AON_MUX(0x1, "AGPIO"), /* agpio18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) AON_MUX(0x2, "nonAON")), /* pin18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) AON_MUX(0x0, "BOOT"), /* sel1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) AON_MUX(0x1, "AGPIO"), /* agpio19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) AON_MUX(0x2, "nonAON")), /* pin19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) AON_MUX(0x0, "BOOT"), /* sel2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) AON_MUX(0x1, "AGPIO"), /* agpio20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) AON_MUX(0x2, "nonAON")), /* pin20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) AON_MUX(0x0, "DEEPSLP"), /* deep sleep out_n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) AON_MUX(0x1, "AGPIO"), /* agpio21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) AON_MUX(0x2, "nonAON")), /* pin21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ZX_RESERVED(AON_RESERVED7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* top_pmm_reg_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) TOP_MUX(0x0, "GMII"), /* gtx_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) TOP_MUX(0x1, "DVI0"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) TOP_MUX(0x2, "BGPIO")), /* gpio0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) TOP_MUX(0x0, "GMII"), /* tx_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) TOP_MUX(0x1, "DVI0"), /* vs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) TOP_MUX(0x2, "BGPIO")), /* gpio1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) TOP_MUX(0x0, "GMII"), /* txd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) TOP_MUX(0x1, "DVI0"), /* hs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) TOP_MUX(0x2, "BGPIO")), /* gpio2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) TOP_MUX(0x0, "GMII"), /* txd1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) TOP_MUX(0x1, "DVI0"), /* d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) TOP_MUX(0x2, "BGPIO")), /* gpio3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) TOP_MUX(0x0, "GMII"), /* txd2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) TOP_MUX(0x1, "DVI0"), /* d1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) TOP_MUX(0x2, "BGPIO")), /* gpio4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) TOP_MUX(0x0, "GMII"), /* txd3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) TOP_MUX(0x1, "DVI0"), /* d2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) TOP_MUX(0x2, "BGPIO")), /* gpio5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) TOP_MUX(0x0, "GMII"), /* txd4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) TOP_MUX(0x1, "DVI0"), /* d3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) TOP_MUX(0x2, "BGPIO")), /* gpio6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) TOP_MUX(0x0, "GMII"), /* txd5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) TOP_MUX(0x1, "DVI0"), /* d4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) TOP_MUX(0x2, "BGPIO")), /* gpio7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) TOP_MUX(0x0, "GMII"), /* txd6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) TOP_MUX(0x1, "DVI0"), /* d5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) TOP_MUX(0x2, "BGPIO")), /* gpio8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) TOP_MUX(0x0, "GMII"), /* txd7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) TOP_MUX(0x1, "DVI0"), /* d6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) TOP_MUX(0x2, "BGPIO")), /* gpio9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) TOP_MUX(0x0, "GMII"), /* tx_er */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) TOP_MUX(0x1, "DVI0"), /* d7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) TOP_MUX(0x2, "BGPIO")), /* gpio10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) TOP_MUX(0x0, "GMII"), /* tx_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) TOP_MUX(0x1, "DVI0"), /* d8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) TOP_MUX(0x3, "BGPIO")), /* gpio11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) TOP_MUX(0x0, "GMII"), /* rx_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) TOP_MUX(0x1, "DVI0"), /* d9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) TOP_MUX(0x3, "BGPIO")), /* gpio12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) TOP_MUX(0x0, "GMII"), /* rxd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) TOP_MUX(0x1, "DVI0"), /* d10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) TOP_MUX(0x3, "BGPIO")), /* gpio13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) TOP_MUX(0x0, "GMII"), /* rxd1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) TOP_MUX(0x1, "DVI0"), /* d11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) TOP_MUX(0x2, "BGPIO")), /* gpio14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) TOP_MUX(0x0, "GMII"), /* rxd2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) TOP_MUX(0x1, "DVI1"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) TOP_MUX(0x2, "BGPIO")), /* gpio15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* top_pmm_reg_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) TOP_MUX(0x0, "GMII"), /* rxd3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) TOP_MUX(0x1, "DVI1"), /* hs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) TOP_MUX(0x2, "BGPIO")), /* gpio16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) TOP_MUX(0x0, "GMII"), /* rxd4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) TOP_MUX(0x1, "DVI1"), /* vs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) TOP_MUX(0x2, "BGPIO")), /* gpio17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) TOP_MUX(0x0, "GMII"), /* rxd5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) TOP_MUX(0x1, "DVI1"), /* d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) TOP_MUX(0x2, "BGPIO"), /* gpio18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) TOP_MUX(0x3, "TSI0")), /* dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) TOP_MUX(0x0, "GMII"), /* rxd6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) TOP_MUX(0x1, "DVI1"), /* d1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) TOP_MUX(0x2, "BGPIO"), /* gpio19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) TOP_MUX(0x3, "TSI0")), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) TOP_MUX(0x0, "GMII"), /* rxd7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) TOP_MUX(0x1, "DVI1"), /* d2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) TOP_MUX(0x2, "BGPIO"), /* gpio20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) TOP_MUX(0x3, "TSI0")), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) TOP_MUX(0x0, "GMII"), /* rx_er */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) TOP_MUX(0x1, "DVI1"), /* d3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) TOP_MUX(0x2, "BGPIO"), /* gpio21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) TOP_MUX(0x3, "TSI0")), /* valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) TOP_MUX(0x0, "GMII"), /* rx_dv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) TOP_MUX(0x1, "DVI1"), /* d4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) TOP_MUX(0x2, "BGPIO"), /* gpio22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) TOP_MUX(0x3, "TSI1")), /* dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) TOP_MUX(0x0, "GMII"), /* col */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) TOP_MUX(0x1, "DVI1"), /* d5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) TOP_MUX(0x2, "BGPIO"), /* gpio23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) TOP_MUX(0x3, "TSI1")), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) TOP_MUX(0x0, "GMII"), /* crs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) TOP_MUX(0x1, "DVI1"), /* d6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) TOP_MUX(0x2, "BGPIO"), /* gpio24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) TOP_MUX(0x3, "TSI1")), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) TOP_MUX(0x0, "GMII"), /* mdc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) TOP_MUX(0x1, "DVI1"), /* d7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) TOP_MUX(0x2, "BGPIO"), /* gpio25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) TOP_MUX(0x3, "TSI1")), /* valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) TOP_MUX(0x0, "GMII"), /* mdio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) TOP_MUX(0x2, "BGPIO")), /* gpio26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) TOP_MUX(0x0, "SDIO1"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) TOP_MUX(0x1, "USIM0"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) TOP_MUX(0x2, "BGPIO"), /* gpio27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) TOP_MUX(0x3, "SPINOR")), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) TOP_MUX(0x0, "SDIO1"), /* cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) TOP_MUX(0x1, "USIM0"), /* cd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) TOP_MUX(0x2, "BGPIO"), /* gpio28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) TOP_MUX(0x3, "SPINOR")), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) TOP_MUX(0x0, "SDIO1"), /* dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) TOP_MUX(0x1, "USIM0"), /* rst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) TOP_MUX(0x2, "BGPIO"), /* gpio29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) TOP_MUX(0x3, "SPINOR")), /* dq0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) TOP_MUX(0x0, "SDIO1"), /* dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) TOP_MUX(0x1, "USIM0"), /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) TOP_MUX(0x2, "BGPIO"), /* gpio30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) TOP_MUX(0x3, "SPINOR")), /* dq1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) TOP_MUX(0x0, "SDIO1"), /* dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) TOP_MUX(0x1, "BGPIO"), /* gpio31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) TOP_MUX(0x2, "SPINOR")), /* dq2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* top_pmm_reg_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) TOP_MUX(0x0, "SDIO1"), /* dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) TOP_MUX(0x1, "BGPIO"), /* gpio32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) TOP_MUX(0x2, "SPINOR")), /* dq3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) TOP_MUX(0x0, "SDIO1"), /* cd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) TOP_MUX(0x1, "BGPIO"), /* gpio33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) TOP_MUX(0x2, "ISP")), /* fl_trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) TOP_MUX(0x0, "SDIO1"), /* wp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) TOP_MUX(0x1, "BGPIO"), /* gpio34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) TOP_MUX(0x2, "ISP")), /* ref_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) TOP_MUX(0x0, "USIM1"), /* cd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) TOP_MUX(0x1, "UART4"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) TOP_MUX(0x2, "BGPIO"), /* gpio39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) TOP_MUX(0x3, "SPI3"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) TOP_MUX(0x4, "I2S0"), /* bclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) TOP_MUX(0x5, "B_DVI0")), /* d8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) TOP_MUX(0x0, "USIM1"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) TOP_MUX(0x1, "UART4"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) TOP_MUX(0x2, "BGPIO"), /* gpio40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) TOP_MUX(0x3, "SPI3"), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) TOP_MUX(0x4, "I2S0"), /* ws */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) TOP_MUX(0x5, "B_DVI0")), /* d9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) TOP_MUX(0x0, "USIM1"), /* rst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) TOP_MUX(0x1, "UART4"), /* cts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) TOP_MUX(0x2, "BGPIO"), /* gpio41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) TOP_MUX(0x3, "SPI3"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) TOP_MUX(0x4, "I2S0"), /* dout0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) TOP_MUX(0x5, "B_DVI0")), /* d10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* top_pmm_reg_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) TOP_MUX(0x0, "USIM1"), /* dat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) TOP_MUX(0x1, "UART4"), /* rst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) TOP_MUX(0x2, "BGPIO"), /* gpio42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) TOP_MUX(0x3, "SPI3"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) TOP_MUX(0x4, "I2S0"), /* din0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) TOP_MUX(0x5, "B_DVI0")), /* d11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) TOP_MUX(0x0, "SDIO0"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) TOP_MUX(0x1, "GPIO")), /* gpio43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) TOP_MUX(0x0, "SDIO0"), /* cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) TOP_MUX(0x1, "GPIO")), /* gpio44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) TOP_MUX(0x0, "SDIO0"), /* dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) TOP_MUX(0x1, "GPIO")), /* gpio45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) TOP_MUX(0x0, "SDIO0"), /* dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) TOP_MUX(0x1, "GPIO")), /* gpio46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) TOP_MUX(0x0, "SDIO0"), /* dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) TOP_MUX(0x1, "GPIO")), /* gpio47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) TOP_MUX(0x0, "SDIO0"), /* dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) TOP_MUX(0x1, "GPIO")), /* gpio48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) TOP_MUX(0x0, "SDIO0"), /* cd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) TOP_MUX(0x1, "GPIO")), /* gpio49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) TOP_MUX(0x0, "SDIO0"), /* wp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) TOP_MUX(0x1, "GPIO")), /* gpio50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* top_pmm_reg_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) TOP_MUX(0x0, "TSI0"), /* dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) TOP_MUX(0x1, "LCD"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) TOP_MUX(0x2, "BGPIO")), /* gpio51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) TOP_MUX(0x0, "SPINOR"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) TOP_MUX(0x1, "TSI0"), /* dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) TOP_MUX(0x2, "LCD"), /* dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) TOP_MUX(0x3, "BGPIO")), /* gpio52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) TOP_MUX(0x0, "TSI2"), /* dat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) TOP_MUX(0x1, "TSI0"), /* dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) TOP_MUX(0x2, "LCD"), /* dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) TOP_MUX(0x3, "BGPIO")), /* gpio53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) TOP_MUX(0x0, "TSI2"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) TOP_MUX(0x1, "TSI0"), /* dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) TOP_MUX(0x2, "LCD"), /* dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) TOP_MUX(0x3, "BGPIO")), /* gpio54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) TOP_MUX(0x0, "TSI2"), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) TOP_MUX(0x1, "TSI0"), /* dat4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) TOP_MUX(0x2, "LCD"), /* dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) TOP_MUX(0x3, "BGPIO")), /* gpio55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) TOP_MUX(0x0, "TSI2"), /* valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) TOP_MUX(0x1, "TSI0"), /* dat5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) TOP_MUX(0x2, "LCD"), /* dat4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) TOP_MUX(0x3, "BGPIO")), /* gpio56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) TOP_MUX(0x0, "SPINOR"), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) TOP_MUX(0x1, "TSI0"), /* dat6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) TOP_MUX(0x2, "LCD"), /* dat5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) TOP_MUX(0x3, "BGPIO")), /* gpio57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) TOP_MUX(0x0, "SPINOR"), /* dq0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) TOP_MUX(0x1, "TSI0"), /* dat7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) TOP_MUX(0x2, "LCD"), /* dat6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) TOP_MUX(0x3, "BGPIO")), /* gpio58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) TOP_MUX(0x0, "SPINOR"), /* dq1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) TOP_MUX(0x1, "TSI0"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) TOP_MUX(0x2, "LCD"), /* dat7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) TOP_MUX(0x3, "BGPIO")), /* gpio59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) TOP_MUX(0x0, "SPINOR"), /* dq2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) TOP_MUX(0x1, "TSI0"), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) TOP_MUX(0x2, "LCD"), /* dat8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) TOP_MUX(0x3, "BGPIO")), /* gpio60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) TOP_MUX(0x0, "SPINOR"), /* dq3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) TOP_MUX(0x1, "TSI0"), /* valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) TOP_MUX(0x2, "LCD"), /* dat9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) TOP_MUX(0x3, "BGPIO")), /* gpio61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) TOP_MUX(0x0, "VGA"), /* hs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) TOP_MUX(0x1, "TSI1"), /* dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) TOP_MUX(0x2, "LCD"), /* dat10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) TOP_MUX(0x3, "BGPIO"), /* gpio62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) TOP_MUX(0x4, "I2S1"), /* din1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) TOP_MUX(0x5, "B_DVI0")), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) TOP_MUX(0x0, "VGA"), /* vs0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) TOP_MUX(0x1, "TSI1"), /* dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) TOP_MUX(0x2, "LCD"), /* dat11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) TOP_MUX(0x3, "BGPIO"), /* gpio63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) TOP_MUX(0x4, "I2S1"), /* din2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) TOP_MUX(0x5, "B_DVI0")), /* vs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) TOP_MUX(0x0, "TSI3"), /* dat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) TOP_MUX(0x1, "TSI1"), /* dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) TOP_MUX(0x2, "LCD"), /* dat12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) TOP_MUX(0x3, "BGPIO"), /* gpio64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) TOP_MUX(0x4, "I2S1"), /* din3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) TOP_MUX(0x5, "B_DVI0")), /* hs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* top_pmm_reg_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) TOP_MUX(0x0, "TSI3"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) TOP_MUX(0x1, "TSI1"), /* dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) TOP_MUX(0x2, "LCD"), /* dat13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) TOP_MUX(0x3, "BGPIO"), /* gpio65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) TOP_MUX(0x4, "I2S1"), /* dout1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) TOP_MUX(0x5, "B_DVI0")), /* d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) TOP_MUX(0x0, "TSI3"), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) TOP_MUX(0x1, "TSI1"), /* dat4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) TOP_MUX(0x2, "LCD"), /* dat14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) TOP_MUX(0x3, "BGPIO"), /* gpio66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) TOP_MUX(0x4, "I2S1"), /* dout2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) TOP_MUX(0x5, "B_DVI0")), /* d1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) TOP_MUX(0x0, "TSI3"), /* valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) TOP_MUX(0x1, "TSI1"), /* dat5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) TOP_MUX(0x2, "LCD"), /* dat15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) TOP_MUX(0x3, "BGPIO"), /* gpio67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) TOP_MUX(0x4, "I2S1"), /* dout3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) TOP_MUX(0x5, "B_DVI0")), /* d2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) TOP_MUX(0x0, "I2S1"), /* ws */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) TOP_MUX(0x1, "TSI1"), /* dat6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) TOP_MUX(0x2, "LCD"), /* dat16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) TOP_MUX(0x3, "BGPIO"), /* gpio68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) TOP_MUX(0x4, "VGA"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) TOP_MUX(0x5, "B_DVI0")), /* d3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) TOP_MUX(0x0, "I2S1"), /* bclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) TOP_MUX(0x1, "TSI1"), /* dat7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) TOP_MUX(0x2, "LCD"), /* dat17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) TOP_MUX(0x3, "BGPIO"), /* gpio69 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) TOP_MUX(0x4, "VGA"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) TOP_MUX(0x5, "B_DVI0")), /* d4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) TOP_MUX(0x0, "I2S1"), /* mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TOP_MUX(0x1, "TSI1"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) TOP_MUX(0x2, "LCD"), /* dat18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) TOP_MUX(0x3, "BGPIO")), /* gpio70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) TOP_MUX(0x0, "I2S1"), /* din0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) TOP_MUX(0x1, "TSI1"), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) TOP_MUX(0x2, "LCD"), /* dat19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) TOP_MUX(0x3, "BGPIO")), /* gpio71 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) TOP_MUX(0x0, "I2S1"), /* dout0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) TOP_MUX(0x1, "TSI1"), /* valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) TOP_MUX(0x2, "LCD"), /* dat20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TOP_MUX(0x3, "BGPIO")), /* gpio72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) TOP_MUX(0x0, "SPI3"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) TOP_MUX(0x1, "TSO1"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) TOP_MUX(0x2, "LCD"), /* dat21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) TOP_MUX(0x3, "BGPIO"), /* gpio73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) TOP_MUX(0x4, "UART5"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) TOP_MUX(0x5, "PCM"), /* fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) TOP_MUX(0x6, "I2S0"), /* din1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) TOP_MUX(0x7, "B_DVI0")), /* d5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) TOP_MUX(0x0, "SPI3"), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) TOP_MUX(0x1, "TSO1"), /* dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) TOP_MUX(0x2, "LCD"), /* dat22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) TOP_MUX(0x3, "BGPIO"), /* gpio74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) TOP_MUX(0x4, "UART5"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) TOP_MUX(0x5, "PCM"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) TOP_MUX(0x6, "I2S0"), /* din2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) TOP_MUX(0x7, "B_DVI0")), /* d6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) TOP_MUX(0x0, "SPI3"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) TOP_MUX(0x1, "TSO1"), /* dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) TOP_MUX(0x2, "LCD"), /* dat23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) TOP_MUX(0x3, "BGPIO"), /* gpio75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) TOP_MUX(0x4, "UART5"), /* cts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) TOP_MUX(0x5, "PCM"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) TOP_MUX(0x6, "I2S0"), /* din3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) TOP_MUX(0x7, "B_DVI0")), /* d7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) TOP_MUX(0x0, "NAND"), /* ldo_ms18_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) TOP_MUX(0x1, "BGPIO")), /* gpio99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* top_pmm_reg_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) TOP_MUX(0x0, "SPI3"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) TOP_MUX(0x1, "TSO1"), /* dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) TOP_MUX(0x2, "LCD"), /* stvu_vsync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) TOP_MUX(0x3, "BGPIO"), /* gpio76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) TOP_MUX(0x4, "UART5"), /* rts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) TOP_MUX(0x5, "PCM"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TOP_MUX(0x6, "I2S0"), /* dout1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) TOP_MUX(0x7, "B_DVI1")), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) TOP_MUX(0x0, "I2S0"), /* mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TOP_MUX(0x1, "TSO1"), /* dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) TOP_MUX(0x2, "LCD"), /* stvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) TOP_MUX(0x3, "BGPIO"), /* gpio77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) TOP_MUX(0x4, "USIM0"), /* cd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) TOP_MUX(0x5, "B_DVI1")), /* vs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) TOP_MUX(0x0, "I2S0"), /* bclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) TOP_MUX(0x1, "TSO1"), /* dat4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) TOP_MUX(0x2, "LCD"), /* sthl_hsync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) TOP_MUX(0x3, "BGPIO"), /* gpio78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) TOP_MUX(0x4, "USIM0"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) TOP_MUX(0x5, "B_DVI1")), /* hs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) TOP_MUX(0x0, "I2S0"), /* ws */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) TOP_MUX(0x1, "TSO1"), /* dat5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) TOP_MUX(0x2, "LCD"), /* sthr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) TOP_MUX(0x3, "BGPIO"), /* gpio79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) TOP_MUX(0x4, "USIM0"), /* rst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) TOP_MUX(0x5, "B_DVI1")), /* d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) TOP_MUX(0x0, "I2S0"), /* din0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) TOP_MUX(0x1, "TSO1"), /* dat6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) TOP_MUX(0x2, "LCD"), /* oev_dataen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) TOP_MUX(0x3, "BGPIO"), /* gpio80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) TOP_MUX(0x4, "USIM0"), /* dat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) TOP_MUX(0x5, "B_DVI1")), /* d1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) TOP_MUX(0x0, "I2S0"), /* dout0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) TOP_MUX(0x1, "TSO1"), /* dat7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) TOP_MUX(0x2, "LCD"), /* ckv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) TOP_MUX(0x3, "BGPIO")), /* gpio81 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) TOP_MUX(0x0, "I2C5"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) TOP_MUX(0x1, "TSO1"), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) TOP_MUX(0x2, "LCD"), /* ld */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) TOP_MUX(0x3, "BGPIO"), /* gpio82 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) TOP_MUX(0x4, "PWM"), /* out2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) TOP_MUX(0x5, "I2S0"), /* dout2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) TOP_MUX(0x6, "B_DVI1")), /* d2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) TOP_MUX(0x0, "I2C5"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) TOP_MUX(0x1, "TSO1"), /* vld */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) TOP_MUX(0x2, "LCD"), /* pol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) TOP_MUX(0x3, "BGPIO"), /* gpio83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) TOP_MUX(0x4, "PWM"), /* out3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) TOP_MUX(0x5, "I2S0"), /* dout3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) TOP_MUX(0x6, "B_DVI1")), /* d3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) TOP_MUX(0x0, "SPI2"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) TOP_MUX(0x1, "TSO0"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) TOP_MUX(0x2, "LCD"), /* degsl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) TOP_MUX(0x3, "BGPIO"), /* gpio84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) TOP_MUX(0x4, "I2C4"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) TOP_MUX(0x5, "B_DVI1")), /* d4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) TOP_MUX(0x0, "SPI2"), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) TOP_MUX(0x1, "TSO0"), /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) TOP_MUX(0x2, "LCD"), /* rev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) TOP_MUX(0x3, "BGPIO"), /* gpio85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) TOP_MUX(0x4, "I2C4"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) TOP_MUX(0x5, "B_DVI1")), /* d5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) TOP_MUX(0x0, "SPI2"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) TOP_MUX(0x1, "TSO0"), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) TOP_MUX(0x2, "LCD"), /* u_d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) TOP_MUX(0x3, "BGPIO"), /* gpio86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) TOP_MUX(0x4, "I2C4"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) TOP_MUX(0x5, "B_DVI1")), /* d6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* top_pmm_reg_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) TOP_MUX(0x0, "SPI2"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) TOP_MUX(0x1, "TSO0"), /* vld */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) TOP_MUX(0x2, "LCD"), /* r_l */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) TOP_MUX(0x3, "BGPIO"), /* gpio87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) TOP_MUX(0x4, "I2C3"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) TOP_MUX(0x5, "B_DVI1")), /* d7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) TOP_MUX(0x0, "NAND"), /* wp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) TOP_MUX(0x1, "PWM"), /* out2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) TOP_MUX(0x2, "SPI2"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) TOP_MUX(0x3, "BGPIO"), /* gpio88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) TOP_MUX(0x4, "TSI0"), /* dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) TOP_MUX(0x5, "I2S1")), /* din1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) TOP_MUX(0x0, "NAND"), /* boot_pagesize0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) TOP_MUX(0x1, "PWM"), /* out3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) TOP_MUX(0x2, "SPI2"), /* cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) TOP_MUX(0x3, "BGPIO"), /* gpio89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) TOP_MUX(0x4, "TSI0"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) TOP_MUX(0x5, "I2S1")), /* din2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) TOP_MUX(0x0, "NAND"), /* boot_pagesize1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) TOP_MUX(0x1, "I2C4"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) TOP_MUX(0x2, "SPI2"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) TOP_MUX(0x3, "BGPIO"), /* gpio90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) TOP_MUX(0x4, "TSI0"), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) TOP_MUX(0x5, "I2S1")), /* din3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) TOP_MUX(0x0, "NAND"), /* boot_addr_cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) TOP_MUX(0x1, "I2C4"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) TOP_MUX(0x2, "SPI2"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) TOP_MUX(0x3, "BGPIO"), /* gpio91 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) TOP_MUX(0x4, "TSI0"), /* valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) TOP_MUX(0x5, "I2S1")), /* dout1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) TOP_MUX(0x0, "NAND"), /* rdy_busy0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) TOP_MUX(0x1, "I2C2"), /* scl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) TOP_MUX(0x2, "USIM0"), /* cd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) TOP_MUX(0x3, "BGPIO"), /* gpio92 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) TOP_MUX(0x4, "TSI1")), /* data0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) TOP_MUX(0x0, "NAND"), /* rdy_busy1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) TOP_MUX(0x1, "I2C2"), /* sda */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) TOP_MUX(0x2, "USIM0"), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) TOP_MUX(0x3, "BGPIO"), /* gpio93 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) TOP_MUX(0x4, "TSI1")), /* clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) TOP_MUX(0x0, "NAND"), /* rdy_busy2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) TOP_MUX(0x1, "UART5"), /* rxd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) TOP_MUX(0x2, "USIM0"), /* rst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) TOP_MUX(0x3, "BGPIO"), /* gpio94 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) TOP_MUX(0x4, "TSI1"), /* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) TOP_MUX(0x4, "I2S1")), /* dout2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) TOP_MUX(0x0, "NAND"), /* rdy_busy3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) TOP_MUX(0x1, "UART5"), /* txd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) TOP_MUX(0x2, "USIM0"), /* dat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) TOP_MUX(0x3, "BGPIO"), /* gpio95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) TOP_MUX(0x4, "TSI1"), /* valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) TOP_MUX(0x4, "I2S1")), /* dout3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* top_pmm_reg_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) TOP_MUX(0x0, "GMII"), /* 125m_in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) TOP_MUX(0x1, "USB2"), /* 0_drvvbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) TOP_MUX(0x2, "ISP"), /* ref_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) TOP_MUX(0x3, "BGPIO")), /* gpio96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) TOP_MUX(0x0, "GMII"), /* 50m_out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) TOP_MUX(0x1, "USB2"), /* 1_drvvbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) TOP_MUX(0x2, "BGPIO"), /* gpio97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) TOP_MUX(0x3, "USB2")), /* 0_drvvbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) TOP_MUX(0x0, "SPINOR")), /* sdio1_clk_i */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) TOP_MUX(0x0, "SPINOR")), /* ssclk_i */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static struct zx_pinctrl_soc_info zx296718_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .pins = zx296718_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .npins = ARRAY_SIZE(zx296718_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int zx296718_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return zx_pinctrl_init(pdev, &zx296718_pinctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const struct of_device_id zx296718_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) { .compatible = "zte,zx296718-pmm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static struct platform_driver zx296718_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .probe = zx296718_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .name = "zx296718-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .of_match_table = zx296718_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) builtin_platform_driver(zx296718_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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