Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 Sanechips Technology Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "../pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "pinctrl-zx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ZX_PULL_DOWN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ZX_PULL_UP		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define ZX_INPUT_ENABLE		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define ZX_DS_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define ZX_DS_MASK		(0x7 << ZX_DS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ZX_DS_VALUE(x)		(((x) << ZX_DS_SHIFT) & ZX_DS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ZX_SLEW			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct zx_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct pinctrl_dev *pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	void __iomem *aux_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct zx_pinctrl_soc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static int zx_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 			     struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			     struct pinctrl_map **map, u32 *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 					      num_maps, PIN_MAP_TYPE_INVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static const struct pinctrl_ops zx_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.dt_node_to_map = zx_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.get_groups_count = pinctrl_generic_get_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.get_group_name = pinctrl_generic_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.get_group_pins = pinctrl_generic_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define NONAON_MVAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		      unsigned int group_selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct zx_pinctrl_soc_info *info = zpctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	const struct pinctrl_pin_desc *pindesc = info->pins + group_selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct zx_pin_data *data = pindesc->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct zx_mux_desc *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 mask, offset, bitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 val, mval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* Skip reserved pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	mux = data->muxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	mask = (1 << data->width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	offset = data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	bitpos = data->bitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	func = pinmux_generic_get_function(pctldev, func_selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	while (mux->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		if (strcmp(mux->name, func->name) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		mux++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* Found mux value to be written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	mval = mux->muxval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	spin_lock_irqsave(&zpctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (data->aon_pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 * It's an AON pin, whose mux register offset and bit position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		 * can be calculated from pin number.  Each register covers 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		 * pins, and each pin occupies 2 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		u16 aoffset = pindesc->number / 16 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		u16 abitpos = (pindesc->number % 16) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		if (mval & AON_MUX_FLAG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			 * This is a mux value that needs to be written into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			 * AON pinmux register.  Write it and then we're done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			val = readl(zpctl->aux_base + aoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			val &= ~(0x3 << abitpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			val |= (mval & 0x3) << abitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			writel(val, zpctl->aux_base + aoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			 * It's a mux value that needs to be written into TOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			 * pinmux register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			val = readl(zpctl->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			val &= ~(mask << bitpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			val |= (mval & mask) << bitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			writel(val, zpctl->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			 * In this case, the AON pinmux register needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			 * set up to select non-AON function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			val = readl(zpctl->aux_base + aoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			val &= ~(0x3 << abitpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			val |= NONAON_MVAL << abitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			writel(val, zpctl->aux_base + aoffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		 * This is a TOP pin, and we only need to set up TOP pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		 * register and then we're done with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		val = readl(zpctl->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		val &= ~(mask << bitpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		val |= (mval & mask) << bitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		writel(val, zpctl->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	spin_unlock_irqrestore(&zpctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct pinmux_ops zx_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.get_functions_count = pinmux_generic_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.get_function_name = pinmux_generic_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.get_function_groups = pinmux_generic_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.set_mux = zx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			     unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct zx_pinctrl_soc_info *info = zpctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	const struct pinctrl_pin_desc *pindesc = info->pins + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct zx_pin_data *data = pindesc->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* Skip reserved pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	val = readl(zpctl->aux_base + data->coffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	val = val >> data->cbitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		val &= ZX_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		val = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		val &= ZX_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		val = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		if (val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		val &= ZX_INPUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		val = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		if (val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		val &= ZX_DS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		val = val >> ZX_DS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		val &= ZX_SLEW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		val = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	*config = pinconf_to_config_packed(param, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			     unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct zx_pinctrl_soc_info *info = zpctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	const struct pinctrl_pin_desc *pindesc = info->pins + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct zx_pin_data *data = pindesc->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 val, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* Skip reserved pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	val = readl(zpctl->aux_base + data->coffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			val |= ZX_PULL_DOWN << data->cbitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			val |= ZX_PULL_UP << data->cbitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			val |= ZX_INPUT_ENABLE << data->cbitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			val &= ~(ZX_DS_MASK << data->cbitpos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			val |= ZX_DS_VALUE(arg) << data->cbitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				val |= ZX_SLEW << data->cbitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				val &= ~ZX_SLEW << data->cbitpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	writel(val, zpctl->aux_base + data->coffset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct pinconf_ops zx_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.pin_config_set = zx_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.pin_config_get = zx_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int zx_pinctrl_build_state(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct zx_pinctrl *zpctl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct zx_pinctrl_soc_info *info = zpctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct pinctrl_dev *pctldev = zpctl->pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct function_desc *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct group_desc *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Every single pin composes a group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	ngroups = info->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	groups = devm_kcalloc(&pdev->dev, ngroups, sizeof(*groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			      GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (!groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	for (i = 0; i < ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		const struct pinctrl_pin_desc *pindesc = info->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		struct group_desc *group = groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		group->name = pindesc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		group->pins = (int *) &pindesc->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		group->num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		radix_tree_insert(&pctldev->pin_group_tree, i, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	pctldev->num_groups = ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/* Build function list from pin mux functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	functions = kcalloc(info->npins, sizeof(*functions), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (!functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	nfunctions = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	for (i = 0; i < info->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		const struct pinctrl_pin_desc *pindesc = info->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		struct zx_pin_data *data = pindesc->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		struct zx_mux_desc *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		/* Reserved pins do not have a drv_data at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		/* Loop over all muxes for the pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		mux = data->muxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		while (mux->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			struct function_desc *func = functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			/* Search function list for given mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			while (func->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				if (strcmp(mux->name, func->name) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 					/* Function exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 					func->num_group_names++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 					break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				func++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			if (!func->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 				/* New function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				func->name = mux->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 				func->num_group_names = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 				radix_tree_insert(&pctldev->pin_function_tree,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 						  nfunctions++, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			mux++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	pctldev->num_functions = nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	functions = krealloc(functions, nfunctions * sizeof(*functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	/* Find pin groups for every single function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	for (i = 0; i < info->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		const struct pinctrl_pin_desc *pindesc = info->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		struct zx_pin_data *data = pindesc->drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		struct zx_mux_desc *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		mux = data->muxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		while (mux->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			const char **group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			/* Find function for given mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			for (j = 0; j < nfunctions; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				if (strcmp(functions[j].name, mux->name) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 					break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			func = functions + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			if (!func->group_names) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 				func->group_names = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 						func->num_group_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 						sizeof(*func->group_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 						GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 				if (!func->group_names) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 					kfree(functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 					return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			group = func->group_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			while (*group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 				group++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			*group = pindesc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			mux++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int zx_pinctrl_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		    struct zx_pinctrl_soc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	struct pinctrl_desc *pctldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	struct zx_pinctrl *zpctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (!zpctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	spin_lock_init(&zpctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	zpctl->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (IS_ERR(zpctl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return PTR_ERR(zpctl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		dev_err(&pdev->dev, "failed to find auxiliary controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	zpctl->aux_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (!zpctl->aux_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	zpctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	zpctl->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (!pctldesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	pctldesc->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	pctldesc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	pctldesc->pins = info->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	pctldesc->npins = info->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	pctldesc->pctlops = &zx_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	pctldesc->pmxops = &zx_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	pctldesc->confops = &zx_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (IS_ERR(zpctl->pctldev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		ret = PTR_ERR(zpctl->pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	platform_set_drvdata(pdev, zpctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	ret = zx_pinctrl_build_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		dev_err(&pdev->dev, "failed to build state: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	dev_info(&pdev->dev, "initialized pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }