Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Pinctrl data for Wondermedia WM8650 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "pinctrl-wmt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Describe the register offsets within the GPIO memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * The dedicated external GPIO's should always be listed in bank 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * so they are exported in the 0..31 range which is what users
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * expect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Do not reorder these banks as it will change the pin numbering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static const struct wmt_pinctrl_bank_registers wm8650_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	WMT_PINCTRL_BANK(0x40, 0x80, 0xC0, 0x00, 0x480, 0x4C0),		/* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	WMT_PINCTRL_BANK(0x44, 0x84, 0xC4, 0x04, 0x484, 0x4C4),		/* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	WMT_PINCTRL_BANK(0x48, 0x88, 0xC8, 0x08, 0x488, 0x4C8),		/* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	WMT_PINCTRL_BANK(0x4C, 0x8C, 0xCC, 0x0C, 0x48C, 0x4CC),		/* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	WMT_PINCTRL_BANK(0x50, 0x90, 0xD0, 0x10, 0x490, 0x4D0),		/* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	WMT_PINCTRL_BANK(0x54, 0x94, 0xD4, 0x14, 0x494, 0x4D4),		/* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	WMT_PINCTRL_BANK(0x58, 0x98, 0xD8, 0x18, 0x498, 0x4D8),		/* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	WMT_PINCTRL_BANK(0x5C, 0x9C, 0xDC, 0x1C, 0x49C, 0x4DC),		/* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Please keep sorted by bank/bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define WMT_PIN_EXTGPIO0	WMT_PIN(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define WMT_PIN_EXTGPIO1	WMT_PIN(0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WMT_PIN_EXTGPIO2	WMT_PIN(0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WMT_PIN_EXTGPIO3	WMT_PIN(0, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WMT_PIN_EXTGPIO4	WMT_PIN(0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WMT_PIN_EXTGPIO5	WMT_PIN(0, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WMT_PIN_EXTGPIO6	WMT_PIN(0, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WMT_PIN_EXTGPIO7	WMT_PIN(0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WMT_PIN_WAKEUP0		WMT_PIN(0, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WMT_PIN_WAKEUP1		WMT_PIN(0, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WMT_PIN_SUSGPIO0	WMT_PIN(0, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WMT_PIN_SD0CD		WMT_PIN(0, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WMT_PIN_SD1CD		WMT_PIN(0, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define WMT_PIN_VDOUT0		WMT_PIN(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define WMT_PIN_VDOUT1		WMT_PIN(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define WMT_PIN_VDOUT2		WMT_PIN(1, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define WMT_PIN_VDOUT3		WMT_PIN(1, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define WMT_PIN_VDOUT4		WMT_PIN(1, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define WMT_PIN_VDOUT5		WMT_PIN(1, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define WMT_PIN_VDOUT6		WMT_PIN(1, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define WMT_PIN_VDOUT7		WMT_PIN(1, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define WMT_PIN_VDOUT8		WMT_PIN(1, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define WMT_PIN_VDOUT9		WMT_PIN(1, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define WMT_PIN_VDOUT10		WMT_PIN(1, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define WMT_PIN_VDOUT11		WMT_PIN(1, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define WMT_PIN_VDOUT12		WMT_PIN(1, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define WMT_PIN_VDOUT13		WMT_PIN(1, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define WMT_PIN_VDOUT14		WMT_PIN(1, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define WMT_PIN_VDOUT15		WMT_PIN(1, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define WMT_PIN_VDOUT16		WMT_PIN(1, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define WMT_PIN_VDOUT17		WMT_PIN(1, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define WMT_PIN_VDOUT18		WMT_PIN(1, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define WMT_PIN_VDOUT19		WMT_PIN(1, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define WMT_PIN_VDOUT20		WMT_PIN(1, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define WMT_PIN_VDOUT21		WMT_PIN(1, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define WMT_PIN_VDOUT22		WMT_PIN(1, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define WMT_PIN_VDOUT23		WMT_PIN(1, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define WMT_PIN_VDIN0		WMT_PIN(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define WMT_PIN_VDIN1		WMT_PIN(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define WMT_PIN_VDIN2		WMT_PIN(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define WMT_PIN_VDIN3		WMT_PIN(2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define WMT_PIN_VDIN4		WMT_PIN(2, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define WMT_PIN_VDIN5		WMT_PIN(2, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define WMT_PIN_VDIN6		WMT_PIN(2, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define WMT_PIN_VDIN7		WMT_PIN(2, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define WMT_PIN_I2C1SCL		WMT_PIN(2, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define WMT_PIN_I2C1SDA		WMT_PIN(2, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define WMT_PIN_SPI0MOSI	WMT_PIN(2, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define WMT_PIN_SPI0MISO	WMT_PIN(2, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define WMT_PIN_SPI0SS0		WMT_PIN(2, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define WMT_PIN_SPI0CLK		WMT_PIN(2, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define WMT_PIN_SD0DATA0	WMT_PIN(3, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define WMT_PIN_SD0DATA1	WMT_PIN(3, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define WMT_PIN_SD0DATA2	WMT_PIN(3, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define WMT_PIN_SD0DATA3	WMT_PIN(3, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define WMT_PIN_SD0CLK		WMT_PIN(3, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define WMT_PIN_SD0WP		WMT_PIN(3, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define WMT_PIN_SD0CMD		WMT_PIN(3, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define WMT_PIN_SD1DATA0	WMT_PIN(3, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define WMT_PIN_SD1DATA1	WMT_PIN(3, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define WMT_PIN_SD1DATA2	WMT_PIN(3, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define WMT_PIN_SD1DATA3	WMT_PIN(3, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define WMT_PIN_SD1DATA4	WMT_PIN(3, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define WMT_PIN_SD1DATA5	WMT_PIN(3, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WMT_PIN_SD1DATA6	WMT_PIN(3, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WMT_PIN_SD1DATA7	WMT_PIN(3, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WMT_PIN_I2C0SCL		WMT_PIN(5, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WMT_PIN_I2C0SDA		WMT_PIN(5, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WMT_PIN_UART0RTS	WMT_PIN(5, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WMT_PIN_UART0TXD	WMT_PIN(5, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WMT_PIN_UART0CTS	WMT_PIN(5, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WMT_PIN_UART0RXD	WMT_PIN(5, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WMT_PIN_UART1RTS	WMT_PIN(5, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WMT_PIN_UART1TXD	WMT_PIN(5, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WMT_PIN_UART1CTS	WMT_PIN(5, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WMT_PIN_UART1RXD	WMT_PIN(5, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WMT_PIN_UART2RTS	WMT_PIN(5, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WMT_PIN_UART2TXD	WMT_PIN(5, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WMT_PIN_UART2CTS	WMT_PIN(5, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WMT_PIN_UART2RXD	WMT_PIN(5, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WMT_PIN_UART3RTS	WMT_PIN(5, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WMT_PIN_UART3TXD	WMT_PIN(5, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WMT_PIN_UART3CTS	WMT_PIN(5, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WMT_PIN_UART3RXD	WMT_PIN(5, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WMT_PIN_KPADROW0	WMT_PIN(6, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define WMT_PIN_KPADROW1	WMT_PIN(6, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WMT_PIN_KPADCOL0	WMT_PIN(6, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define WMT_PIN_KPADCOL1	WMT_PIN(6, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define WMT_PIN_SD1CLK		WMT_PIN(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define WMT_PIN_SD1CMD		WMT_PIN(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define WMT_PIN_SD1WP		WMT_PIN(7, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct pinctrl_pin_desc wm8650_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	PINCTRL_PIN(WMT_PIN_SPI0SS0, "spi0_ss0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	PINCTRL_PIN(WMT_PIN_SD0DATA0, "sd0_data0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	PINCTRL_PIN(WMT_PIN_SD0DATA1, "sd0_data1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	PINCTRL_PIN(WMT_PIN_SD0DATA2, "sd0_data2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	PINCTRL_PIN(WMT_PIN_SD0DATA3, "sd0_data3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	PINCTRL_PIN(WMT_PIN_SD0CLK, "sd0_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	PINCTRL_PIN(WMT_PIN_SD0WP, "sd0_wp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	PINCTRL_PIN(WMT_PIN_SD0CMD, "sd0_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	PINCTRL_PIN(WMT_PIN_SD1DATA0, "sd1_data0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	PINCTRL_PIN(WMT_PIN_SD1DATA1, "sd1_data1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	PINCTRL_PIN(WMT_PIN_SD1DATA2, "sd1_data2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	PINCTRL_PIN(WMT_PIN_SD1DATA3, "sd1_data3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	PINCTRL_PIN(WMT_PIN_SD1DATA4, "sd1_data4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	PINCTRL_PIN(WMT_PIN_SD1DATA5, "sd1_data5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	PINCTRL_PIN(WMT_PIN_SD1DATA6, "sd1_data6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	PINCTRL_PIN(WMT_PIN_SD1DATA7, "sd1_data7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	PINCTRL_PIN(WMT_PIN_UART0RTS, "uart0_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	PINCTRL_PIN(WMT_PIN_UART0TXD, "uart0_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	PINCTRL_PIN(WMT_PIN_UART0CTS, "uart0_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	PINCTRL_PIN(WMT_PIN_UART0RXD, "uart0_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	PINCTRL_PIN(WMT_PIN_UART1RTS, "uart1_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	PINCTRL_PIN(WMT_PIN_UART1TXD, "uart1_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	PINCTRL_PIN(WMT_PIN_UART1CTS, "uart1_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	PINCTRL_PIN(WMT_PIN_UART1RXD, "uart1_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	PINCTRL_PIN(WMT_PIN_UART2RTS, "uart2_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	PINCTRL_PIN(WMT_PIN_UART2TXD, "uart2_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	PINCTRL_PIN(WMT_PIN_UART2CTS, "uart2_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	PINCTRL_PIN(WMT_PIN_UART2RXD, "uart2_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	PINCTRL_PIN(WMT_PIN_UART3RTS, "uart3_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	PINCTRL_PIN(WMT_PIN_UART3TXD, "uart3_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	PINCTRL_PIN(WMT_PIN_UART3CTS, "uart3_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	PINCTRL_PIN(WMT_PIN_UART3RXD, "uart3_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	PINCTRL_PIN(WMT_PIN_KPADROW0, "kpadrow0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	PINCTRL_PIN(WMT_PIN_KPADROW1, "kpadrow1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	PINCTRL_PIN(WMT_PIN_KPADCOL0, "kpadcol0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	PINCTRL_PIN(WMT_PIN_KPADCOL1, "kpadcol1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	PINCTRL_PIN(WMT_PIN_SD1CLK, "sd1_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	PINCTRL_PIN(WMT_PIN_SD1CMD, "sd1_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	PINCTRL_PIN(WMT_PIN_SD1WP, "sd1_wp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Order of these names must match the above list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const char * const wm8650_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	"extgpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	"extgpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	"extgpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	"extgpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	"extgpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	"extgpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	"extgpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	"extgpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	"wakeup0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	"wakeup1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	"susgpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	"sd0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	"sd1_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	"vdout0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	"vdout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	"vdout2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	"vdout3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	"vdout4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	"vdout5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	"vdout6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	"vdout7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	"vdout8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	"vdout9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	"vdout10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	"vdout11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	"vdout12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	"vdout13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	"vdout14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	"vdout15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	"vdout16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	"vdout17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	"vdout18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	"vdout19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	"vdout20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	"vdout21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	"vdout22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	"vdout23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	"vdin0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	"vdin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	"vdin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	"vdin3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	"vdin4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	"vdin5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	"vdin6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	"vdin7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	"i2c1_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	"i2c1_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	"spi0_mosi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	"spi0_miso",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	"spi0_ss0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	"spi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	"sd0_data0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	"sd0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	"sd0_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	"sd0_data3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	"sd0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	"sd0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	"sd0_cmd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	"sd1_data0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	"sd1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	"sd1_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	"sd1_data3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	"sd1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	"sd1_data5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	"sd1_data6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	"sd1_data7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	"i2c0_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	"i2c0_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	"uart0_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	"uart0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	"uart0_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	"uart0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	"uart1_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	"uart1_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	"uart1_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	"uart1_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	"uart2_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	"uart2_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	"uart2_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	"uart2_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	"uart3_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	"uart3_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	"uart3_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	"uart3_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	"kpadrow0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	"kpadrow1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	"kpadcol0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	"kpadcol1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	"sd1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	"sd1_cmd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	"sd1_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int wm8650_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct wmt_pinctrl_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	data->banks = wm8650_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	data->nbanks = ARRAY_SIZE(wm8650_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	data->pins = wm8650_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	data->npins = ARRAY_SIZE(wm8650_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	data->groups = wm8650_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	data->ngroups = ARRAY_SIZE(wm8650_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return wmt_pinctrl_probe(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct of_device_id wmt_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{ .compatible = "wm,wm8650-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct platform_driver wmt_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.probe	= wm8650_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.name	= "pinctrl-wm8650",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.of_match_table	= wmt_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) builtin_platform_driver(wmt_pinctrl_driver);