^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pinctrl data for Wondermedia WM8505 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pinctrl-wmt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Describe the register offsets within the GPIO memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * The dedicated external GPIO's should always be listed in bank 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * so they are exported in the 0..31 range which is what users
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * expect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Do not reorder these banks as it will change the pin numbering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct wmt_pinctrl_bank_registers wm8505_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) WMT_PINCTRL_BANK(0x64, 0x8C, 0xB4, 0xDC, NO_REG, NO_REG), /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) WMT_PINCTRL_BANK(0x40, 0x68, 0x90, 0xB8, NO_REG, NO_REG), /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) WMT_PINCTRL_BANK(0x44, 0x6C, 0x94, 0xBC, NO_REG, NO_REG), /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) WMT_PINCTRL_BANK(0x48, 0x70, 0x98, 0xC0, NO_REG, NO_REG), /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) WMT_PINCTRL_BANK(0x4C, 0x74, 0x9C, 0xC4, NO_REG, NO_REG), /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) WMT_PINCTRL_BANK(0x50, 0x78, 0xA0, 0xC8, NO_REG, NO_REG), /* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) WMT_PINCTRL_BANK(0x54, 0x7C, 0xA4, 0xD0, NO_REG, NO_REG), /* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) WMT_PINCTRL_BANK(0x58, 0x80, 0xA8, 0xD4, NO_REG, NO_REG), /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) WMT_PINCTRL_BANK(0x5C, 0x84, 0xAC, 0xD8, NO_REG, NO_REG), /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) WMT_PINCTRL_BANK(0x60, 0x88, 0xB0, 0xDC, NO_REG, NO_REG), /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) WMT_PINCTRL_BANK(0x500, 0x504, 0x508, 0x50C, NO_REG, NO_REG), /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Please keep sorted by bank/bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WMT_PIN_EXTGPIO0 WMT_PIN(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WMT_PIN_EXTGPIO1 WMT_PIN(0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WMT_PIN_EXTGPIO2 WMT_PIN(0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WMT_PIN_EXTGPIO3 WMT_PIN(0, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WMT_PIN_EXTGPIO4 WMT_PIN(0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WMT_PIN_EXTGPIO5 WMT_PIN(0, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WMT_PIN_EXTGPIO6 WMT_PIN(0, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WMT_PIN_EXTGPIO7 WMT_PIN(0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WMT_PIN_WAKEUP0 WMT_PIN(0, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WMT_PIN_WAKEUP1 WMT_PIN(0, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WMT_PIN_WAKEUP2 WMT_PIN(0, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WMT_PIN_WAKEUP3 WMT_PIN(0, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WMT_PIN_SUSGPIO0 WMT_PIN(0, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WMT_PIN_SDDATA0 WMT_PIN(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WMT_PIN_SDDATA1 WMT_PIN(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WMT_PIN_SDDATA2 WMT_PIN(1, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WMT_PIN_SDDATA3 WMT_PIN(1, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WMT_PIN_MMCDATA0 WMT_PIN(1, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WMT_PIN_MMCDATA1 WMT_PIN(1, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WMT_PIN_MMCDATA2 WMT_PIN(1, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WMT_PIN_MMCDATA3 WMT_PIN(1, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WMT_PIN_VDIN0 WMT_PIN(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WMT_PIN_VDIN1 WMT_PIN(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WMT_PIN_VDIN2 WMT_PIN(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WMT_PIN_VDIN3 WMT_PIN(2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define WMT_PIN_VDIN4 WMT_PIN(2, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define WMT_PIN_VDIN5 WMT_PIN(2, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WMT_PIN_VDIN6 WMT_PIN(2, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define WMT_PIN_VDIN7 WMT_PIN(2, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define WMT_PIN_VDOUT0 WMT_PIN(2, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define WMT_PIN_VDOUT1 WMT_PIN(2, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WMT_PIN_VDOUT2 WMT_PIN(2, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define WMT_PIN_VDOUT3 WMT_PIN(2, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WMT_PIN_VDOUT4 WMT_PIN(2, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define WMT_PIN_VDOUT5 WMT_PIN(2, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WMT_PIN_VDOUT6 WMT_PIN(2, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WMT_PIN_VDOUT7 WMT_PIN(2, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WMT_PIN_VDOUT8 WMT_PIN(2, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WMT_PIN_VDOUT9 WMT_PIN(2, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define WMT_PIN_VDOUT10 WMT_PIN(2, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define WMT_PIN_VDOUT11 WMT_PIN(2, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define WMT_PIN_VDOUT12 WMT_PIN(2, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define WMT_PIN_VDOUT13 WMT_PIN(2, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define WMT_PIN_VDOUT14 WMT_PIN(2, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WMT_PIN_VDOUT15 WMT_PIN(2, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WMT_PIN_VDOUT16 WMT_PIN(2, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WMT_PIN_VDOUT17 WMT_PIN(2, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define WMT_PIN_VDOUT18 WMT_PIN(2, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define WMT_PIN_VDOUT19 WMT_PIN(2, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define WMT_PIN_VDOUT20 WMT_PIN(2, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define WMT_PIN_VDOUT21 WMT_PIN(2, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define WMT_PIN_VDOUT22 WMT_PIN(2, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define WMT_PIN_VDOUT23 WMT_PIN(2, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define WMT_PIN_VHSYNC WMT_PIN(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define WMT_PIN_VVSYNC WMT_PIN(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define WMT_PIN_VGAHSYNC WMT_PIN(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define WMT_PIN_VGAVSYNC WMT_PIN(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define WMT_PIN_VDHSYNC WMT_PIN(3, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define WMT_PIN_VDVSYNC WMT_PIN(3, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define WMT_PIN_NORD0 WMT_PIN(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define WMT_PIN_NORD1 WMT_PIN(4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WMT_PIN_NORD2 WMT_PIN(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WMT_PIN_NORD3 WMT_PIN(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WMT_PIN_NORD4 WMT_PIN(4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WMT_PIN_NORD5 WMT_PIN(4, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WMT_PIN_NORD6 WMT_PIN(4, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WMT_PIN_NORD7 WMT_PIN(4, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WMT_PIN_NORD8 WMT_PIN(4, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WMT_PIN_NORD9 WMT_PIN(4, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WMT_PIN_NORD10 WMT_PIN(4, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WMT_PIN_NORD11 WMT_PIN(4, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WMT_PIN_NORD12 WMT_PIN(4, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WMT_PIN_NORD13 WMT_PIN(4, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WMT_PIN_NORD14 WMT_PIN(4, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WMT_PIN_NORD15 WMT_PIN(4, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WMT_PIN_NORA0 WMT_PIN(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WMT_PIN_NORA1 WMT_PIN(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WMT_PIN_NORA2 WMT_PIN(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WMT_PIN_NORA3 WMT_PIN(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WMT_PIN_NORA4 WMT_PIN(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WMT_PIN_NORA5 WMT_PIN(5, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WMT_PIN_NORA6 WMT_PIN(5, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define WMT_PIN_NORA7 WMT_PIN(5, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WMT_PIN_NORA8 WMT_PIN(5, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define WMT_PIN_NORA9 WMT_PIN(5, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define WMT_PIN_NORA10 WMT_PIN(5, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define WMT_PIN_NORA11 WMT_PIN(5, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define WMT_PIN_NORA12 WMT_PIN(5, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define WMT_PIN_NORA13 WMT_PIN(5, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define WMT_PIN_NORA14 WMT_PIN(5, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define WMT_PIN_NORA15 WMT_PIN(5, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define WMT_PIN_NORA16 WMT_PIN(5, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define WMT_PIN_NORA17 WMT_PIN(5, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define WMT_PIN_NORA18 WMT_PIN(5, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define WMT_PIN_NORA19 WMT_PIN(5, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define WMT_PIN_NORA20 WMT_PIN(5, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define WMT_PIN_NORA21 WMT_PIN(5, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define WMT_PIN_NORA22 WMT_PIN(5, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define WMT_PIN_NORA23 WMT_PIN(5, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define WMT_PIN_NORA24 WMT_PIN(5, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define WMT_PIN_AC97SDI WMT_PIN(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define WMT_PIN_AC97SYNC WMT_PIN(6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define WMT_PIN_AC97SDO WMT_PIN(6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define WMT_PIN_AC97BCLK WMT_PIN(6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define WMT_PIN_AC97RST WMT_PIN(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define WMT_PIN_SFDO WMT_PIN(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define WMT_PIN_SFCS0 WMT_PIN(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define WMT_PIN_SFCS1 WMT_PIN(7, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define WMT_PIN_SFCLK WMT_PIN(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define WMT_PIN_SFDI WMT_PIN(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define WMT_PIN_SPI0CLK WMT_PIN(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define WMT_PIN_SPI0MISO WMT_PIN(8, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define WMT_PIN_SPI0MOSI WMT_PIN(8, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define WMT_PIN_SPI0SS WMT_PIN(8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define WMT_PIN_SPI1CLK WMT_PIN(8, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define WMT_PIN_SPI1MISO WMT_PIN(8, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define WMT_PIN_SPI1MOSI WMT_PIN(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define WMT_PIN_SPI1SS WMT_PIN(8, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define WMT_PIN_SPI2CLK WMT_PIN(8, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define WMT_PIN_SPI2MISO WMT_PIN(8, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define WMT_PIN_SPI2MOSI WMT_PIN(8, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define WMT_PIN_SPI2SS WMT_PIN(8, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define WMT_PIN_UART0_RTS WMT_PIN(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define WMT_PIN_UART0_TXD WMT_PIN(9, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define WMT_PIN_UART0_CTS WMT_PIN(9, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define WMT_PIN_UART0_RXD WMT_PIN(9, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define WMT_PIN_UART1_RTS WMT_PIN(9, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define WMT_PIN_UART1_TXD WMT_PIN(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define WMT_PIN_UART1_CTS WMT_PIN(9, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define WMT_PIN_UART1_RXD WMT_PIN(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define WMT_PIN_UART2_RTS WMT_PIN(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define WMT_PIN_UART2_TXD WMT_PIN(9, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define WMT_PIN_UART2_CTS WMT_PIN(9, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define WMT_PIN_UART2_RXD WMT_PIN(9, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define WMT_PIN_UART3_RTS WMT_PIN(9, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define WMT_PIN_UART3_TXD WMT_PIN(9, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define WMT_PIN_UART3_CTS WMT_PIN(9, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define WMT_PIN_UART3_RXD WMT_PIN(9, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define WMT_PIN_I2C0SCL WMT_PIN(10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define WMT_PIN_I2C0SDA WMT_PIN(10, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define WMT_PIN_I2C1SCL WMT_PIN(10, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define WMT_PIN_I2C1SDA WMT_PIN(10, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define WMT_PIN_I2C2SCL WMT_PIN(10, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define WMT_PIN_I2C2SDA WMT_PIN(10, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct pinctrl_pin_desc wm8505_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(WMT_PIN_WAKEUP2, "wakeup2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(WMT_PIN_WAKEUP3, "wakeup3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(WMT_PIN_SDDATA0, "sd_data0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(WMT_PIN_SDDATA1, "sd_data1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(WMT_PIN_SDDATA2, "sd_data2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(WMT_PIN_SDDATA3, "sd_data3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(WMT_PIN_MMCDATA0, "mmc_data0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(WMT_PIN_MMCDATA1, "mmc_data1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(WMT_PIN_MMCDATA2, "mmc_data2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(WMT_PIN_MMCDATA3, "mmc_data3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(WMT_PIN_VDOUT6, "vdout6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(WMT_PIN_VDOUT7, "vdout7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(WMT_PIN_VDOUT8, "vdout8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(WMT_PIN_VDOUT9, "vdout9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(WMT_PIN_VDOUT10, "vdout10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(WMT_PIN_VDOUT11, "vdout11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(WMT_PIN_VDOUT12, "vdout12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(WMT_PIN_VDOUT13, "vdout13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(WMT_PIN_VDOUT14, "vdout14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(WMT_PIN_VDOUT15, "vdout15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(WMT_PIN_VDOUT16, "vdout16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(WMT_PIN_VDOUT17, "vdout17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(WMT_PIN_VDOUT18, "vdout18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(WMT_PIN_VDOUT19, "vdout19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(WMT_PIN_VDOUT20, "vdout20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(WMT_PIN_VDOUT21, "vdout21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(WMT_PIN_VDOUT22, "vdout22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(WMT_PIN_VDOUT23, "vdout23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(WMT_PIN_VHSYNC, "v_hsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(WMT_PIN_VVSYNC, "v_vsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(WMT_PIN_VGAHSYNC, "vga_hsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(WMT_PIN_VGAVSYNC, "vga_vsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(WMT_PIN_VDHSYNC, "vd_hsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(WMT_PIN_VDVSYNC, "vd_vsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(WMT_PIN_NORD0, "nor_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(WMT_PIN_NORD1, "nor_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(WMT_PIN_NORD2, "nor_d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(WMT_PIN_NORD3, "nor_d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(WMT_PIN_NORD4, "nor_d4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(WMT_PIN_NORD5, "nor_d5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(WMT_PIN_NORD6, "nor_d6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(WMT_PIN_NORD7, "nor_d7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(WMT_PIN_NORD8, "nor_d8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(WMT_PIN_NORD9, "nor_d9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(WMT_PIN_NORD10, "nor_d10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(WMT_PIN_NORD11, "nor_d11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(WMT_PIN_NORD12, "nor_d12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(WMT_PIN_NORD13, "nor_d13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(WMT_PIN_NORD14, "nor_d14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(WMT_PIN_NORD15, "nor_d15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(WMT_PIN_NORA0, "nor_a0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(WMT_PIN_NORA1, "nor_a1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(WMT_PIN_NORA2, "nor_a2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(WMT_PIN_NORA3, "nor_a3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(WMT_PIN_NORA4, "nor_a4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(WMT_PIN_NORA5, "nor_a5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(WMT_PIN_NORA6, "nor_a6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(WMT_PIN_NORA7, "nor_a7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(WMT_PIN_NORA8, "nor_a8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(WMT_PIN_NORA9, "nor_a9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(WMT_PIN_NORA10, "nor_a10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(WMT_PIN_NORA11, "nor_a11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(WMT_PIN_NORA12, "nor_a12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(WMT_PIN_NORA13, "nor_a13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(WMT_PIN_NORA14, "nor_a14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(WMT_PIN_NORA15, "nor_a15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(WMT_PIN_NORA16, "nor_a16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(WMT_PIN_NORA17, "nor_a17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(WMT_PIN_NORA18, "nor_a18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(WMT_PIN_NORA19, "nor_a19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(WMT_PIN_NORA20, "nor_a20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(WMT_PIN_NORA21, "nor_a21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(WMT_PIN_NORA22, "nor_a22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(WMT_PIN_NORA23, "nor_a23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(WMT_PIN_NORA24, "nor_a24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(WMT_PIN_AC97SDI, "ac97_sdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(WMT_PIN_AC97SYNC, "ac97_sync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(WMT_PIN_AC97SDO, "ac97_sdo"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(WMT_PIN_AC97BCLK, "ac97_bclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(WMT_PIN_AC97RST, "ac97_rst"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(WMT_PIN_SFDO, "sf_do"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(WMT_PIN_SFCS0, "sf_cs0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(WMT_PIN_SFCS1, "sf_cs1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(WMT_PIN_SFCLK, "sf_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(WMT_PIN_SFDI, "sf_di"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(WMT_PIN_SPI0SS, "spi0_ss"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(WMT_PIN_SPI1CLK, "spi1_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(WMT_PIN_SPI1MISO, "spi1_miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(WMT_PIN_SPI1MOSI, "spi1_mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(WMT_PIN_SPI1SS, "spi1_ss"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(WMT_PIN_SPI2CLK, "spi2_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(WMT_PIN_SPI2MISO, "spi2_miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(WMT_PIN_SPI2MOSI, "spi2_mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(WMT_PIN_SPI2SS, "spi2_ss"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(WMT_PIN_UART0_RTS, "uart0_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(WMT_PIN_UART0_TXD, "uart0_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(WMT_PIN_UART0_CTS, "uart0_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(WMT_PIN_UART0_RXD, "uart0_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(WMT_PIN_UART1_RTS, "uart1_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(WMT_PIN_UART1_TXD, "uart1_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(WMT_PIN_UART1_CTS, "uart1_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(WMT_PIN_UART1_RXD, "uart1_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(WMT_PIN_UART2_RTS, "uart2_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(WMT_PIN_UART2_TXD, "uart2_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(WMT_PIN_UART2_CTS, "uart2_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(WMT_PIN_UART2_RXD, "uart2_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(WMT_PIN_UART3_RTS, "uart3_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(WMT_PIN_UART3_TXD, "uart3_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(WMT_PIN_UART3_CTS, "uart3_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(WMT_PIN_UART3_RXD, "uart3_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(WMT_PIN_I2C2SCL, "i2c2_scl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(WMT_PIN_I2C2SDA, "i2c2_sda"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Order of these names must match the above list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const char * const wm8505_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "extgpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "extgpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "extgpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "extgpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "extgpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "extgpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "extgpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "extgpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "wakeup0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "wakeup1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "wakeup2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "wakeup3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "susgpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "sd_data0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "sd_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "sd_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "sd_data3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "mmc_data0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "mmc_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "mmc_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "mmc_data3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "vdin0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "vdin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "vdin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "vdin3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "vdin4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "vdin5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "vdin6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "vdin7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "vdout0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "vdout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "vdout2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "vdout3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "vdout4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "vdout5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "vdout6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "vdout7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "vdout8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "vdout9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "vdout10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "vdout11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "vdout12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "vdout13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "vdout14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "vdout15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "vdout16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "vdout17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "vdout18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "vdout19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "vdout20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "vdout21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "vdout22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "vdout23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "v_hsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "v_vsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "vga_hsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "vga_vsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "vd_hsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "vd_vsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "nor_d0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "nor_d1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "nor_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "nor_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "nor_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "nor_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "nor_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "nor_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "nor_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "nor_d9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "nor_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "nor_d11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "nor_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "nor_d13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "nor_d14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "nor_d15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "nor_a0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "nor_a1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "nor_a2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "nor_a3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "nor_a4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "nor_a5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "nor_a6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "nor_a7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "nor_a8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "nor_a9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "nor_a10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "nor_a11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "nor_a12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "nor_a13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "nor_a14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "nor_a15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "nor_a16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "nor_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "nor_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "nor_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "nor_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "nor_a21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) "nor_a22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "nor_a23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "nor_a24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "ac97_sdi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "ac97_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "ac97_sdo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "ac97_bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "ac97_rst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "sf_do",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "sf_cs0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "sf_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "sf_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "sf_di",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "spi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "spi0_miso",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "spi0_mosi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "spi0_ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "spi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "spi1_miso",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "spi1_mosi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "spi1_ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "spi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "spi2_miso",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "spi2_mosi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "spi2_ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "uart0_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) "uart0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "uart0_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "uart0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "uart1_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "uart1_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "uart1_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "uart1_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "uart2_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "uart2_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "uart2_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "uart2_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "uart3_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "uart3_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "uart3_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "uart3_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "i2c0_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "i2c0_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "i2c1_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "i2c1_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "i2c2_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "i2c2_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int wm8505_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct wmt_pinctrl_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) data->banks = wm8505_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) data->nbanks = ARRAY_SIZE(wm8505_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) data->pins = wm8505_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) data->npins = ARRAY_SIZE(wm8505_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) data->groups = wm8505_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) data->ngroups = ARRAY_SIZE(wm8505_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return wmt_pinctrl_probe(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct of_device_id wmt_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { .compatible = "wm,wm8505-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static struct platform_driver wmt_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .probe = wm8505_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .name = "pinctrl-wm8505",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .of_match_table = wmt_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) builtin_platform_driver(wmt_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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