Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Pinctrl data for VIA VT8500 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2013 Tony Prisk <linux@prisktech.co.nz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "pinctrl-wmt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Describe the register offsets within the GPIO memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * The dedicated external GPIO's should always be listed in bank 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * so they are exported in the 0..31 range which is what users
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * expect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Do not reorder these banks as it will change the pin numbering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static const struct wmt_pinctrl_bank_registers vt8500_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	WMT_PINCTRL_BANK(NO_REG, 0x3C, 0x5C, 0x7C, NO_REG, NO_REG),	/* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	WMT_PINCTRL_BANK(0x00, 0x20, 0x40, 0x60, NO_REG, NO_REG),	/* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	WMT_PINCTRL_BANK(0x04, 0x24, 0x44, 0x64, NO_REG, NO_REG),	/* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	WMT_PINCTRL_BANK(0x08, 0x28, 0x48, 0x68, NO_REG, NO_REG),	/* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	WMT_PINCTRL_BANK(0x0C, 0x2C, 0x4C, 0x6C, NO_REG, NO_REG),	/* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	WMT_PINCTRL_BANK(0x10, 0x30, 0x50, 0x70, NO_REG, NO_REG),	/* 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	WMT_PINCTRL_BANK(0x14, 0x34, 0x54, 0x74, NO_REG, NO_REG),	/* 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* Please keep sorted by bank/bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define WMT_PIN_EXTGPIO0	WMT_PIN(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define WMT_PIN_EXTGPIO1	WMT_PIN(0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define WMT_PIN_EXTGPIO2	WMT_PIN(0, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WMT_PIN_EXTGPIO3	WMT_PIN(0, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WMT_PIN_EXTGPIO4	WMT_PIN(0, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WMT_PIN_EXTGPIO5	WMT_PIN(0, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WMT_PIN_EXTGPIO6	WMT_PIN(0, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WMT_PIN_EXTGPIO7	WMT_PIN(0, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WMT_PIN_EXTGPIO8	WMT_PIN(0, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WMT_PIN_UART0RTS	WMT_PIN(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WMT_PIN_UART0TXD	WMT_PIN(1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WMT_PIN_UART0CTS	WMT_PIN(1, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WMT_PIN_UART0RXD	WMT_PIN(1, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WMT_PIN_UART1RTS	WMT_PIN(1, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define WMT_PIN_UART1TXD	WMT_PIN(1, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define WMT_PIN_UART1CTS	WMT_PIN(1, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define WMT_PIN_UART1RXD	WMT_PIN(1, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define WMT_PIN_SPI0CLK		WMT_PIN(1, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define WMT_PIN_SPI0SS		WMT_PIN(1, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define WMT_PIN_SPI0MISO	WMT_PIN(1, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define WMT_PIN_SPI0MOSI	WMT_PIN(1, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define WMT_PIN_SPI1CLK		WMT_PIN(1, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define WMT_PIN_SPI1SS		WMT_PIN(1, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define WMT_PIN_SPI1MISO	WMT_PIN(1, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define WMT_PIN_SPI1MOSI	WMT_PIN(1, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define WMT_PIN_SPI2CLK		WMT_PIN(1, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define WMT_PIN_SPI2SS		WMT_PIN(1, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define WMT_PIN_SPI2MISO	WMT_PIN(1, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define WMT_PIN_SPI2MOSI	WMT_PIN(1, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define WMT_PIN_SDDATA0		WMT_PIN(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define WMT_PIN_SDDATA1		WMT_PIN(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define WMT_PIN_SDDATA2		WMT_PIN(2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define WMT_PIN_SDDATA3		WMT_PIN(2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define WMT_PIN_MMCDATA0	WMT_PIN(2, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define WMT_PIN_MMCDATA1	WMT_PIN(2, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define WMT_PIN_MMCDATA2	WMT_PIN(2, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define WMT_PIN_MMCDATA3	WMT_PIN(2, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define WMT_PIN_SDCLK		WMT_PIN(2, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define WMT_PIN_SDWP		WMT_PIN(2, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define WMT_PIN_SDCMD		WMT_PIN(2, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define WMT_PIN_MSDATA0		WMT_PIN(2, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define WMT_PIN_MSDATA1		WMT_PIN(2, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define WMT_PIN_MSDATA2		WMT_PIN(2, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define WMT_PIN_MSDATA3		WMT_PIN(2, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define WMT_PIN_MSCLK		WMT_PIN(2, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define WMT_PIN_MSBS		WMT_PIN(2, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define WMT_PIN_MSINS		WMT_PIN(2, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define WMT_PIN_I2C0SCL		WMT_PIN(2, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define WMT_PIN_I2C0SDA		WMT_PIN(2, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define WMT_PIN_I2C1SCL		WMT_PIN(2, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define WMT_PIN_I2C1SDA		WMT_PIN(2, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define WMT_PIN_MII0RXD0	WMT_PIN(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define WMT_PIN_MII0RXD1	WMT_PIN(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define WMT_PIN_MII0RXD2	WMT_PIN(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define WMT_PIN_MII0RXD3	WMT_PIN(3, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define WMT_PIN_MII0RXCLK	WMT_PIN(3, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define WMT_PIN_MII0RXDV	WMT_PIN(3, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define WMT_PIN_MII0RXERR	WMT_PIN(3, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define WMT_PIN_MII0PHYRST	WMT_PIN(3, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define WMT_PIN_MII0TXD0	WMT_PIN(3, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define WMT_PIN_MII0TXD1	WMT_PIN(3, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define WMT_PIN_MII0TXD2	WMT_PIN(3, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define WMT_PIN_MII0TXD3	WMT_PIN(3, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define WMT_PIN_MII0TXCLK	WMT_PIN(3, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define WMT_PIN_MII0TXEN	WMT_PIN(3, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WMT_PIN_MII0TXERR	WMT_PIN(3, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WMT_PIN_MII0PHYPD	WMT_PIN(3, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WMT_PIN_MII0COL		WMT_PIN(3, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WMT_PIN_MII0CRS		WMT_PIN(3, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WMT_PIN_MII0MDIO	WMT_PIN(3, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WMT_PIN_MII0MDC		WMT_PIN(3, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WMT_PIN_SEECS		WMT_PIN(3, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WMT_PIN_SEECK		WMT_PIN(3, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WMT_PIN_SEEDI		WMT_PIN(3, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WMT_PIN_SEEDO		WMT_PIN(3, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WMT_PIN_IDEDREQ0	WMT_PIN(3, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WMT_PIN_IDEDREQ1	WMT_PIN(3, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WMT_PIN_IDEIOW		WMT_PIN(3, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WMT_PIN_IDEIOR		WMT_PIN(3, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WMT_PIN_IDEDACK		WMT_PIN(3, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WMT_PIN_IDEIORDY	WMT_PIN(3, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WMT_PIN_IDEINTRQ	WMT_PIN(3, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WMT_PIN_VDIN0		WMT_PIN(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WMT_PIN_VDIN1		WMT_PIN(4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WMT_PIN_VDIN2		WMT_PIN(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WMT_PIN_VDIN3		WMT_PIN(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define WMT_PIN_VDIN4		WMT_PIN(4, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WMT_PIN_VDIN5		WMT_PIN(4, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define WMT_PIN_VDIN6		WMT_PIN(4, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define WMT_PIN_VDIN7		WMT_PIN(4, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define WMT_PIN_VDOUT0		WMT_PIN(4, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define WMT_PIN_VDOUT1		WMT_PIN(4, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define WMT_PIN_VDOUT2		WMT_PIN(4, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define WMT_PIN_VDOUT3		WMT_PIN(4, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define WMT_PIN_VDOUT4		WMT_PIN(4, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define WMT_PIN_VDOUT5		WMT_PIN(4, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define WMT_PIN_NANDCLE0	WMT_PIN(4, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define WMT_PIN_NANDCLE1	WMT_PIN(4, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define WMT_PIN_VDOUT6_7	WMT_PIN(4, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define WMT_PIN_VHSYNC		WMT_PIN(4, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define WMT_PIN_VVSYNC		WMT_PIN(4, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define WMT_PIN_TSDIN0		WMT_PIN(5, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define WMT_PIN_TSDIN1		WMT_PIN(5, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define WMT_PIN_TSDIN2		WMT_PIN(5, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define WMT_PIN_TSDIN3		WMT_PIN(5, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define WMT_PIN_TSDIN4		WMT_PIN(5, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define WMT_PIN_TSDIN5		WMT_PIN(5, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define WMT_PIN_TSDIN6		WMT_PIN(5, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define WMT_PIN_TSDIN7		WMT_PIN(5, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define WMT_PIN_TSSYNC		WMT_PIN(5, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define WMT_PIN_TSVALID		WMT_PIN(5, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define WMT_PIN_TSCLK		WMT_PIN(5, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define WMT_PIN_LCDD0		WMT_PIN(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define WMT_PIN_LCDD1		WMT_PIN(6, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define WMT_PIN_LCDD2		WMT_PIN(6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define WMT_PIN_LCDD3		WMT_PIN(6, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define WMT_PIN_LCDD4		WMT_PIN(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define WMT_PIN_LCDD5		WMT_PIN(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define WMT_PIN_LCDD6		WMT_PIN(6, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define WMT_PIN_LCDD7		WMT_PIN(6, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define WMT_PIN_LCDD8		WMT_PIN(6, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define WMT_PIN_LCDD9		WMT_PIN(6, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define WMT_PIN_LCDD10		WMT_PIN(6, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define WMT_PIN_LCDD11		WMT_PIN(6, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define WMT_PIN_LCDD12		WMT_PIN(6, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define WMT_PIN_LCDD13		WMT_PIN(6, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define WMT_PIN_LCDD14		WMT_PIN(6, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define WMT_PIN_LCDD15		WMT_PIN(6, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define WMT_PIN_LCDD16		WMT_PIN(6, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define WMT_PIN_LCDD17		WMT_PIN(6, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define WMT_PIN_LCDCLK		WMT_PIN(6, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define WMT_PIN_LCDDEN		WMT_PIN(6, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define WMT_PIN_LCDLINE		WMT_PIN(6, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define WMT_PIN_LCDFRM		WMT_PIN(6, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define WMT_PIN_LCDBIAS		WMT_PIN(6, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct pinctrl_pin_desc vt8500_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	PINCTRL_PIN(WMT_PIN_EXTGPIO8, "extgpio8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	PINCTRL_PIN(WMT_PIN_UART0RTS, "uart0_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	PINCTRL_PIN(WMT_PIN_UART0TXD, "uart0_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	PINCTRL_PIN(WMT_PIN_UART0CTS, "uart0_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	PINCTRL_PIN(WMT_PIN_UART0RXD, "uart0_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	PINCTRL_PIN(WMT_PIN_UART1RTS, "uart1_rts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	PINCTRL_PIN(WMT_PIN_UART1TXD, "uart1_txd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	PINCTRL_PIN(WMT_PIN_UART1CTS, "uart1_cts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	PINCTRL_PIN(WMT_PIN_UART1RXD, "uart1_rxd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	PINCTRL_PIN(WMT_PIN_SPI0CLK, "spi0_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	PINCTRL_PIN(WMT_PIN_SPI0SS, "spi0_ss"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	PINCTRL_PIN(WMT_PIN_SPI0MISO, "spi0_miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	PINCTRL_PIN(WMT_PIN_SPI0MOSI, "spi0_mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	PINCTRL_PIN(WMT_PIN_SPI1CLK, "spi1_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	PINCTRL_PIN(WMT_PIN_SPI1SS, "spi1_ss"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	PINCTRL_PIN(WMT_PIN_SPI1MISO, "spi1_miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	PINCTRL_PIN(WMT_PIN_SPI1MOSI, "spi1_mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	PINCTRL_PIN(WMT_PIN_SPI2CLK, "spi2_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	PINCTRL_PIN(WMT_PIN_SPI2SS, "spi2_ss"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	PINCTRL_PIN(WMT_PIN_SPI2MISO, "spi2_miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	PINCTRL_PIN(WMT_PIN_SPI2MOSI, "spi2_mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	PINCTRL_PIN(WMT_PIN_SDDATA0, "sd_data0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	PINCTRL_PIN(WMT_PIN_SDDATA1, "sd_data1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	PINCTRL_PIN(WMT_PIN_SDDATA2, "sd_data2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	PINCTRL_PIN(WMT_PIN_SDDATA3, "sd_data3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	PINCTRL_PIN(WMT_PIN_MMCDATA0, "mmc_data0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	PINCTRL_PIN(WMT_PIN_MMCDATA1, "mmc_data1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	PINCTRL_PIN(WMT_PIN_MMCDATA2, "mmc_data2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	PINCTRL_PIN(WMT_PIN_MMCDATA3, "mmc_data3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	PINCTRL_PIN(WMT_PIN_SDCLK, "sd_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	PINCTRL_PIN(WMT_PIN_SDWP, "sd_wp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	PINCTRL_PIN(WMT_PIN_SDCMD, "sd_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	PINCTRL_PIN(WMT_PIN_MSDATA0, "ms_data0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	PINCTRL_PIN(WMT_PIN_MSDATA1, "ms_data1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	PINCTRL_PIN(WMT_PIN_MSDATA2, "ms_data2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	PINCTRL_PIN(WMT_PIN_MSDATA3, "ms_data3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	PINCTRL_PIN(WMT_PIN_MSCLK, "ms_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	PINCTRL_PIN(WMT_PIN_MSBS, "ms_bs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	PINCTRL_PIN(WMT_PIN_MSINS, "ms_ins"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	PINCTRL_PIN(WMT_PIN_I2C0SCL, "i2c0_scl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	PINCTRL_PIN(WMT_PIN_I2C0SDA, "i2c0_sda"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	PINCTRL_PIN(WMT_PIN_I2C1SCL, "i2c1_scl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	PINCTRL_PIN(WMT_PIN_I2C1SDA, "i2c1_sda"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	PINCTRL_PIN(WMT_PIN_MII0RXD0, "mii0_rxd0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	PINCTRL_PIN(WMT_PIN_MII0RXD1, "mii0_rxd1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	PINCTRL_PIN(WMT_PIN_MII0RXD2, "mii0_rxd2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	PINCTRL_PIN(WMT_PIN_MII0RXD3, "mii0_rxd3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	PINCTRL_PIN(WMT_PIN_MII0RXCLK, "mii0_rxclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	PINCTRL_PIN(WMT_PIN_MII0RXDV, "mii0_rxdv"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	PINCTRL_PIN(WMT_PIN_MII0RXERR, "mii0_rxerr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	PINCTRL_PIN(WMT_PIN_MII0PHYRST, "mii0_phyrst"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	PINCTRL_PIN(WMT_PIN_MII0TXD0, "mii0_txd0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	PINCTRL_PIN(WMT_PIN_MII0TXD1, "mii0_txd1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	PINCTRL_PIN(WMT_PIN_MII0TXD2, "mii0_txd2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	PINCTRL_PIN(WMT_PIN_MII0TXD3, "mii0_txd3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	PINCTRL_PIN(WMT_PIN_MII0TXCLK, "mii0_txclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	PINCTRL_PIN(WMT_PIN_MII0TXEN, "mii0_txen"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	PINCTRL_PIN(WMT_PIN_MII0TXERR, "mii0_txerr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	PINCTRL_PIN(WMT_PIN_MII0PHYPD, "mii0_phypd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	PINCTRL_PIN(WMT_PIN_MII0COL, "mii0_col"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	PINCTRL_PIN(WMT_PIN_MII0CRS, "mii0_crs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	PINCTRL_PIN(WMT_PIN_MII0MDIO, "mii0_mdio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	PINCTRL_PIN(WMT_PIN_MII0MDC, "mii0_mdc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	PINCTRL_PIN(WMT_PIN_SEECS, "see_cs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	PINCTRL_PIN(WMT_PIN_SEECK, "see_ck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	PINCTRL_PIN(WMT_PIN_SEEDI, "see_di"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	PINCTRL_PIN(WMT_PIN_SEEDO, "see_do"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	PINCTRL_PIN(WMT_PIN_IDEDREQ0, "ide_dreq0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	PINCTRL_PIN(WMT_PIN_IDEDREQ1, "ide_dreq1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	PINCTRL_PIN(WMT_PIN_IDEIOW, "ide_iow"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	PINCTRL_PIN(WMT_PIN_IDEIOR, "ide_ior"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	PINCTRL_PIN(WMT_PIN_IDEDACK, "ide_dack"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	PINCTRL_PIN(WMT_PIN_IDEIORDY, "ide_iordy"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	PINCTRL_PIN(WMT_PIN_IDEINTRQ, "ide_intrq"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	PINCTRL_PIN(WMT_PIN_VDIN0, "vdin0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	PINCTRL_PIN(WMT_PIN_VDIN1, "vdin1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	PINCTRL_PIN(WMT_PIN_VDIN2, "vdin2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	PINCTRL_PIN(WMT_PIN_VDIN3, "vdin3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	PINCTRL_PIN(WMT_PIN_VDIN4, "vdin4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	PINCTRL_PIN(WMT_PIN_VDIN5, "vdin5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	PINCTRL_PIN(WMT_PIN_VDIN6, "vdin6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	PINCTRL_PIN(WMT_PIN_VDIN7, "vdin7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	PINCTRL_PIN(WMT_PIN_VDOUT5, "vdout5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	PINCTRL_PIN(WMT_PIN_NANDCLE0, "nand_cle0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	PINCTRL_PIN(WMT_PIN_NANDCLE1, "nand_cle1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	PINCTRL_PIN(WMT_PIN_VDOUT6_7, "vdout6_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	PINCTRL_PIN(WMT_PIN_VHSYNC, "vhsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	PINCTRL_PIN(WMT_PIN_VVSYNC, "vvsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	PINCTRL_PIN(WMT_PIN_TSDIN0, "tsdin0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	PINCTRL_PIN(WMT_PIN_TSDIN1, "tsdin1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	PINCTRL_PIN(WMT_PIN_TSDIN2, "tsdin2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	PINCTRL_PIN(WMT_PIN_TSDIN3, "tsdin3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	PINCTRL_PIN(WMT_PIN_TSDIN4, "tsdin4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	PINCTRL_PIN(WMT_PIN_TSDIN5, "tsdin5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	PINCTRL_PIN(WMT_PIN_TSDIN6, "tsdin6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	PINCTRL_PIN(WMT_PIN_TSDIN7, "tsdin7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	PINCTRL_PIN(WMT_PIN_TSSYNC, "tssync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	PINCTRL_PIN(WMT_PIN_TSVALID, "tsvalid"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	PINCTRL_PIN(WMT_PIN_TSCLK, "tsclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	PINCTRL_PIN(WMT_PIN_LCDD0, "lcd_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	PINCTRL_PIN(WMT_PIN_LCDD1, "lcd_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	PINCTRL_PIN(WMT_PIN_LCDD2, "lcd_d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	PINCTRL_PIN(WMT_PIN_LCDD3, "lcd_d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	PINCTRL_PIN(WMT_PIN_LCDD4, "lcd_d4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	PINCTRL_PIN(WMT_PIN_LCDD5, "lcd_d5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	PINCTRL_PIN(WMT_PIN_LCDD6, "lcd_d6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	PINCTRL_PIN(WMT_PIN_LCDD7, "lcd_d7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	PINCTRL_PIN(WMT_PIN_LCDD8, "lcd_d8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	PINCTRL_PIN(WMT_PIN_LCDD9, "lcd_d9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	PINCTRL_PIN(WMT_PIN_LCDD10, "lcd_d10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	PINCTRL_PIN(WMT_PIN_LCDD11, "lcd_d11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	PINCTRL_PIN(WMT_PIN_LCDD12, "lcd_d12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	PINCTRL_PIN(WMT_PIN_LCDD13, "lcd_d13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	PINCTRL_PIN(WMT_PIN_LCDD14, "lcd_d14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	PINCTRL_PIN(WMT_PIN_LCDD15, "lcd_d15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	PINCTRL_PIN(WMT_PIN_LCDD16, "lcd_d16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	PINCTRL_PIN(WMT_PIN_LCDD17, "lcd_d17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	PINCTRL_PIN(WMT_PIN_LCDCLK, "lcd_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	PINCTRL_PIN(WMT_PIN_LCDDEN, "lcd_den"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	PINCTRL_PIN(WMT_PIN_LCDLINE, "lcd_line"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	PINCTRL_PIN(WMT_PIN_LCDFRM, "lcd_frm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	PINCTRL_PIN(WMT_PIN_LCDBIAS, "lcd_bias"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Order of these names must match the above list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const char * const vt8500_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	"extgpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	"extgpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	"extgpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	"extgpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	"extgpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	"extgpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	"extgpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	"extgpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	"extgpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	"uart0_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	"uart0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	"uart0_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	"uart0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	"uart1_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	"uart1_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	"uart1_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	"uart1_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	"spi0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	"spi0_ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	"spi0_miso",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	"spi0_mosi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	"spi1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	"spi1_ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	"spi1_miso",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	"spi1_mosi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	"spi2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	"spi2_ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	"spi2_miso",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	"spi2_mosi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	"sd_data0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	"sd_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	"sd_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	"sd_data3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	"mmc_data0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	"mmc_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	"mmc_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	"mmc_data3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	"sd_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	"sd_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	"sd_cmd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	"ms_data0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	"ms_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	"ms_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	"ms_data3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	"ms_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	"ms_bs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	"ms_ins",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	"i2c0_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	"i2c0_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	"i2c1_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	"i2c1_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	"mii0_rxd0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	"mii0_rxd1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	"mii0_rxd2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	"mii0_rxd3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	"mii0_rxclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	"mii0_rxdv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	"mii0_rxerr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	"mii0_phyrst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	"mii0_txd0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	"mii0_txd1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	"mii0_txd2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	"mii0_txd3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	"mii0_txclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	"mii0_txen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	"mii0_txerr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	"mii0_phypd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	"mii0_col",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	"mii0_crs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	"mii0_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	"mii0_mdc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	"see_cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	"see_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	"see_di",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	"see_do",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	"ide_dreq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	"ide_dreq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	"ide_iow",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	"ide_ior",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	"ide_dack",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	"ide_iordy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	"ide_intrq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	"vdin0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	"vdin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	"vdin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	"vdin3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	"vdin4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	"vdin5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	"vdin6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	"vdin7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	"vdout0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	"vdout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	"vdout2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	"vdout3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	"vdout4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	"vdout5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	"nand_cle0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	"nand_cle1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	"vdout6_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	"vhsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	"vvsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	"tsdin0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	"tsdin1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	"tsdin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	"tsdin3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	"tsdin4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	"tsdin5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	"tsdin6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	"tsdin7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	"tssync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	"tsvalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	"tsclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	"lcd_d0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	"lcd_d1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	"lcd_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	"lcd_d3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	"lcd_d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	"lcd_d5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	"lcd_d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	"lcd_d7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	"lcd_d8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	"lcd_d9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	"lcd_d10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	"lcd_d11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	"lcd_d12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	"lcd_d13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	"lcd_d14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	"lcd_d15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	"lcd_d16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	"lcd_d17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	"lcd_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	"lcd_den",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	"lcd_line",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	"lcd_frm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	"lcd_bias",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int vt8500_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	struct wmt_pinctrl_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	data->banks = vt8500_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	data->nbanks = ARRAY_SIZE(vt8500_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	data->pins = vt8500_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	data->npins = ARRAY_SIZE(vt8500_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	data->groups = vt8500_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	data->ngroups = ARRAY_SIZE(vt8500_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	return wmt_pinctrl_probe(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const struct of_device_id wmt_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	{ .compatible = "via,vt8500-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct platform_driver wmt_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.probe	= vt8500_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		.name	= "pinctrl-vt8500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		.of_match_table	= wmt_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) builtin_platform_driver(wmt_pinctrl_driver);