^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 TOSHIBA CORPORATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pinctrl-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define tmpv7700_MAGIC_NUM 0x4932f70e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_KEY_CTRL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_KEY_CMD 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_PINMUX1 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_PINMUX2 0x3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_PINMUX3 0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_PINMUX4 0x300c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_PINMUX5 0x3010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_IOSET 0x3014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_IO_VSEL 0x3018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_IO_DSEL1 0x301c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_IO_DSEL2 0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_IO_DSEL3 0x3024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_IO_DSEL4 0x3028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_IO_DSEL5 0x302c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_IO_DSEL6 0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_IO_DSEL7 0x3034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_IO_DSEL8 0x3038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_IO_PUDE1 0x303c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_IO_PUDE2 0x3040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_IO_PUDSEL1 0x3044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_IO_PUDSEL2 0x3048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* PIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const struct visconti_desc_pin pins_tmpv7700[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) VISCONTI_PIN(PINCTRL_PIN(0, "gpio0"), REG_IO_DSEL4, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) REG_IO_PUDE1, REG_IO_PUDSEL1, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) VISCONTI_PIN(PINCTRL_PIN(1, "gpio1"), REG_IO_DSEL4, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) REG_IO_PUDE1, REG_IO_PUDSEL1, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) VISCONTI_PIN(PINCTRL_PIN(2, "gpio2"), REG_IO_DSEL5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) REG_IO_PUDE2, REG_IO_PUDSEL2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) VISCONTI_PIN(PINCTRL_PIN(3, "gpio3"), REG_IO_DSEL5, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) REG_IO_PUDE2, REG_IO_PUDSEL2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) VISCONTI_PIN(PINCTRL_PIN(4, "gpio4"), REG_IO_DSEL5, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) REG_IO_PUDE2, REG_IO_PUDSEL2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) VISCONTI_PIN(PINCTRL_PIN(5, "gpio5"), REG_IO_DSEL5, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) REG_IO_PUDE2, REG_IO_PUDSEL2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) VISCONTI_PIN(PINCTRL_PIN(6, "gpio6"), REG_IO_DSEL5, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) REG_IO_PUDE2, REG_IO_PUDSEL2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) VISCONTI_PIN(PINCTRL_PIN(7, "gpio7"), REG_IO_DSEL5, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) REG_IO_PUDE2, REG_IO_PUDSEL2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) VISCONTI_PIN(PINCTRL_PIN(8, "gpio8"), REG_IO_DSEL5, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) REG_IO_PUDE2, REG_IO_PUDSEL2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) VISCONTI_PIN(PINCTRL_PIN(9, "gpio9"), REG_IO_DSEL5, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) REG_IO_PUDE2, REG_IO_PUDSEL2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) VISCONTI_PIN(PINCTRL_PIN(10, "gpio10"), REG_IO_DSEL6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) REG_IO_PUDE2, REG_IO_PUDSEL2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) VISCONTI_PIN(PINCTRL_PIN(11, "gpio11"), REG_IO_DSEL6, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) REG_IO_PUDE2, REG_IO_PUDSEL2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) VISCONTI_PIN(PINCTRL_PIN(12, "gpio12"), REG_IO_DSEL6, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) REG_IO_PUDE2, REG_IO_PUDSEL2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) VISCONTI_PIN(PINCTRL_PIN(13, "gpio13"), REG_IO_DSEL6, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) REG_IO_PUDE2, REG_IO_PUDSEL2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) VISCONTI_PIN(PINCTRL_PIN(14, "gpio14"), REG_IO_DSEL6, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) REG_IO_PUDE2, REG_IO_PUDSEL2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) VISCONTI_PIN(PINCTRL_PIN(15, "gpio15"), REG_IO_DSEL6, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) REG_IO_PUDE2, REG_IO_PUDSEL2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) VISCONTI_PIN(PINCTRL_PIN(16, "gpio16"), REG_IO_DSEL6, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) REG_IO_PUDE2, REG_IO_PUDSEL2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) VISCONTI_PIN(PINCTRL_PIN(17, "gpio17"), REG_IO_DSEL6, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) REG_IO_PUDE2, REG_IO_PUDSEL2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) VISCONTI_PIN(PINCTRL_PIN(18, "gpio18"), REG_IO_DSEL7, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) REG_IO_PUDE2, REG_IO_PUDSEL2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) VISCONTI_PIN(PINCTRL_PIN(19, "gpio19"), REG_IO_DSEL7, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) REG_IO_PUDE2, REG_IO_PUDSEL2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) VISCONTI_PIN(PINCTRL_PIN(20, "gpio20"), REG_IO_DSEL7, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) REG_IO_PUDE2, REG_IO_PUDSEL2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) VISCONTI_PIN(PINCTRL_PIN(21, "gpio21"), REG_IO_DSEL7, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) REG_IO_PUDE2, REG_IO_PUDSEL2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) VISCONTI_PIN(PINCTRL_PIN(22, "gpio22"), REG_IO_DSEL7, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) REG_IO_PUDE2, REG_IO_PUDSEL2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) VISCONTI_PIN(PINCTRL_PIN(23, "gpio23"), REG_IO_DSEL7, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) REG_IO_PUDE2, REG_IO_PUDSEL2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) VISCONTI_PIN(PINCTRL_PIN(24, "gpio24"), REG_IO_DSEL7, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) REG_IO_PUDE2, REG_IO_PUDSEL2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) VISCONTI_PIN(PINCTRL_PIN(25, "gpio25"), REG_IO_DSEL7, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) REG_IO_PUDE2, REG_IO_PUDSEL2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) VISCONTI_PIN(PINCTRL_PIN(26, "gpio26"), REG_IO_DSEL8, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) REG_IO_PUDE2, REG_IO_PUDSEL2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) VISCONTI_PIN(PINCTRL_PIN(27, "gpio27"), REG_IO_DSEL8, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) REG_IO_PUDE2, REG_IO_PUDSEL2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) VISCONTI_PIN(PINCTRL_PIN(28, "gpio28"), REG_IO_DSEL8, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) REG_IO_PUDE2, REG_IO_PUDSEL2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) VISCONTI_PIN(PINCTRL_PIN(29, "gpio29"), REG_IO_DSEL4, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) REG_IO_PUDE1, REG_IO_PUDSEL1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) VISCONTI_PIN(PINCTRL_PIN(30, "gpio30"), REG_IO_DSEL4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) REG_IO_PUDE1, REG_IO_PUDSEL1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) VISCONTI_PIN(PINCTRL_PIN(31, "gpio31"), REG_IO_DSEL4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) REG_IO_PUDE1, REG_IO_PUDSEL1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) VISCONTI_PIN(PINCTRL_PIN(32, "spi_sck"), REG_IO_DSEL4, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) REG_IO_PUDE1, REG_IO_PUDSEL1, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) VISCONTI_PIN(PINCTRL_PIN(33, "spi_sdo"), REG_IO_DSEL4, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) REG_IO_PUDE1, REG_IO_PUDSEL1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) VISCONTI_PIN(PINCTRL_PIN(34, "spi_sdi"), REG_IO_DSEL4, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) REG_IO_PUDE1, REG_IO_PUDSEL1, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) VISCONTI_PINS(i2c0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) VISCONTI_PINS(i2c1, 2, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) VISCONTI_PINS(i2c2, 12, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) VISCONTI_PINS(i2c3, 14, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) VISCONTI_PINS(i2c4, 16, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) VISCONTI_PINS(i2c5, 18, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) VISCONTI_PINS(i2c6, 33, 34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) VISCONTI_PINS(i2c7, 29, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) VISCONTI_PINS(i2c8, 30, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) VISCONTI_PINS(spi0_cs0, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) VISCONTI_PINS(spi0_cs1, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) VISCONTI_PINS(spi0_cs2, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) VISCONTI_PINS(spi1_cs, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) VISCONTI_PINS(spi2_cs, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) VISCONTI_PINS(spi3_cs, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) VISCONTI_PINS(spi4_cs, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) VISCONTI_PINS(spi5_cs, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) VISCONTI_PINS(spi6_cs, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) VISCONTI_PINS(spi0, 32, 33, 34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) VISCONTI_PINS(spi1, 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) VISCONTI_PINS(spi2, 4, 5, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) VISCONTI_PINS(spi3, 8, 9, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) VISCONTI_PINS(spi4, 12, 13, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) VISCONTI_PINS(spi5, 16, 17, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) VISCONTI_PINS(spi6, 24, 25, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) VISCONTI_PINS(uart0, 4, 5, 6, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) VISCONTI_PINS(uart1, 8, 9, 10, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) VISCONTI_PINS(uart2, 12, 13, 14, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) VISCONTI_PINS(uart3, 16, 17, 18, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) VISCONTI_PINS(pwm0_gpio4, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) VISCONTI_PINS(pwm1_gpio5, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) VISCONTI_PINS(pwm2_gpio6, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) VISCONTI_PINS(pwm3_gpio7, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) VISCONTI_PINS(pwm0_gpio8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) VISCONTI_PINS(pwm1_gpio9, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) VISCONTI_PINS(pwm2_gpio10, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) VISCONTI_PINS(pwm3_gpio11, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) VISCONTI_PINS(pwm0_gpio12, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) VISCONTI_PINS(pwm1_gpio13, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) VISCONTI_PINS(pwm2_gpio14, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) VISCONTI_PINS(pwm3_gpio15, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) VISCONTI_PINS(pwm0_gpio16, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) VISCONTI_PINS(pwm1_gpio17, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) VISCONTI_PINS(pwm2_gpio18, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) VISCONTI_PINS(pwm3_gpio19, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) VISCONTI_PINS(pcmif_out, 20, 21, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) VISCONTI_PINS(pcmif_in, 24, 25, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct visconti_pin_group groups_tmpv7700[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) VISCONTI_PIN_GROUP(i2c0, REG_PINMUX2, GENMASK(7, 0), 0x00000022),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) VISCONTI_PIN_GROUP(i2c1, REG_PINMUX2, GENMASK(15, 8), 0x00002200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) VISCONTI_PIN_GROUP(i2c2, REG_PINMUX3, GENMASK(23, 16), 0x00770000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) VISCONTI_PIN_GROUP(i2c3, REG_PINMUX3, GENMASK(31, 24), 0x77000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) VISCONTI_PIN_GROUP(i2c4, REG_PINMUX4, GENMASK(7, 0), 0x00000077),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) VISCONTI_PIN_GROUP(i2c5, REG_PINMUX4, GENMASK(15, 8), 0x00007700),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) VISCONTI_PIN_GROUP(i2c6, REG_PINMUX1, GENMASK(3, 0), 0x0000002),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) VISCONTI_PIN_GROUP(i2c7, REG_PINMUX5, GENMASK(23, 20), 0x00200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) VISCONTI_PIN_GROUP(i2c8, REG_PINMUX5, GENMASK(31, 24), 0x22000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) VISCONTI_PIN_GROUP(spi0_cs0, REG_PINMUX5, GENMASK(23, 20), 0x00100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) VISCONTI_PIN_GROUP(spi0_cs1, REG_PINMUX5, GENMASK(27, 24), 0x01000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) VISCONTI_PIN_GROUP(spi0_cs2, REG_PINMUX5, GENMASK(31, 28), 0x10000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) VISCONTI_PIN_GROUP(spi1_cs, REG_PINMUX2, GENMASK(15, 12), 0x00001000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) VISCONTI_PIN_GROUP(spi2_cs, REG_PINMUX2, GENMASK(31, 28), 0x10000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) VISCONTI_PIN_GROUP(spi3_cs, REG_PINMUX3, GENMASK(15, 12), 0x00001000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) VISCONTI_PIN_GROUP(spi4_cs, REG_PINMUX4, GENMASK(31, 28), 0x10000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) VISCONTI_PIN_GROUP(spi5_cs, REG_PINMUX4, GENMASK(15, 12), 0x00001000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) VISCONTI_PIN_GROUP(spi6_cs, REG_PINMUX5, GENMASK(15, 12), 0x00001000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) VISCONTI_PIN_GROUP(spi0, REG_PINMUX1, GENMASK(3, 0), 0x00000001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) VISCONTI_PIN_GROUP(spi1, REG_PINMUX2, GENMASK(11, 0), 0x00000111),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) VISCONTI_PIN_GROUP(spi2, REG_PINMUX2, GENMASK(27, 16), 0x01110000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) VISCONTI_PIN_GROUP(spi3, REG_PINMUX3, GENMASK(11, 0), 0x00000111),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) VISCONTI_PIN_GROUP(spi4, REG_PINMUX3, GENMASK(27, 16), 0x01110000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) VISCONTI_PIN_GROUP(spi5, REG_PINMUX4, GENMASK(11, 0), 0x00000111),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) VISCONTI_PIN_GROUP(spi6, REG_PINMUX5, GENMASK(11, 0), 0x00000111),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) VISCONTI_PIN_GROUP(uart0, REG_PINMUX2, GENMASK(31, 16), 0x22220000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) VISCONTI_PIN_GROUP(uart1, REG_PINMUX3, GENMASK(15, 0), 0x00002222),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) VISCONTI_PIN_GROUP(uart2, REG_PINMUX3, GENMASK(31, 16), 0x22220000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) VISCONTI_PIN_GROUP(uart3, REG_PINMUX4, GENMASK(15, 0), 0x00002222),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) VISCONTI_PIN_GROUP(pwm0_gpio4, REG_PINMUX2, GENMASK(19, 16), 0x00050000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) VISCONTI_PIN_GROUP(pwm1_gpio5, REG_PINMUX2, GENMASK(23, 20), 0x00500000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) VISCONTI_PIN_GROUP(pwm2_gpio6, REG_PINMUX2, GENMASK(27, 24), 0x05000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) VISCONTI_PIN_GROUP(pwm3_gpio7, REG_PINMUX2, GENMASK(31, 28), 0x50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) VISCONTI_PIN_GROUP(pwm0_gpio8, REG_PINMUX3, GENMASK(3, 0), 0x00000005),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) VISCONTI_PIN_GROUP(pwm1_gpio9, REG_PINMUX3, GENMASK(7, 4), 0x00000050),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) VISCONTI_PIN_GROUP(pwm2_gpio10, REG_PINMUX3, GENMASK(11, 8), 0x00000500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) VISCONTI_PIN_GROUP(pwm3_gpio11, REG_PINMUX3, GENMASK(15, 12), 0x00005000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) VISCONTI_PIN_GROUP(pwm0_gpio12, REG_PINMUX3, GENMASK(19, 16), 0x00050000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) VISCONTI_PIN_GROUP(pwm1_gpio13, REG_PINMUX3, GENMASK(23, 20), 0x00500000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) VISCONTI_PIN_GROUP(pwm2_gpio14, REG_PINMUX3, GENMASK(27, 24), 0x05000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) VISCONTI_PIN_GROUP(pwm3_gpio15, REG_PINMUX3, GENMASK(31, 28), 0x50000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) VISCONTI_PIN_GROUP(pwm0_gpio16, REG_PINMUX4, GENMASK(3, 0), 0x00000005),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) VISCONTI_PIN_GROUP(pwm1_gpio17, REG_PINMUX4, GENMASK(7, 4), 0x00000050),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) VISCONTI_PIN_GROUP(pwm2_gpio18, REG_PINMUX4, GENMASK(11, 8), 0x00000500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) VISCONTI_PIN_GROUP(pwm3_gpio19, REG_PINMUX4, GENMASK(15, 12), 0x00005000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) VISCONTI_PIN_GROUP(pcmif_out, REG_PINMUX4, GENMASK(27, 16), 0x01110000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) VISCONTI_PIN_GROUP(pcmif_in, REG_PINMUX5, GENMASK(11, 0), 0x00000222),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) VISCONTI_GROUPS(i2c0, "i2c0_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) VISCONTI_GROUPS(i2c1, "i2c1_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) VISCONTI_GROUPS(i2c2, "i2c2_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) VISCONTI_GROUPS(i2c3, "i2c3_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) VISCONTI_GROUPS(i2c4, "i2c4_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) VISCONTI_GROUPS(i2c5, "i2c5_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) VISCONTI_GROUPS(i2c6, "i2c6_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) VISCONTI_GROUPS(i2c7, "i2c7_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) VISCONTI_GROUPS(i2c8, "i2c8_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) VISCONTI_GROUPS(spi0, "spi0_grp", "spi0_cs0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "spi0_cs1_grp", "spi0_cs2_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) VISCONTI_GROUPS(spi1, "spi1_grp", "spi1_cs_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) VISCONTI_GROUPS(spi2, "spi2_grp", "spi2_cs_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) VISCONTI_GROUPS(spi3, "spi3_grp", "spi3_cs_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) VISCONTI_GROUPS(spi4, "spi4_grp", "spi4_cs_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) VISCONTI_GROUPS(spi5, "spi5_grp", "spi5_cs_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) VISCONTI_GROUPS(spi6, "spi6_grp", "spi6_cs_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) VISCONTI_GROUPS(uart0, "uart0_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) VISCONTI_GROUPS(uart1, "uart1_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) VISCONTI_GROUPS(uart2, "uart2_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) VISCONTI_GROUPS(uart3, "uart3_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) VISCONTI_GROUPS(pwm, "pwm0_gpio4_grp", "pwm0_gpio8_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "pwm0_gpio12_grp", "pwm0_gpio16_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "pwm1_gpio5_grp", "pwm1_gpio9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "pwm1_gpio13_grp", "pwm1_gpio17_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "pwm2_gpio6_grp", "pwm2_gpio10_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "pwm2_gpio14_grp", "pwm2_gpio18_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "pwm3_gpio7_grp", "pwm3_gpio11_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "pwm3_gpio15_grp", "pwm3_gpio19_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) VISCONTI_GROUPS(pcmif_out, "pcmif_out_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) VISCONTI_GROUPS(pcmif_in, "pcmif_in_grp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct visconti_pin_function functions_tmpv7700[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) VISCONTI_PIN_FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) VISCONTI_PIN_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) VISCONTI_PIN_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) VISCONTI_PIN_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) VISCONTI_PIN_FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) VISCONTI_PIN_FUNCTION(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) VISCONTI_PIN_FUNCTION(i2c6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) VISCONTI_PIN_FUNCTION(i2c7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) VISCONTI_PIN_FUNCTION(i2c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) VISCONTI_PIN_FUNCTION(spi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) VISCONTI_PIN_FUNCTION(spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) VISCONTI_PIN_FUNCTION(spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) VISCONTI_PIN_FUNCTION(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) VISCONTI_PIN_FUNCTION(spi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) VISCONTI_PIN_FUNCTION(spi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) VISCONTI_PIN_FUNCTION(spi6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) VISCONTI_PIN_FUNCTION(uart0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) VISCONTI_PIN_FUNCTION(uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) VISCONTI_PIN_FUNCTION(uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) VISCONTI_PIN_FUNCTION(uart3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) VISCONTI_PIN_FUNCTION(pwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) VISCONTI_PIN_FUNCTION(pcmif_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) VISCONTI_PIN_FUNCTION(pcmif_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* GPIO MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define tmpv7700_GPIO_MUX(off, msk) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .offset = off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .mask = msk, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .val = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct visconti_mux gpio_mux_tmpv7700[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(15, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(19, 16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(23, 20)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(27, 24)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(31, 28)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(15, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(19, 16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(23, 20)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(27, 24)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(31, 28)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(15, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(19, 16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(23, 20)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(27, 24)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(31, 28)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(7, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(11, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(15, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(19, 16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(23, 20)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(27, 24)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(31, 28)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void tmpv7700_pinctrl_unlock(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel(1, base + REG_KEY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writel(tmpv7700_MAGIC_NUM, base + REG_KEY_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* chip dependent data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct visconti_pinctrl_devdata tmpv7700_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .pins = pins_tmpv7700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .nr_pins = ARRAY_SIZE(pins_tmpv7700),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .groups = groups_tmpv7700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .nr_groups = ARRAY_SIZE(groups_tmpv7700),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .functions = functions_tmpv7700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .nr_functions = ARRAY_SIZE(functions_tmpv7700),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .gpio_mux = gpio_mux_tmpv7700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .unlock = tmpv7700_pinctrl_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int tmpv7700_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return visconti_pinctrl_probe(pdev, &tmpv7700_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct of_device_id tmpv7700_pctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { .compatible = "toshiba,tmpv7708-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static struct platform_driver tmpv7700_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .probe = tmpv7700_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .name = "tmpv7700-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .of_match_table = tmpv7700_pctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int __init tmpv7700_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return platform_driver_register(&tmpv7700_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) arch_initcall(tmpv7700_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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