^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 TOSHIBA CORPORATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DSEL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct visconti_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct pinctrl_desc pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) const struct visconti_pinctrl_devdata *devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) spinlock_t lock; /* protect pinctrl register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* pinconf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int visconti_pin_config_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int _pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const struct visconti_desc_pin *pin = &priv->devdata->pins[_pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int val, set_val, pude_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) dev_dbg(priv->dev, "%s: pin = %d (%s)\n", __func__, _pin, pin->pin.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) set_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pude_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) set_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* update pudsel setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = readl(priv->base + pin->pudsel_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) val &= ~BIT(pin->pud_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) val |= set_val << pin->pud_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel(val, priv->base + pin->pudsel_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pude_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* update pude setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val = readl(priv->base + pin->pude_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val &= ~BIT(pin->pud_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val |= pude_val << pin->pud_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel(val, priv->base + pin->pude_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dev_dbg(priv->dev, "BIAS(%d): off = 0x%x val = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) param, pin->pude_offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dev_dbg(priv->dev, "DRV_STR arg = %d\n", arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * I/O drive capacity setting:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 2mA: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 4mA: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 8mA: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * 16mA: 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 24mA: 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * 32mA: 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) set_val = DIV_ROUND_CLOSEST(arg, 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* update drive setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val = readl(priv->base + pin->dsel_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val &= ~(DSEL_MASK << pin->dsel_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val |= set_val << pin->dsel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel(val, priv->base + pin->dsel_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int visconti_pin_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pins = priv->devdata->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) num_pins = priv->devdata->groups[selector].nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_dbg(priv->dev, "%s: select = %d, n_pin = %d, n_config = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __func__, selector, num_pins, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) for (i = 0; i < num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = visconti_pin_config_set(pctldev, pins[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct pinconf_ops visconti_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .pin_config_set = visconti_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .pin_config_group_set = visconti_pin_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .pin_config_config_dbg_show = pinconf_generic_dump_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int visconti_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return priv->devdata->nr_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const char *visconti_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return priv->devdata->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int visconti_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *pins = priv->devdata->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *num_pins = priv->devdata->groups[selector].nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct pinctrl_ops visconti_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .get_groups_count = visconti_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .get_group_name = visconti_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .get_group_pins = visconti_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* pinmux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int visconti_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return priv->devdata->nr_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const char *visconti_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return priv->devdata->functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int visconti_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *groups = priv->devdata->functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *num_groups = priv->devdata->functions[selector].nr_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int visconti_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int function, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) const struct visconti_pin_function *func = &priv->devdata->functions[function];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const struct visconti_pin_group *grp = &priv->devdata->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const struct visconti_mux *mux = &grp->mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_dbg(priv->dev, "%s: function = %d(%s) group = %d(%s)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) function, func->name, group, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* update mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val = readl(priv->base + mux->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val &= ~mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val |= mux->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel(val, priv->base + mux->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_dbg(priv->dev, "[%x]: 0x%x\n", mux->offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct pinmux_ops visconti_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .get_functions_count = visconti_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .get_function_name = visconti_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .get_function_groups = visconti_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .set_mux = visconti_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int visconti_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) const struct visconti_pinctrl_devdata *devdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct visconti_pinctrl *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) priv->devdata = devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (IS_ERR(priv->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_err(dev, "unable to map I/O space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pins = devm_kcalloc(dev, devdata->nr_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) sizeof(*pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < devdata->nr_pins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pins[i] = devdata->pins[i].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) priv->pctl_desc.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) priv->pctl_desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) priv->pctl_desc.pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) priv->pctl_desc.npins = devdata->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) priv->pctl_desc.confops = &visconti_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) priv->pctl_desc.pctlops = &visconti_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) priv->pctl_desc.pmxops = &visconti_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = devm_pinctrl_register_and_init(dev, &priv->pctl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) priv, &priv->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(dev, "couldn't register pinctrl: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (devdata->unlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) devdata->unlock(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return pinctrl_enable(priv->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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