^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015-2017 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __PINCTRL_UNIPHIER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __PINCTRL_UNIPHIER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/build_bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* input enable control register bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define UNIPHIER_PIN_IECTRL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UNIPHIER_PIN_IECTRL_BITS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* drive strength control register number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) (UNIPHIER_PIN_IECTRL_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UNIPHIER_PIN_DRVCTRL_BITS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* drive control type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (UNIPHIER_PIN_DRVCTRL_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UNIPHIER_PIN_DRV_TYPE_BITS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UNIPHIER_PIN_DRV_TYPE_MASK ((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* pull-up / pull-down register number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (UNIPHIER_PIN_DRV_TYPE_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UNIPHIER_PIN_PUPDCTRL_BITS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* direction of pull register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) (UNIPHIER_PIN_PUPDCTRL_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UNIPHIER_PIN_PULL_DIR_BITS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #error "unable to pack pin attributes."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UNIPHIER_PIN_IECTRL_EXIST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* drive control type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum uniphier_pin_drv_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* direction of pull register (no pin supports bi-directional pull biasing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum uniphier_pin_pull_dir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) UNIPHIER_PIN_PULL_NONE, /* no pull register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define UNIPHIER_PIN_IECTRL(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define UNIPHIER_PIN_DRVCTRL(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define UNIPHIER_PIN_DRV_TYPE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define UNIPHIER_PIN_PUPDCTRL(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) (((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UNIPHIER_PIN_PULL_DIR(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) (UNIPHIER_PIN_IECTRL(iectrl) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) UNIPHIER_PIN_DRVCTRL(drvctrl) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) UNIPHIER_PIN_DRV_TYPE(drv_type) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) UNIPHIER_PIN_PULL_DIR(pull_dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) UNIPHIER_PIN_IECTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) UNIPHIER_PIN_DRVCTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline unsigned int uniphier_pin_get_drv_type(void *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) UNIPHIER_PIN_DRV_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) UNIPHIER_PIN_PUPDCTRL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) UNIPHIER_PIN_PULL_DIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct uniphier_pinctrl_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const int *muxvals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct uniphier_pinmux_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct uniphier_pinctrl_socdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const struct uniphier_pinctrl_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int groups_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct uniphier_pinmux_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int functions_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int (*get_gpio_muxval)(unsigned int pin, unsigned int gpio_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .number = a, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define __UNIPHIER_PINCTRL_GROUP(grp, mux) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .name = #grp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .pins = grp##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .num_pins = ARRAY_SIZE(grp##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .muxvals = mux, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define UNIPHIER_PINCTRL_GROUP(grp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __UNIPHIER_PINCTRL_GROUP(grp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) grp##_muxvals + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ARRAY_SIZE(grp##_muxvals)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define UNIPHIER_PINCTRL_GROUP_GPIO(grp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __UNIPHIER_PINCTRL_GROUP(grp, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define UNIPHIER_PINMUX_FUNCTION(func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = #func, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .groups = func##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .num_groups = ARRAY_SIZE(func##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int uniphier_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) const struct uniphier_pinctrl_socdata *socdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) extern const struct dev_pm_ops uniphier_pinctrl_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif /* __PINCTRL_UNIPHIER_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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