^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pinctrl data for the NVIDIA Tegra30 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Stephen Warren <swarren@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-tegra.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Most pins affected by the pinmux can also be GPIOs. Define these first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * These must match how the GPIO driver names/numbers its pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define _GPIO(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA_PIN_SDMMC3_DAT5_PD0 _GPIO(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA_PIN_SDMMC3_DAT4_PD1 _GPIO(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA_PIN_LCD_DC1_PD2 _GPIO(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA_PIN_SDMMC3_DAT6_PD3 _GPIO(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA_PIN_SDMMC3_DAT7_PD4 _GPIO(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA_PIN_GMI_DQS_PI2 _GPIO(66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TEGRA_PIN_PU0 _GPIO(160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TEGRA_PIN_PU1 _GPIO(161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA_PIN_PU2 _GPIO(162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA_PIN_PU3 _GPIO(163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA_PIN_PU4 _GPIO(164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TEGRA_PIN_PU5 _GPIO(165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TEGRA_PIN_PU6 _GPIO(166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA_PIN_PV0 _GPIO(168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TEGRA_PIN_PV1 _GPIO(169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA_PIN_PV2 _GPIO(170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TEGRA_PIN_PV3 _GPIO(171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA_PIN_CRT_HSYNC_PV6 _GPIO(174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA_PIN_CRT_VSYNC_PV7 _GPIO(175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TEGRA_PIN_PBB0 _GPIO(216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TEGRA_PIN_PBB3 _GPIO(219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TEGRA_PIN_PBB4 _GPIO(220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TEGRA_PIN_PBB5 _GPIO(221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA_PIN_PBB6 _GPIO(222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TEGRA_PIN_PBB7 _GPIO(223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TEGRA_PIN_PCC1 _GPIO(225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TEGRA_PIN_PCC2 _GPIO(226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TEGRA_PIN_SDMMC4_RST_N_PCC3 _GPIO(227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TEGRA_PIN_PEX_L2_RST_N_PCC6 _GPIO(230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7 _GPIO(231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TEGRA_PIN_PEX_L0_PRSNT_N_PDD0 _GPIO(232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEGRA_PIN_PEX_L1_PRSNT_N_PDD4 _GPIO(236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TEGRA_PIN_PEX_L2_PRSNT_N_PDD7 _GPIO(239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEGRA_PIN_PEE4 _GPIO(244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TEGRA_PIN_PEE5 _GPIO(245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEGRA_PIN_PEE6 _GPIO(246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TEGRA_PIN_PEE7 _GPIO(247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* All non-GPIO pins follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define NUM_GPIOS (TEGRA_PIN_PEE7 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define _PIN(offset) (NUM_GPIOS + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Non-GPIO pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TEGRA_PIN_CLK_32K_IN _PIN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TEGRA_PIN_CORE_PWR_REQ _PIN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TEGRA_PIN_CPU_PWR_REQ _PIN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TEGRA_PIN_JTAG_TCK _PIN(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TEGRA_PIN_JTAG_TDI _PIN(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TEGRA_PIN_JTAG_TDO _PIN(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TEGRA_PIN_JTAG_TMS _PIN(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TEGRA_PIN_JTAG_TRST_N _PIN(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TEGRA_PIN_OWR _PIN(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TEGRA_PIN_PWR_INT_N _PIN(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TEGRA_PIN_SYS_RESET_N _PIN(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TEGRA_PIN_TEST_MODE_EN _PIN(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct pinctrl_pin_desc tegra30_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT5_PD0, "SDMMC3_DAT5 PD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT4_PD1, "SDMMC3_DAT4 PD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PD2, "LCD_DC1 PD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT6_PD3, "SDMMC3_DAT6 PD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT7_PD4, "SDMMC3_DAT7 PD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINCTRL_PIN(TEGRA_PIN_GMI_DQS_PI2, "GMI_DQS PI2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VI_D10 PT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC_PV6, "CRT_HSYNC PV6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC_PV7, "CRT_VSYNC PV7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PINCTRL_PIN(TEGRA_PIN_SDMMC4_RST_N_PCC3, "SDMMC4_RST_N PCC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PCC6, "PEX_L2_RST_N PCC6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7, "PEX_L2_CLKREQ_N PCC7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINCTRL_PIN(TEGRA_PIN_PEX_L0_PRSNT_N_PDD0, "PEX_L0_PRSNT_N PDD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINCTRL_PIN(TEGRA_PIN_PEX_L1_PRSNT_N_PDD4, "PEX_L1_PRSNT_N PDD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINCTRL_PIN(TEGRA_PIN_PEX_L2_PRSNT_N_PDD7, "PEX_L2_PRSNT_N PDD7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINCTRL_PIN(TEGRA_PIN_PEE4, "PEE4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINCTRL_PIN(TEGRA_PIN_PEE5, "PEE5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINCTRL_PIN(TEGRA_PIN_PEE6, "PEE6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINCTRL_PIN(TEGRA_PIN_PEE7, "PEE7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const unsigned clk_32k_out_pa0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) TEGRA_PIN_CLK_32K_OUT_PA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const unsigned uart3_cts_n_pa1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) TEGRA_PIN_UART3_CTS_N_PA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const unsigned dap2_fs_pa2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) TEGRA_PIN_DAP2_FS_PA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const unsigned dap2_sclk_pa3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) TEGRA_PIN_DAP2_SCLK_PA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const unsigned dap2_din_pa4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) TEGRA_PIN_DAP2_DIN_PA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const unsigned dap2_dout_pa5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) TEGRA_PIN_DAP2_DOUT_PA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const unsigned sdmmc3_clk_pa6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) TEGRA_PIN_SDMMC3_CLK_PA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const unsigned sdmmc3_cmd_pa7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) TEGRA_PIN_SDMMC3_CMD_PA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const unsigned gmi_a17_pb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) TEGRA_PIN_GMI_A17_PB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const unsigned gmi_a18_pb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) TEGRA_PIN_GMI_A18_PB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const unsigned lcd_pwr0_pb2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) TEGRA_PIN_LCD_PWR0_PB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const unsigned lcd_pclk_pb3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) TEGRA_PIN_LCD_PCLK_PB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const unsigned sdmmc3_dat3_pb4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) TEGRA_PIN_SDMMC3_DAT3_PB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const unsigned sdmmc3_dat2_pb5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) TEGRA_PIN_SDMMC3_DAT2_PB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const unsigned sdmmc3_dat1_pb6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) TEGRA_PIN_SDMMC3_DAT1_PB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const unsigned sdmmc3_dat0_pb7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) TEGRA_PIN_SDMMC3_DAT0_PB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const unsigned uart3_rts_n_pc0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) TEGRA_PIN_UART3_RTS_N_PC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const unsigned lcd_pwr1_pc1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) TEGRA_PIN_LCD_PWR1_PC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const unsigned uart2_txd_pc2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) TEGRA_PIN_UART2_TXD_PC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const unsigned uart2_rxd_pc3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) TEGRA_PIN_UART2_RXD_PC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const unsigned gen1_i2c_scl_pc4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) TEGRA_PIN_GEN1_I2C_SCL_PC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const unsigned gen1_i2c_sda_pc5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) TEGRA_PIN_GEN1_I2C_SDA_PC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const unsigned lcd_pwr2_pc6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) TEGRA_PIN_LCD_PWR2_PC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const unsigned gmi_wp_n_pc7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) TEGRA_PIN_GMI_WP_N_PC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static const unsigned sdmmc3_dat5_pd0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) TEGRA_PIN_SDMMC3_DAT5_PD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const unsigned sdmmc3_dat4_pd1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) TEGRA_PIN_SDMMC3_DAT4_PD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const unsigned lcd_dc1_pd2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) TEGRA_PIN_LCD_DC1_PD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const unsigned sdmmc3_dat6_pd3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) TEGRA_PIN_SDMMC3_DAT6_PD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const unsigned sdmmc3_dat7_pd4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) TEGRA_PIN_SDMMC3_DAT7_PD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const unsigned vi_d1_pd5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) TEGRA_PIN_VI_D1_PD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const unsigned vi_vsync_pd6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) TEGRA_PIN_VI_VSYNC_PD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const unsigned vi_hsync_pd7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) TEGRA_PIN_VI_HSYNC_PD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const unsigned lcd_d0_pe0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) TEGRA_PIN_LCD_D0_PE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static const unsigned lcd_d1_pe1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) TEGRA_PIN_LCD_D1_PE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const unsigned lcd_d2_pe2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) TEGRA_PIN_LCD_D2_PE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const unsigned lcd_d3_pe3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) TEGRA_PIN_LCD_D3_PE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const unsigned lcd_d4_pe4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) TEGRA_PIN_LCD_D4_PE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const unsigned lcd_d5_pe5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) TEGRA_PIN_LCD_D5_PE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static const unsigned lcd_d6_pe6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) TEGRA_PIN_LCD_D6_PE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static const unsigned lcd_d7_pe7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) TEGRA_PIN_LCD_D7_PE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const unsigned lcd_d8_pf0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) TEGRA_PIN_LCD_D8_PF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const unsigned lcd_d9_pf1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) TEGRA_PIN_LCD_D9_PF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const unsigned lcd_d10_pf2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) TEGRA_PIN_LCD_D10_PF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const unsigned lcd_d11_pf3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) TEGRA_PIN_LCD_D11_PF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const unsigned lcd_d12_pf4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) TEGRA_PIN_LCD_D12_PF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const unsigned lcd_d13_pf5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) TEGRA_PIN_LCD_D13_PF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const unsigned lcd_d14_pf6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) TEGRA_PIN_LCD_D14_PF6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const unsigned lcd_d15_pf7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) TEGRA_PIN_LCD_D15_PF7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const unsigned gmi_ad0_pg0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) TEGRA_PIN_GMI_AD0_PG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const unsigned gmi_ad1_pg1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) TEGRA_PIN_GMI_AD1_PG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const unsigned gmi_ad2_pg2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) TEGRA_PIN_GMI_AD2_PG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static const unsigned gmi_ad3_pg3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) TEGRA_PIN_GMI_AD3_PG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const unsigned gmi_ad4_pg4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) TEGRA_PIN_GMI_AD4_PG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const unsigned gmi_ad5_pg5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) TEGRA_PIN_GMI_AD5_PG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const unsigned gmi_ad6_pg6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) TEGRA_PIN_GMI_AD6_PG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const unsigned gmi_ad7_pg7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) TEGRA_PIN_GMI_AD7_PG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static const unsigned gmi_ad8_ph0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) TEGRA_PIN_GMI_AD8_PH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static const unsigned gmi_ad9_ph1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) TEGRA_PIN_GMI_AD9_PH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const unsigned gmi_ad10_ph2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) TEGRA_PIN_GMI_AD10_PH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const unsigned gmi_ad11_ph3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) TEGRA_PIN_GMI_AD11_PH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const unsigned gmi_ad12_ph4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) TEGRA_PIN_GMI_AD12_PH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const unsigned gmi_ad13_ph5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) TEGRA_PIN_GMI_AD13_PH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const unsigned gmi_ad14_ph6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) TEGRA_PIN_GMI_AD14_PH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const unsigned gmi_ad15_ph7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) TEGRA_PIN_GMI_AD15_PH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const unsigned gmi_wr_n_pi0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) TEGRA_PIN_GMI_WR_N_PI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static const unsigned gmi_oe_n_pi1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) TEGRA_PIN_GMI_OE_N_PI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const unsigned gmi_dqs_pi2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) TEGRA_PIN_GMI_DQS_PI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const unsigned gmi_cs6_n_pi3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) TEGRA_PIN_GMI_CS6_N_PI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const unsigned gmi_rst_n_pi4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) TEGRA_PIN_GMI_RST_N_PI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const unsigned gmi_iordy_pi5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) TEGRA_PIN_GMI_IORDY_PI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const unsigned gmi_cs7_n_pi6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) TEGRA_PIN_GMI_CS7_N_PI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const unsigned gmi_wait_pi7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) TEGRA_PIN_GMI_WAIT_PI7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static const unsigned gmi_cs0_n_pj0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) TEGRA_PIN_GMI_CS0_N_PJ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const unsigned lcd_de_pj1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) TEGRA_PIN_LCD_DE_PJ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const unsigned gmi_cs1_n_pj2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) TEGRA_PIN_GMI_CS1_N_PJ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static const unsigned lcd_hsync_pj3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) TEGRA_PIN_LCD_HSYNC_PJ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const unsigned lcd_vsync_pj4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) TEGRA_PIN_LCD_VSYNC_PJ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const unsigned uart2_cts_n_pj5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) TEGRA_PIN_UART2_CTS_N_PJ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const unsigned uart2_rts_n_pj6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) TEGRA_PIN_UART2_RTS_N_PJ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const unsigned gmi_a16_pj7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) TEGRA_PIN_GMI_A16_PJ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static const unsigned gmi_adv_n_pk0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) TEGRA_PIN_GMI_ADV_N_PK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const unsigned gmi_clk_pk1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) TEGRA_PIN_GMI_CLK_PK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const unsigned gmi_cs4_n_pk2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) TEGRA_PIN_GMI_CS4_N_PK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const unsigned gmi_cs2_n_pk3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) TEGRA_PIN_GMI_CS2_N_PK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const unsigned gmi_cs3_n_pk4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) TEGRA_PIN_GMI_CS3_N_PK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const unsigned spdif_out_pk5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) TEGRA_PIN_SPDIF_OUT_PK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static const unsigned spdif_in_pk6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) TEGRA_PIN_SPDIF_IN_PK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const unsigned gmi_a19_pk7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) TEGRA_PIN_GMI_A19_PK7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const unsigned vi_d2_pl0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) TEGRA_PIN_VI_D2_PL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static const unsigned vi_d3_pl1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) TEGRA_PIN_VI_D3_PL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const unsigned vi_d4_pl2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) TEGRA_PIN_VI_D4_PL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static const unsigned vi_d5_pl3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) TEGRA_PIN_VI_D5_PL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const unsigned vi_d6_pl4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) TEGRA_PIN_VI_D6_PL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static const unsigned vi_d7_pl5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) TEGRA_PIN_VI_D7_PL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const unsigned vi_d8_pl6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) TEGRA_PIN_VI_D8_PL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const unsigned vi_d9_pl7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) TEGRA_PIN_VI_D9_PL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const unsigned lcd_d16_pm0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) TEGRA_PIN_LCD_D16_PM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const unsigned lcd_d17_pm1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) TEGRA_PIN_LCD_D17_PM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const unsigned lcd_d18_pm2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) TEGRA_PIN_LCD_D18_PM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const unsigned lcd_d19_pm3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) TEGRA_PIN_LCD_D19_PM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const unsigned lcd_d20_pm4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) TEGRA_PIN_LCD_D20_PM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static const unsigned lcd_d21_pm5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) TEGRA_PIN_LCD_D21_PM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const unsigned lcd_d22_pm6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) TEGRA_PIN_LCD_D22_PM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static const unsigned lcd_d23_pm7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) TEGRA_PIN_LCD_D23_PM7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const unsigned dap1_fs_pn0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) TEGRA_PIN_DAP1_FS_PN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const unsigned dap1_din_pn1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) TEGRA_PIN_DAP1_DIN_PN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const unsigned dap1_dout_pn2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) TEGRA_PIN_DAP1_DOUT_PN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const unsigned dap1_sclk_pn3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) TEGRA_PIN_DAP1_SCLK_PN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const unsigned lcd_cs0_n_pn4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) TEGRA_PIN_LCD_CS0_N_PN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const unsigned lcd_sdout_pn5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) TEGRA_PIN_LCD_SDOUT_PN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const unsigned lcd_dc0_pn6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) TEGRA_PIN_LCD_DC0_PN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const unsigned hdmi_int_pn7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) TEGRA_PIN_HDMI_INT_PN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static const unsigned ulpi_data7_po0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) TEGRA_PIN_ULPI_DATA7_PO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const unsigned ulpi_data0_po1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) TEGRA_PIN_ULPI_DATA0_PO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const unsigned ulpi_data1_po2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) TEGRA_PIN_ULPI_DATA1_PO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static const unsigned ulpi_data2_po3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) TEGRA_PIN_ULPI_DATA2_PO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static const unsigned ulpi_data3_po4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) TEGRA_PIN_ULPI_DATA3_PO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const unsigned ulpi_data4_po5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) TEGRA_PIN_ULPI_DATA4_PO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static const unsigned ulpi_data5_po6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) TEGRA_PIN_ULPI_DATA5_PO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static const unsigned ulpi_data6_po7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) TEGRA_PIN_ULPI_DATA6_PO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const unsigned dap3_fs_pp0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) TEGRA_PIN_DAP3_FS_PP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const unsigned dap3_din_pp1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) TEGRA_PIN_DAP3_DIN_PP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static const unsigned dap3_dout_pp2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) TEGRA_PIN_DAP3_DOUT_PP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static const unsigned dap3_sclk_pp3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) TEGRA_PIN_DAP3_SCLK_PP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static const unsigned dap4_fs_pp4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) TEGRA_PIN_DAP4_FS_PP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static const unsigned dap4_din_pp5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) TEGRA_PIN_DAP4_DIN_PP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const unsigned dap4_dout_pp6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) TEGRA_PIN_DAP4_DOUT_PP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static const unsigned dap4_sclk_pp7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) TEGRA_PIN_DAP4_SCLK_PP7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static const unsigned kb_col0_pq0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) TEGRA_PIN_KB_COL0_PQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static const unsigned kb_col1_pq1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) TEGRA_PIN_KB_COL1_PQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static const unsigned kb_col2_pq2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) TEGRA_PIN_KB_COL2_PQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static const unsigned kb_col3_pq3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) TEGRA_PIN_KB_COL3_PQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static const unsigned kb_col4_pq4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) TEGRA_PIN_KB_COL4_PQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static const unsigned kb_col5_pq5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) TEGRA_PIN_KB_COL5_PQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static const unsigned kb_col6_pq6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) TEGRA_PIN_KB_COL6_PQ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static const unsigned kb_col7_pq7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) TEGRA_PIN_KB_COL7_PQ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static const unsigned kb_row0_pr0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) TEGRA_PIN_KB_ROW0_PR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static const unsigned kb_row1_pr1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) TEGRA_PIN_KB_ROW1_PR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static const unsigned kb_row2_pr2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) TEGRA_PIN_KB_ROW2_PR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static const unsigned kb_row3_pr3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) TEGRA_PIN_KB_ROW3_PR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static const unsigned kb_row4_pr4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) TEGRA_PIN_KB_ROW4_PR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static const unsigned kb_row5_pr5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) TEGRA_PIN_KB_ROW5_PR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static const unsigned kb_row6_pr6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) TEGRA_PIN_KB_ROW6_PR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static const unsigned kb_row7_pr7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) TEGRA_PIN_KB_ROW7_PR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static const unsigned kb_row8_ps0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) TEGRA_PIN_KB_ROW8_PS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static const unsigned kb_row9_ps1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) TEGRA_PIN_KB_ROW9_PS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static const unsigned kb_row10_ps2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) TEGRA_PIN_KB_ROW10_PS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const unsigned kb_row11_ps3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) TEGRA_PIN_KB_ROW11_PS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static const unsigned kb_row12_ps4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) TEGRA_PIN_KB_ROW12_PS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static const unsigned kb_row13_ps5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) TEGRA_PIN_KB_ROW13_PS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static const unsigned kb_row14_ps6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) TEGRA_PIN_KB_ROW14_PS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const unsigned kb_row15_ps7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) TEGRA_PIN_KB_ROW15_PS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static const unsigned vi_pclk_pt0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) TEGRA_PIN_VI_PCLK_PT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const unsigned vi_mclk_pt1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) TEGRA_PIN_VI_MCLK_PT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static const unsigned vi_d10_pt2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) TEGRA_PIN_VI_D10_PT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const unsigned vi_d11_pt3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) TEGRA_PIN_VI_D11_PT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static const unsigned vi_d0_pt4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) TEGRA_PIN_VI_D0_PT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static const unsigned gen2_i2c_scl_pt5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) TEGRA_PIN_GEN2_I2C_SCL_PT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static const unsigned gen2_i2c_sda_pt6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) TEGRA_PIN_GEN2_I2C_SDA_PT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static const unsigned sdmmc4_cmd_pt7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) TEGRA_PIN_SDMMC4_CMD_PT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static const unsigned pu0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) TEGRA_PIN_PU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const unsigned pu1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) TEGRA_PIN_PU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static const unsigned pu2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) TEGRA_PIN_PU2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static const unsigned pu3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) TEGRA_PIN_PU3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static const unsigned pu4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) TEGRA_PIN_PU4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static const unsigned pu5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) TEGRA_PIN_PU5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static const unsigned pu6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) TEGRA_PIN_PU6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static const unsigned jtag_rtck_pu7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) TEGRA_PIN_JTAG_RTCK_PU7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static const unsigned pv0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) TEGRA_PIN_PV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static const unsigned pv1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) TEGRA_PIN_PV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static const unsigned pv2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) TEGRA_PIN_PV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static const unsigned pv3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) TEGRA_PIN_PV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const unsigned ddc_scl_pv4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) TEGRA_PIN_DDC_SCL_PV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static const unsigned ddc_sda_pv5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) TEGRA_PIN_DDC_SDA_PV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static const unsigned crt_hsync_pv6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) TEGRA_PIN_CRT_HSYNC_PV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static const unsigned crt_vsync_pv7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) TEGRA_PIN_CRT_VSYNC_PV7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const unsigned lcd_cs1_n_pw0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) TEGRA_PIN_LCD_CS1_N_PW0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static const unsigned lcd_m1_pw1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) TEGRA_PIN_LCD_M1_PW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static const unsigned spi2_cs1_n_pw2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) TEGRA_PIN_SPI2_CS1_N_PW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const unsigned spi2_cs2_n_pw3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) TEGRA_PIN_SPI2_CS2_N_PW3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static const unsigned clk1_out_pw4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) TEGRA_PIN_CLK1_OUT_PW4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static const unsigned clk2_out_pw5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) TEGRA_PIN_CLK2_OUT_PW5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static const unsigned uart3_txd_pw6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) TEGRA_PIN_UART3_TXD_PW6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static const unsigned uart3_rxd_pw7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) TEGRA_PIN_UART3_RXD_PW7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static const unsigned spi2_mosi_px0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) TEGRA_PIN_SPI2_MOSI_PX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static const unsigned spi2_miso_px1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) TEGRA_PIN_SPI2_MISO_PX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static const unsigned spi2_sck_px2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) TEGRA_PIN_SPI2_SCK_PX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static const unsigned spi2_cs0_n_px3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) TEGRA_PIN_SPI2_CS0_N_PX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static const unsigned spi1_mosi_px4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) TEGRA_PIN_SPI1_MOSI_PX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static const unsigned spi1_sck_px5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) TEGRA_PIN_SPI1_SCK_PX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const unsigned spi1_cs0_n_px6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) TEGRA_PIN_SPI1_CS0_N_PX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static const unsigned spi1_miso_px7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) TEGRA_PIN_SPI1_MISO_PX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static const unsigned ulpi_clk_py0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) TEGRA_PIN_ULPI_CLK_PY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static const unsigned ulpi_dir_py1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) TEGRA_PIN_ULPI_DIR_PY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static const unsigned ulpi_nxt_py2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) TEGRA_PIN_ULPI_NXT_PY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static const unsigned ulpi_stp_py3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) TEGRA_PIN_ULPI_STP_PY3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const unsigned sdmmc1_dat3_py4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) TEGRA_PIN_SDMMC1_DAT3_PY4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static const unsigned sdmmc1_dat2_py5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) TEGRA_PIN_SDMMC1_DAT2_PY5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static const unsigned sdmmc1_dat1_py6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) TEGRA_PIN_SDMMC1_DAT1_PY6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static const unsigned sdmmc1_dat0_py7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) TEGRA_PIN_SDMMC1_DAT0_PY7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static const unsigned sdmmc1_clk_pz0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) TEGRA_PIN_SDMMC1_CLK_PZ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static const unsigned sdmmc1_cmd_pz1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) TEGRA_PIN_SDMMC1_CMD_PZ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static const unsigned lcd_sdin_pz2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) TEGRA_PIN_LCD_SDIN_PZ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static const unsigned lcd_wr_n_pz3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) TEGRA_PIN_LCD_WR_N_PZ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static const unsigned lcd_sck_pz4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) TEGRA_PIN_LCD_SCK_PZ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static const unsigned sys_clk_req_pz5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) TEGRA_PIN_SYS_CLK_REQ_PZ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static const unsigned pwr_i2c_scl_pz6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) TEGRA_PIN_PWR_I2C_SCL_PZ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static const unsigned pwr_i2c_sda_pz7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) TEGRA_PIN_PWR_I2C_SDA_PZ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static const unsigned sdmmc4_dat0_paa0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) TEGRA_PIN_SDMMC4_DAT0_PAA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static const unsigned sdmmc4_dat1_paa1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) TEGRA_PIN_SDMMC4_DAT1_PAA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static const unsigned sdmmc4_dat2_paa2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) TEGRA_PIN_SDMMC4_DAT2_PAA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static const unsigned sdmmc4_dat3_paa3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) TEGRA_PIN_SDMMC4_DAT3_PAA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static const unsigned sdmmc4_dat4_paa4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) TEGRA_PIN_SDMMC4_DAT4_PAA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static const unsigned sdmmc4_dat5_paa5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) TEGRA_PIN_SDMMC4_DAT5_PAA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static const unsigned sdmmc4_dat6_paa6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) TEGRA_PIN_SDMMC4_DAT6_PAA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static const unsigned sdmmc4_dat7_paa7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) TEGRA_PIN_SDMMC4_DAT7_PAA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static const unsigned pbb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) TEGRA_PIN_PBB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static const unsigned cam_i2c_scl_pbb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) TEGRA_PIN_CAM_I2C_SCL_PBB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static const unsigned cam_i2c_sda_pbb2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) TEGRA_PIN_CAM_I2C_SDA_PBB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static const unsigned pbb3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) TEGRA_PIN_PBB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static const unsigned pbb4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) TEGRA_PIN_PBB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static const unsigned pbb5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) TEGRA_PIN_PBB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static const unsigned pbb6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) TEGRA_PIN_PBB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static const unsigned pbb7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) TEGRA_PIN_PBB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static const unsigned cam_mclk_pcc0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) TEGRA_PIN_CAM_MCLK_PCC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static const unsigned pcc1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) TEGRA_PIN_PCC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static const unsigned pcc2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) TEGRA_PIN_PCC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static const unsigned sdmmc4_rst_n_pcc3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) TEGRA_PIN_SDMMC4_RST_N_PCC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const unsigned sdmmc4_clk_pcc4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) TEGRA_PIN_SDMMC4_CLK_PCC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static const unsigned clk2_req_pcc5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) TEGRA_PIN_CLK2_REQ_PCC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static const unsigned pex_l2_rst_n_pcc6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) TEGRA_PIN_PEX_L2_RST_N_PCC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static const unsigned pex_l2_clkreq_n_pcc7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const unsigned pex_l0_prsnt_n_pdd0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const unsigned pex_l0_rst_n_pdd1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) TEGRA_PIN_PEX_L0_RST_N_PDD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static const unsigned pex_wake_n_pdd3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) TEGRA_PIN_PEX_WAKE_N_PDD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static const unsigned pex_l1_prsnt_n_pdd4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static const unsigned pex_l1_rst_n_pdd5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) TEGRA_PIN_PEX_L1_RST_N_PDD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static const unsigned pex_l2_prsnt_n_pdd7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static const unsigned clk3_out_pee0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) TEGRA_PIN_CLK3_OUT_PEE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static const unsigned clk3_req_pee1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) TEGRA_PIN_CLK3_REQ_PEE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static const unsigned clk1_req_pee2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) TEGRA_PIN_CLK1_REQ_PEE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const unsigned hdmi_cec_pee3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) TEGRA_PIN_HDMI_CEC_PEE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static const unsigned clk_32k_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) TEGRA_PIN_CLK_32K_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static const unsigned core_pwr_req_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) TEGRA_PIN_CORE_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static const unsigned cpu_pwr_req_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) TEGRA_PIN_CPU_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static const unsigned owr_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) TEGRA_PIN_OWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static const unsigned pwr_int_n_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) TEGRA_PIN_PWR_INT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static const unsigned drive_ao1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) TEGRA_PIN_KB_ROW0_PR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) TEGRA_PIN_KB_ROW1_PR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) TEGRA_PIN_KB_ROW2_PR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) TEGRA_PIN_KB_ROW3_PR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) TEGRA_PIN_KB_ROW4_PR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) TEGRA_PIN_KB_ROW5_PR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) TEGRA_PIN_KB_ROW6_PR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) TEGRA_PIN_KB_ROW7_PR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) TEGRA_PIN_PWR_I2C_SCL_PZ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) TEGRA_PIN_PWR_I2C_SDA_PZ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) TEGRA_PIN_SYS_RESET_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static const unsigned drive_ao2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) TEGRA_PIN_CLK_32K_OUT_PA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) TEGRA_PIN_KB_COL0_PQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) TEGRA_PIN_KB_COL1_PQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) TEGRA_PIN_KB_COL2_PQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) TEGRA_PIN_KB_COL3_PQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) TEGRA_PIN_KB_COL4_PQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) TEGRA_PIN_KB_COL5_PQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) TEGRA_PIN_KB_COL6_PQ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) TEGRA_PIN_KB_COL7_PQ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) TEGRA_PIN_KB_ROW8_PS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) TEGRA_PIN_KB_ROW9_PS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) TEGRA_PIN_KB_ROW10_PS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) TEGRA_PIN_KB_ROW11_PS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) TEGRA_PIN_KB_ROW12_PS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) TEGRA_PIN_KB_ROW13_PS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) TEGRA_PIN_KB_ROW14_PS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) TEGRA_PIN_KB_ROW15_PS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) TEGRA_PIN_SYS_CLK_REQ_PZ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) TEGRA_PIN_CLK_32K_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) TEGRA_PIN_CORE_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) TEGRA_PIN_CPU_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) TEGRA_PIN_PWR_INT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static const unsigned drive_at1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) TEGRA_PIN_GMI_AD8_PH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) TEGRA_PIN_GMI_AD9_PH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) TEGRA_PIN_GMI_AD10_PH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) TEGRA_PIN_GMI_AD11_PH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) TEGRA_PIN_GMI_AD12_PH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) TEGRA_PIN_GMI_AD13_PH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) TEGRA_PIN_GMI_AD14_PH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) TEGRA_PIN_GMI_AD15_PH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) TEGRA_PIN_GMI_IORDY_PI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) TEGRA_PIN_GMI_CS7_N_PI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static const unsigned drive_at2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) TEGRA_PIN_GMI_AD0_PG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) TEGRA_PIN_GMI_AD1_PG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) TEGRA_PIN_GMI_AD2_PG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) TEGRA_PIN_GMI_AD3_PG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) TEGRA_PIN_GMI_AD4_PG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) TEGRA_PIN_GMI_AD5_PG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) TEGRA_PIN_GMI_AD6_PG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) TEGRA_PIN_GMI_AD7_PG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) TEGRA_PIN_GMI_WR_N_PI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) TEGRA_PIN_GMI_OE_N_PI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) TEGRA_PIN_GMI_DQS_PI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) TEGRA_PIN_GMI_CS6_N_PI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) TEGRA_PIN_GMI_RST_N_PI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) TEGRA_PIN_GMI_WAIT_PI7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) TEGRA_PIN_GMI_ADV_N_PK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) TEGRA_PIN_GMI_CLK_PK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) TEGRA_PIN_GMI_CS4_N_PK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) TEGRA_PIN_GMI_CS2_N_PK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) TEGRA_PIN_GMI_CS3_N_PK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static const unsigned drive_at3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) TEGRA_PIN_GMI_WP_N_PC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) TEGRA_PIN_GMI_CS0_N_PJ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static const unsigned drive_at4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) TEGRA_PIN_GMI_A17_PB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) TEGRA_PIN_GMI_A18_PB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) TEGRA_PIN_GMI_CS1_N_PJ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) TEGRA_PIN_GMI_A16_PJ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) TEGRA_PIN_GMI_A19_PK7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static const unsigned drive_at5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) TEGRA_PIN_GEN2_I2C_SCL_PT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) TEGRA_PIN_GEN2_I2C_SDA_PT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static const unsigned drive_cdev1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) TEGRA_PIN_CLK1_OUT_PW4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) TEGRA_PIN_CLK1_REQ_PEE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static const unsigned drive_cdev2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) TEGRA_PIN_CLK2_OUT_PW5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) TEGRA_PIN_CLK2_REQ_PCC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static const unsigned drive_cec_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) TEGRA_PIN_HDMI_CEC_PEE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static const unsigned drive_crt_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) TEGRA_PIN_CRT_HSYNC_PV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) TEGRA_PIN_CRT_VSYNC_PV7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static const unsigned drive_csus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) TEGRA_PIN_VI_MCLK_PT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static const unsigned drive_dap1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) TEGRA_PIN_SPDIF_OUT_PK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) TEGRA_PIN_SPDIF_IN_PK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) TEGRA_PIN_DAP1_FS_PN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) TEGRA_PIN_DAP1_DIN_PN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) TEGRA_PIN_DAP1_DOUT_PN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) TEGRA_PIN_DAP1_SCLK_PN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static const unsigned drive_dap2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) TEGRA_PIN_DAP2_FS_PA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) TEGRA_PIN_DAP2_SCLK_PA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) TEGRA_PIN_DAP2_DIN_PA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) TEGRA_PIN_DAP2_DOUT_PA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) static const unsigned drive_dap3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) TEGRA_PIN_DAP3_FS_PP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) TEGRA_PIN_DAP3_DIN_PP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) TEGRA_PIN_DAP3_DOUT_PP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) TEGRA_PIN_DAP3_SCLK_PP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) static const unsigned drive_dap4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) TEGRA_PIN_DAP4_FS_PP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) TEGRA_PIN_DAP4_DIN_PP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) TEGRA_PIN_DAP4_DOUT_PP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) TEGRA_PIN_DAP4_SCLK_PP7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) static const unsigned drive_dbg_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) TEGRA_PIN_GEN1_I2C_SCL_PC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) TEGRA_PIN_GEN1_I2C_SDA_PC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) TEGRA_PIN_PU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) TEGRA_PIN_PU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) TEGRA_PIN_PU2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) TEGRA_PIN_PU3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) TEGRA_PIN_PU4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) TEGRA_PIN_PU5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) TEGRA_PIN_PU6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) TEGRA_PIN_JTAG_RTCK_PU7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) TEGRA_PIN_JTAG_TCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) TEGRA_PIN_JTAG_TDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) TEGRA_PIN_JTAG_TDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) TEGRA_PIN_JTAG_TMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) TEGRA_PIN_JTAG_TRST_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) TEGRA_PIN_TEST_MODE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static const unsigned drive_ddc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) TEGRA_PIN_DDC_SCL_PV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) TEGRA_PIN_DDC_SDA_PV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static const unsigned drive_dev3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) TEGRA_PIN_CLK3_OUT_PEE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) TEGRA_PIN_CLK3_REQ_PEE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static const unsigned drive_gma_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) TEGRA_PIN_SDMMC4_DAT0_PAA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) TEGRA_PIN_SDMMC4_DAT1_PAA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) TEGRA_PIN_SDMMC4_DAT2_PAA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) TEGRA_PIN_SDMMC4_DAT3_PAA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) TEGRA_PIN_SDMMC4_RST_N_PCC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static const unsigned drive_gmb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) TEGRA_PIN_SDMMC4_DAT4_PAA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) TEGRA_PIN_SDMMC4_DAT5_PAA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) TEGRA_PIN_SDMMC4_DAT6_PAA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) TEGRA_PIN_SDMMC4_DAT7_PAA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static const unsigned drive_gmc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) TEGRA_PIN_SDMMC4_CLK_PCC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static const unsigned drive_gmd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) TEGRA_PIN_SDMMC4_CMD_PT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static const unsigned drive_gme_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) TEGRA_PIN_PBB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) TEGRA_PIN_CAM_I2C_SCL_PBB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) TEGRA_PIN_CAM_I2C_SDA_PBB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) TEGRA_PIN_PBB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) TEGRA_PIN_PCC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static const unsigned drive_gmf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) TEGRA_PIN_PBB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) TEGRA_PIN_PBB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) TEGRA_PIN_PBB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) TEGRA_PIN_PBB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static const unsigned drive_gmg_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) TEGRA_PIN_CAM_MCLK_PCC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static const unsigned drive_gmh_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) TEGRA_PIN_PCC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static const unsigned drive_gpv_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) TEGRA_PIN_PEX_L2_RST_N_PCC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) TEGRA_PIN_PEX_L0_PRSNT_N_PDD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) TEGRA_PIN_PEX_L0_RST_N_PDD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) TEGRA_PIN_PEX_WAKE_N_PDD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) TEGRA_PIN_PEX_L1_PRSNT_N_PDD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) TEGRA_PIN_PEX_L1_RST_N_PDD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) TEGRA_PIN_PEX_L2_PRSNT_N_PDD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static const unsigned drive_lcd1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) TEGRA_PIN_LCD_PWR1_PC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) TEGRA_PIN_LCD_PWR2_PC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) TEGRA_PIN_LCD_CS0_N_PN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) TEGRA_PIN_LCD_SDOUT_PN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) TEGRA_PIN_LCD_DC0_PN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) TEGRA_PIN_LCD_SDIN_PZ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) TEGRA_PIN_LCD_WR_N_PZ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) TEGRA_PIN_LCD_SCK_PZ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static const unsigned drive_lcd2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) TEGRA_PIN_LCD_PWR0_PB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) TEGRA_PIN_LCD_PCLK_PB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) TEGRA_PIN_LCD_DC1_PD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) TEGRA_PIN_LCD_D0_PE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) TEGRA_PIN_LCD_D1_PE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) TEGRA_PIN_LCD_D2_PE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) TEGRA_PIN_LCD_D3_PE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) TEGRA_PIN_LCD_D4_PE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) TEGRA_PIN_LCD_D5_PE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) TEGRA_PIN_LCD_D6_PE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) TEGRA_PIN_LCD_D7_PE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) TEGRA_PIN_LCD_D8_PF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) TEGRA_PIN_LCD_D9_PF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) TEGRA_PIN_LCD_D10_PF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) TEGRA_PIN_LCD_D11_PF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) TEGRA_PIN_LCD_D12_PF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) TEGRA_PIN_LCD_D13_PF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) TEGRA_PIN_LCD_D14_PF6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) TEGRA_PIN_LCD_D15_PF7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) TEGRA_PIN_LCD_DE_PJ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) TEGRA_PIN_LCD_HSYNC_PJ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) TEGRA_PIN_LCD_VSYNC_PJ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) TEGRA_PIN_LCD_D16_PM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) TEGRA_PIN_LCD_D17_PM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) TEGRA_PIN_LCD_D18_PM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) TEGRA_PIN_LCD_D19_PM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) TEGRA_PIN_LCD_D20_PM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) TEGRA_PIN_LCD_D21_PM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) TEGRA_PIN_LCD_D22_PM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) TEGRA_PIN_LCD_D23_PM7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) TEGRA_PIN_HDMI_INT_PN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) TEGRA_PIN_LCD_CS1_N_PW0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) TEGRA_PIN_LCD_M1_PW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) static const unsigned drive_owr_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) TEGRA_PIN_OWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static const unsigned drive_sdio1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) TEGRA_PIN_SDMMC1_DAT3_PY4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) TEGRA_PIN_SDMMC1_DAT2_PY5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) TEGRA_PIN_SDMMC1_DAT1_PY6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) TEGRA_PIN_SDMMC1_DAT0_PY7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) TEGRA_PIN_SDMMC1_CLK_PZ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) TEGRA_PIN_SDMMC1_CMD_PZ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static const unsigned drive_sdio2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) TEGRA_PIN_SDMMC3_DAT5_PD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) TEGRA_PIN_SDMMC3_DAT4_PD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) TEGRA_PIN_SDMMC3_DAT6_PD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) TEGRA_PIN_SDMMC3_DAT7_PD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static const unsigned drive_sdio3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) TEGRA_PIN_SDMMC3_CLK_PA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) TEGRA_PIN_SDMMC3_CMD_PA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) TEGRA_PIN_SDMMC3_DAT3_PB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) TEGRA_PIN_SDMMC3_DAT2_PB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) TEGRA_PIN_SDMMC3_DAT1_PB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) TEGRA_PIN_SDMMC3_DAT0_PB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static const unsigned drive_spi_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) TEGRA_PIN_SPI2_CS1_N_PW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) TEGRA_PIN_SPI2_CS2_N_PW3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) TEGRA_PIN_SPI2_MOSI_PX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) TEGRA_PIN_SPI2_MISO_PX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) TEGRA_PIN_SPI2_SCK_PX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) TEGRA_PIN_SPI2_CS0_N_PX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) TEGRA_PIN_SPI1_MOSI_PX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) TEGRA_PIN_SPI1_SCK_PX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) TEGRA_PIN_SPI1_CS0_N_PX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) TEGRA_PIN_SPI1_MISO_PX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static const unsigned drive_uaa_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) TEGRA_PIN_ULPI_DATA0_PO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) TEGRA_PIN_ULPI_DATA1_PO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) TEGRA_PIN_ULPI_DATA2_PO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) TEGRA_PIN_ULPI_DATA3_PO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static const unsigned drive_uab_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) TEGRA_PIN_ULPI_DATA7_PO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) TEGRA_PIN_ULPI_DATA4_PO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) TEGRA_PIN_ULPI_DATA5_PO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) TEGRA_PIN_ULPI_DATA6_PO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) TEGRA_PIN_PV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) TEGRA_PIN_PV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) TEGRA_PIN_PV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) TEGRA_PIN_PV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static const unsigned drive_uart2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) TEGRA_PIN_UART2_TXD_PC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) TEGRA_PIN_UART2_RXD_PC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) TEGRA_PIN_UART2_CTS_N_PJ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) TEGRA_PIN_UART2_RTS_N_PJ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static const unsigned drive_uart3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) TEGRA_PIN_UART3_CTS_N_PA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) TEGRA_PIN_UART3_RTS_N_PC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) TEGRA_PIN_UART3_TXD_PW6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) TEGRA_PIN_UART3_RXD_PW7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static const unsigned drive_uda_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) TEGRA_PIN_ULPI_CLK_PY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) TEGRA_PIN_ULPI_DIR_PY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) TEGRA_PIN_ULPI_NXT_PY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) TEGRA_PIN_ULPI_STP_PY3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static const unsigned drive_vi1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) TEGRA_PIN_VI_D1_PD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) TEGRA_PIN_VI_VSYNC_PD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) TEGRA_PIN_VI_HSYNC_PD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) TEGRA_PIN_VI_D2_PL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) TEGRA_PIN_VI_D3_PL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) TEGRA_PIN_VI_D4_PL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) TEGRA_PIN_VI_D5_PL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) TEGRA_PIN_VI_D6_PL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) TEGRA_PIN_VI_D7_PL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) TEGRA_PIN_VI_D8_PL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) TEGRA_PIN_VI_D9_PL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) TEGRA_PIN_VI_PCLK_PT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) TEGRA_PIN_VI_D10_PT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) TEGRA_PIN_VI_D11_PT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) TEGRA_PIN_VI_D0_PT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) enum tegra_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) TEGRA_MUX_BLINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) TEGRA_MUX_CEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) TEGRA_MUX_CLK_12M_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) TEGRA_MUX_CLK_32K_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) TEGRA_MUX_CORE_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) TEGRA_MUX_CPU_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) TEGRA_MUX_CRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) TEGRA_MUX_DAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) TEGRA_MUX_DDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) TEGRA_MUX_DEV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) TEGRA_MUX_DISPLAYA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) TEGRA_MUX_DISPLAYB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) TEGRA_MUX_DTV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) TEGRA_MUX_EXTPERIPH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) TEGRA_MUX_EXTPERIPH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) TEGRA_MUX_EXTPERIPH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) TEGRA_MUX_GMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) TEGRA_MUX_GMI_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) TEGRA_MUX_HDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) TEGRA_MUX_HDCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) TEGRA_MUX_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) TEGRA_MUX_HSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) TEGRA_MUX_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) TEGRA_MUX_I2C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) TEGRA_MUX_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) TEGRA_MUX_I2C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) TEGRA_MUX_I2CPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) TEGRA_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) TEGRA_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) TEGRA_MUX_I2S2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) TEGRA_MUX_I2S3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) TEGRA_MUX_I2S4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) TEGRA_MUX_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) TEGRA_MUX_KBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) TEGRA_MUX_MIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) TEGRA_MUX_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) TEGRA_MUX_NAND_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) TEGRA_MUX_OWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) TEGRA_MUX_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) TEGRA_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) TEGRA_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) TEGRA_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) TEGRA_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) TEGRA_MUX_PWR_INT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) TEGRA_MUX_RSVD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) TEGRA_MUX_RSVD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) TEGRA_MUX_RSVD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) TEGRA_MUX_RSVD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) TEGRA_MUX_RTCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) TEGRA_MUX_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) TEGRA_MUX_SDMMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) TEGRA_MUX_SDMMC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) TEGRA_MUX_SDMMC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) TEGRA_MUX_SDMMC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) TEGRA_MUX_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) TEGRA_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) TEGRA_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) TEGRA_MUX_SPI2_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) TEGRA_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) TEGRA_MUX_SPI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) TEGRA_MUX_SPI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) TEGRA_MUX_SPI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) TEGRA_MUX_SYSCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) TEGRA_MUX_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) TEGRA_MUX_TRACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) TEGRA_MUX_UARTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) TEGRA_MUX_UARTB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) TEGRA_MUX_UARTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) TEGRA_MUX_UARTD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) TEGRA_MUX_UARTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) TEGRA_MUX_ULPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) TEGRA_MUX_VGP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) TEGRA_MUX_VGP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) TEGRA_MUX_VGP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) TEGRA_MUX_VGP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) TEGRA_MUX_VGP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) TEGRA_MUX_VGP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) TEGRA_MUX_VI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) TEGRA_MUX_VI_ALT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) TEGRA_MUX_VI_ALT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) TEGRA_MUX_VI_ALT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static struct tegra_function tegra30_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) FUNCTION(blink),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) FUNCTION(cec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) FUNCTION(clk_12m_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) FUNCTION(clk_32k_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) FUNCTION(core_pwr_req),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) FUNCTION(cpu_pwr_req),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) FUNCTION(crt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) FUNCTION(dap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) FUNCTION(ddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) FUNCTION(dev3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) FUNCTION(displaya),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) FUNCTION(displayb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) FUNCTION(dtv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) FUNCTION(extperiph1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) FUNCTION(extperiph2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) FUNCTION(extperiph3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) FUNCTION(gmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) FUNCTION(gmi_alt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) FUNCTION(hda),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) FUNCTION(hdcp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) FUNCTION(hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) FUNCTION(hsi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) FUNCTION(i2cpwr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) FUNCTION(i2s0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) FUNCTION(i2s1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) FUNCTION(i2s2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) FUNCTION(i2s3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) FUNCTION(i2s4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) FUNCTION(invalid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) FUNCTION(kbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) FUNCTION(mio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) FUNCTION(nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) FUNCTION(nand_alt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) FUNCTION(owr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) FUNCTION(pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) FUNCTION(pwr_int_n),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) FUNCTION(rsvd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) FUNCTION(rsvd2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) FUNCTION(rsvd3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) FUNCTION(rsvd4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) FUNCTION(rtck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) FUNCTION(sata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) FUNCTION(sdmmc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) FUNCTION(sdmmc2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) FUNCTION(sdmmc3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) FUNCTION(sdmmc4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) FUNCTION(spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) FUNCTION(spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) FUNCTION(spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) FUNCTION(spi2_alt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) FUNCTION(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) FUNCTION(spi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) FUNCTION(spi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) FUNCTION(spi6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) FUNCTION(sysclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) FUNCTION(test),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) FUNCTION(trace),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) FUNCTION(uarta),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) FUNCTION(uartb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) FUNCTION(uartc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) FUNCTION(uartd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) FUNCTION(uarte),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) FUNCTION(ulpi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) FUNCTION(vgp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) FUNCTION(vgp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) FUNCTION(vgp3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) FUNCTION(vgp4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) FUNCTION(vgp5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) FUNCTION(vgp6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) FUNCTION(vi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) FUNCTION(vi_alt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) FUNCTION(vi_alt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) FUNCTION(vi_alt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) #define PINGROUP_REG_A 0x3000 /* bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) #define PINGROUP_BIT_Y(b) (b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #define PINGROUP_BIT_N(b) (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .funcs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) TEGRA_MUX_##f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) TEGRA_MUX_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) TEGRA_MUX_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) TEGRA_MUX_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .mux_reg = PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .mux_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .mux_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .pupd_reg = PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .pupd_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .pupd_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .tri_reg = PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .tri_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .tri_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .einput_bit = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .odrain_bit = PINGROUP_BIT_##od(6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .lock_bit = 7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .ioreset_bit = PINGROUP_BIT_##ior(8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .rcv_sel_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .drv_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .parked_bitmask = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) slwf_b, slwf_w) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .name = "drive_" #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .pins = drive_##pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .mux_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .pupd_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .tri_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .einput_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .odrain_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .lock_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .ioreset_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .rcv_sel_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .drv_reg = DRV_PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .drv_bank = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .hsm_bit = hsm_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .schmitt_bit = schmitt_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .lpmd_bit = lpmd_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .drvdn_bit = drvdn_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .drvdn_width = drvdn_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .drvup_bit = drvup_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .drvup_width = drvup_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .slwr_bit = slwr_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .slwr_width = slwr_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .slwf_bit = slwf_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .slwf_width = slwf_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .drvtype_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .parked_bitmask = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) static const struct tegra_pingroup tegra30_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) /* pg_name, f0, f1, f2, f3, r, od, ior */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, 0x331c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, 0x317c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, GMI, 0x3358, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, GMI, 0x3364, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, GMI, 0x335c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, GMI, 0x3360, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) PINGROUP(sdmmc3_clk_pa6, UARTA, PWM2, SDMMC3, SPI3, 0x3390, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) PINGROUP(sdmmc3_cmd_pa7, UARTA, PWM3, SDMMC3, SPI2, 0x3394, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) PINGROUP(gmi_a17_pb0, UARTD, SPI4, GMI, DTV, 0x3234, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) PINGROUP(gmi_a18_pb1, UARTD, SPI4, GMI, DTV, 0x3238, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) PINGROUP(lcd_pwr0_pb2, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3090, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) PINGROUP(lcd_pclk_pb3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3094, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) PINGROUP(sdmmc3_dat3_pb4, RSVD1, PWM0, SDMMC3, SPI3, 0x33a4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) PINGROUP(sdmmc3_dat2_pb5, RSVD1, PWM1, SDMMC3, SPI3, 0x33a0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) PINGROUP(sdmmc3_dat1_pb6, RSVD1, RSVD2, SDMMC3, SPI3, 0x339c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) PINGROUP(sdmmc3_dat0_pb7, RSVD1, RSVD2, SDMMC3, SPI3, 0x3398, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, GMI, RSVD4, 0x3180, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) PINGROUP(lcd_pwr1_pc1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3070, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) PINGROUP(uart2_txd_pc2, UARTB, SPDIF, UARTA, SPI4, 0x3168, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) PINGROUP(uart2_rxd_pc3, UARTB, SPDIF, UARTA, SPI4, 0x3164, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) PINGROUP(lcd_pwr2_pc6, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3074, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) PINGROUP(sdmmc3_dat5_pd0, PWM0, SPI4, SDMMC3, SPI2, 0x33ac, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) PINGROUP(sdmmc3_dat4_pd1, PWM1, SPI4, SDMMC3, SPI2, 0x33a8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) PINGROUP(lcd_dc1_pd2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x310c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) PINGROUP(sdmmc3_dat6_pd3, SPDIF, SPI4, SDMMC3, SPI2, 0x33b0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) PINGROUP(sdmmc3_dat7_pd4, SPDIF, SPI4, SDMMC3, SPI2, 0x33b4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) PINGROUP(lcd_d0_pe0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) PINGROUP(lcd_d1_pe1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) PINGROUP(lcd_d2_pe2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ac, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) PINGROUP(lcd_d3_pe3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) PINGROUP(lcd_d4_pe4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) PINGROUP(lcd_d5_pe5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30b8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) PINGROUP(lcd_d6_pe6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30bc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) PINGROUP(lcd_d7_pe7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) PINGROUP(lcd_d8_pf0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) PINGROUP(lcd_d9_pf1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30c8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) PINGROUP(lcd_d10_pf2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30cc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) PINGROUP(lcd_d11_pf3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) PINGROUP(lcd_d12_pf4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) PINGROUP(lcd_d13_pf5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30d8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) PINGROUP(lcd_d14_pf6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30dc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) PINGROUP(lcd_d15_pf7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, RSVD4, 0x3214, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, RSVD4, 0x3218, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, RSVD4, 0x321c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) PINGROUP(gmi_ad12_ph4, RSVD1, NAND, GMI, RSVD4, 0x3220, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) PINGROUP(gmi_ad13_ph5, RSVD1, NAND, GMI, RSVD4, 0x3224, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) PINGROUP(gmi_ad14_ph6, RSVD1, NAND, GMI, RSVD4, 0x3228, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) PINGROUP(gmi_ad15_ph7, RSVD1, NAND, GMI, RSVD4, 0x322c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, RSVD4, 0x3240, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, RSVD4, 0x3244, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) PINGROUP(gmi_dqs_pi2, RSVD1, NAND, GMI, RSVD4, 0x3248, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SATA, 0x31e8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, 0x324c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) PINGROUP(gmi_iordy_pi5, RSVD1, NAND, GMI, RSVD4, 0x31c4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, GMI_ALT, 0x31ec, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) PINGROUP(gmi_wait_pi7, RSVD1, NAND, GMI, RSVD4, 0x31c8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, DTV, 0x31d4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) PINGROUP(lcd_de_pj1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3098, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, DTV, 0x31d8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) PINGROUP(lcd_hsync_pj3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x309c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) PINGROUP(lcd_vsync_pj4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30a0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) PINGROUP(gmi_a16_pj7, UARTD, SPI4, GMI, GMI_ALT, 0x3230, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, RSVD4, 0x31cc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) PINGROUP(gmi_clk_pk1, RSVD1, NAND, GMI, RSVD4, 0x31d0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) PINGROUP(gmi_cs4_n_pk2, RSVD1, NAND, GMI, RSVD4, 0x31e4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) PINGROUP(gmi_cs2_n_pk3, RSVD1, NAND, GMI, RSVD4, 0x31dc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) PINGROUP(gmi_cs3_n_pk4, RSVD1, NAND, GMI, GMI_ALT, 0x31e0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) PINGROUP(spdif_out_pk5, SPDIF, RSVD2, I2C1, SDMMC2, 0x3354, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) PINGROUP(spdif_in_pk6, SPDIF, HDA, I2C1, SDMMC2, 0x3350, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, RSVD4, 0x323c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) PINGROUP(vi_d9_pl7, DDR, SDMMC2, VI, RSVD4, 0x3148, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) PINGROUP(lcd_d16_pm0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) PINGROUP(lcd_d17_pm1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30e8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) PINGROUP(lcd_d18_pm2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30ec, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) PINGROUP(lcd_d19_pm3, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) PINGROUP(lcd_d20_pm4, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) PINGROUP(lcd_d21_pm5, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30f8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) PINGROUP(lcd_d22_pm6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x30fc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) PINGROUP(lcd_d23_pm7, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3100, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, SDMMC2, 0x3338, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, SDMMC2, 0x333c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SDMMC2, 0x3340, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, SDMMC2, 0x3344, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) PINGROUP(lcd_cs0_n_pn4, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3084, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) PINGROUP(lcd_sdout_pn5, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x307c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) PINGROUP(lcd_dc0_pn6, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3088, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) PINGROUP(hdmi_int_pn7, HDMI, RSVD2, RSVD3, RSVD4, 0x3110, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) PINGROUP(dap3_fs_pp0, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3030, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) PINGROUP(dap3_din_pp1, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3034, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) PINGROUP(dap3_dout_pp2, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x3038, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) PINGROUP(dap3_sclk_pp3, I2S2, RSVD2, DISPLAYA, DISPLAYB, 0x303c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) PINGROUP(dap4_fs_pp4, I2S3, RSVD2, GMI, RSVD4, 0x31a8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) PINGROUP(dap4_din_pp5, I2S3, RSVD2, GMI, RSVD4, 0x31ac, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) PINGROUP(dap4_dout_pp6, I2S3, RSVD2, GMI, RSVD4, 0x31b0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, GMI, RSVD4, 0x31b4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) PINGROUP(kb_col0_pq0, KBC, NAND, TRACE, TEST, 0x32fc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) PINGROUP(kb_col1_pq1, KBC, NAND, TRACE, TEST, 0x3300, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) PINGROUP(kb_col2_pq2, KBC, NAND, TRACE, RSVD4, 0x3304, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) PINGROUP(kb_col3_pq3, KBC, NAND, TRACE, RSVD4, 0x3308, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) PINGROUP(kb_col4_pq4, KBC, NAND, TRACE, RSVD4, 0x330c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) PINGROUP(kb_col5_pq5, KBC, NAND, TRACE, RSVD4, 0x3310, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) PINGROUP(kb_col6_pq6, KBC, NAND, TRACE, MIO, 0x3314, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) PINGROUP(kb_col7_pq7, KBC, NAND, TRACE, MIO, 0x3318, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) PINGROUP(kb_row0_pr0, KBC, NAND, RSVD3, RSVD4, 0x32bc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) PINGROUP(kb_row1_pr1, KBC, NAND, RSVD3, RSVD4, 0x32c0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) PINGROUP(kb_row2_pr2, KBC, NAND, RSVD3, RSVD4, 0x32c4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) PINGROUP(kb_row3_pr3, KBC, NAND, RSVD3, INVALID, 0x32c8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) PINGROUP(kb_row4_pr4, KBC, NAND, TRACE, RSVD4, 0x32cc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) PINGROUP(kb_row5_pr5, KBC, NAND, TRACE, OWR, 0x32d0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) PINGROUP(kb_row6_pr6, KBC, NAND, SDMMC2, MIO, 0x32d4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) PINGROUP(kb_row7_pr7, KBC, NAND, SDMMC2, MIO, 0x32d8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) PINGROUP(kb_row8_ps0, KBC, NAND, SDMMC2, MIO, 0x32dc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) PINGROUP(kb_row9_ps1, KBC, NAND, SDMMC2, MIO, 0x32e0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) PINGROUP(kb_row10_ps2, KBC, NAND, SDMMC2, MIO, 0x32e4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) PINGROUP(kb_row11_ps3, KBC, NAND, SDMMC2, MIO, 0x32e8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) PINGROUP(kb_row12_ps4, KBC, NAND, SDMMC2, MIO, 0x32ec, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) PINGROUP(kb_row13_ps5, KBC, NAND, SDMMC2, MIO, 0x32f0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) PINGROUP(kb_row14_ps6, KBC, NAND, SDMMC2, MIO, 0x32f4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) PINGROUP(kb_row15_ps7, KBC, NAND, SDMMC2, MIO, 0x32f8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) PINGROUP(vi_pclk_pt0, RSVD1, SDMMC2, VI, RSVD4, 0x3154, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) PINGROUP(vi_mclk_pt1, VI, VI_ALT1, VI_ALT2, VI_ALT3, 0x3158, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) PINGROUP(vi_d10_pt2, DDR, RSVD2, VI, RSVD4, 0x314c, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) PINGROUP(vi_d11_pt3, DDR, RSVD2, VI, RSVD4, 0x3150, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) PINGROUP(vi_d0_pt4, DDR, RSVD2, VI, RSVD4, 0x3124, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) PINGROUP(gen2_i2c_scl_pt5, I2C2, HDCP, GMI, RSVD4, 0x3250, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) PINGROUP(gen2_i2c_sda_pt6, I2C2, HDCP, GMI, RSVD4, 0x3254, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) PINGROUP(sdmmc4_cmd_pt7, I2C3, NAND, GMI, SDMMC4, 0x325c, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) PINGROUP(pu3, PWM0, UARTA, GMI, RSVD4, 0x3190, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) PINGROUP(pu4, PWM1, UARTA, GMI, RSVD4, 0x3194, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) PINGROUP(pu5, PWM2, UARTA, GMI, RSVD4, 0x3198, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) PINGROUP(pu6, PWM3, UARTA, GMI, RSVD4, 0x319c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) PINGROUP(jtag_rtck_pu7, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) PINGROUP(pv2, OWR, RSVD2, RSVD3, RSVD4, 0x3060, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) PINGROUP(pv3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4, 0x3064, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) PINGROUP(crt_hsync_pv6, CRT, RSVD2, RSVD3, RSVD4, 0x311c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) PINGROUP(crt_vsync_pv7, CRT, RSVD2, RSVD3, RSVD4, 0x3120, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) PINGROUP(lcd_cs1_n_pw0, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3104, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) PINGROUP(lcd_m1_pw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x3108, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) PINGROUP(spi2_cs1_n_pw2, SPI3, SPI2, SPI2_ALT, I2C1, 0x3388, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) PINGROUP(spi2_cs2_n_pw3, SPI3, SPI2, SPI2_ALT, I2C1, 0x338c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) PINGROUP(clk1_out_pw4, EXTPERIPH1, RSVD2, RSVD3, RSVD4, 0x334c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, RSVD4, 0x3174, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, RSVD4, 0x3178, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) PINGROUP(spi2_mosi_px0, SPI6, SPI2, SPI3, GMI, 0x3368, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) PINGROUP(spi2_miso_px1, SPI6, SPI2, SPI3, GMI, 0x336c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) PINGROUP(spi2_sck_px2, SPI6, SPI2, SPI3, GMI, 0x3374, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) PINGROUP(spi2_cs0_n_px3, SPI6, SPI2, SPI3, GMI, 0x3370, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) PINGROUP(spi1_mosi_px4, SPI2, SPI1, SPI2_ALT, GMI, 0x3378, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) PINGROUP(spi1_sck_px5, SPI2, SPI1, SPI2_ALT, GMI, 0x337c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) PINGROUP(spi1_cs0_n_px6, SPI2, SPI1, SPI2_ALT, GMI, 0x3380, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) PINGROUP(spi1_miso_px7, SPI3, SPI1, SPI2_ALT, RSVD4, 0x3384, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) PINGROUP(ulpi_clk_py0, SPI1, RSVD2, UARTD, ULPI, 0x3020, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) PINGROUP(ulpi_dir_py1, SPI1, RSVD2, UARTD, ULPI, 0x3024, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) PINGROUP(ulpi_nxt_py2, SPI1, RSVD2, UARTD, ULPI, 0x3028, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) PINGROUP(ulpi_stp_py3, SPI1, RSVD2, UARTD, ULPI, 0x302c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) PINGROUP(sdmmc1_dat3_py4, SDMMC1, RSVD2, UARTE, UARTA, 0x3050, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) PINGROUP(sdmmc1_dat2_py5, SDMMC1, RSVD2, UARTE, UARTA, 0x3054, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) PINGROUP(sdmmc1_dat1_py6, SDMMC1, RSVD2, UARTE, UARTA, 0x3058, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, UARTE, UARTA, 0x305c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) PINGROUP(sdmmc1_clk_pz0, SDMMC1, RSVD2, RSVD3, UARTA, 0x3048, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) PINGROUP(sdmmc1_cmd_pz1, SDMMC1, RSVD2, RSVD3, UARTA, 0x304c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) PINGROUP(lcd_sdin_pz2, DISPLAYA, DISPLAYB, SPI5, RSVD4, 0x3078, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) PINGROUP(lcd_wr_n_pz3, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x3080, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) PINGROUP(lcd_sck_pz4, DISPLAYA, DISPLAYB, SPI5, HDCP, 0x308c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, 0x3320, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) PINGROUP(sdmmc4_dat0_paa0, UARTE, SPI3, GMI, SDMMC4, 0x3260, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) PINGROUP(sdmmc4_dat1_paa1, UARTE, SPI3, GMI, SDMMC4, 0x3264, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) PINGROUP(sdmmc4_dat2_paa2, UARTE, SPI3, GMI, SDMMC4, 0x3268, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) PINGROUP(sdmmc4_dat3_paa3, UARTE, SPI3, GMI, SDMMC4, 0x326c, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) PINGROUP(sdmmc4_dat4_paa4, I2C3, I2S4, GMI, SDMMC4, 0x3270, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) PINGROUP(sdmmc4_dat5_paa5, VGP3, I2S4, GMI, SDMMC4, 0x3274, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) PINGROUP(sdmmc4_dat6_paa6, VGP4, I2S4, GMI, SDMMC4, 0x3278, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) PINGROUP(sdmmc4_dat7_paa7, VGP5, I2S4, GMI, SDMMC4, 0x327c, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) PINGROUP(pbb0, I2S4, RSVD2, RSVD3, SDMMC4, 0x328c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC4, 0x3290, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC4, 0x3294, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC4, 0x3298, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC4, 0x329c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, SDMMC4, 0x32a0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, SDMMC4, 0x32a4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC4, 0x32a8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC4, 0x3284, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC4, 0x3288, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, 0x32ac, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) PINGROUP(sdmmc4_rst_n_pcc3, VGP6, RSVD2, RSVD3, SDMMC4, 0x3280, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) PINGROUP(sdmmc4_clk_pcc4, INVALID, NAND, GMI, SDMMC4, 0x3258, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) PINGROUP(pex_l2_rst_n_pcc6, PCIE, HDA, RSVD3, RSVD4, 0x33d8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) PINGROUP(pex_l2_clkreq_n_pcc7, PCIE, HDA, RSVD3, RSVD4, 0x33dc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) PINGROUP(pex_l0_prsnt_n_pdd0, PCIE, HDA, RSVD3, RSVD4, 0x33b8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) PINGROUP(pex_l0_rst_n_pdd1, PCIE, HDA, RSVD3, RSVD4, 0x33bc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) PINGROUP(pex_l0_clkreq_n_pdd2, PCIE, HDA, RSVD3, RSVD4, 0x33c0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) PINGROUP(pex_wake_n_pdd3, PCIE, HDA, RSVD3, RSVD4, 0x33c4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) PINGROUP(pex_l1_prsnt_n_pdd4, PCIE, HDA, RSVD3, RSVD4, 0x33c8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) PINGROUP(pex_l1_rst_n_pdd5, PCIE, HDA, RSVD3, RSVD4, 0x33cc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) PINGROUP(pex_l1_clkreq_n_pdd6, PCIE, HDA, RSVD3, RSVD4, 0x33d0, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) PINGROUP(pex_l2_prsnt_n_pdd7, PCIE, HDA, RSVD3, RSVD4, 0x33d4, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) PINGROUP(clk1_req_pee2, DAP, HDA, RSVD3, RSVD4, 0x3348, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) PINGROUP(clk_32k_in, CLK_32K_IN, RSVD2, RSVD3, RSVD4, 0x3330, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) PINGROUP(core_pwr_req, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3324, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) PINGROUP(cpu_pwr_req, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4, 0x3328, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) PINGROUP(owr, OWR, CEC, RSVD3, RSVD4, 0x3334, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) PINGROUP(pwr_int_n, PWR_INT_N, RSVD2, RSVD3, RSVD4, 0x332c, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) DRV_PINGROUP(at1, 0x870, 2, 3, 4, 14, 5, 19, 5, 24, 2, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) DRV_PINGROUP(at2, 0x874, 2, 3, 4, 14, 5, 19, 5, 24, 2, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) DRV_PINGROUP(at3, 0x878, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) DRV_PINGROUP(crt, 0x8f8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) DRV_PINGROUP(csus, 0x88c, -1, -1, -1, 12, 5, 19, 5, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) DRV_PINGROUP(gma, 0x900, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) DRV_PINGROUP(gmb, 0x904, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) DRV_PINGROUP(gmc, 0x908, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) DRV_PINGROUP(gmd, 0x90c, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) DRV_PINGROUP(lcd1, 0x8a4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) DRV_PINGROUP(lcd2, 0x8a8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) DRV_PINGROUP(sdio2, 0x8ac, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) DRV_PINGROUP(vi1, 0x8c8, -1, -1, -1, 14, 5, 19, 5, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .ngpios = NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .gpio_compatible = "nvidia,tegra30-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .pins = tegra30_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .npins = ARRAY_SIZE(tegra30_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .functions = tegra30_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .nfunctions = ARRAY_SIZE(tegra30_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .groups = tegra30_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .ngroups = ARRAY_SIZE(tegra30_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .hsm_in_mux = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .schmitt_in_mux = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .drvtype_in_mux = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static int tegra30_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) static const struct of_device_id tegra30_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) { .compatible = "nvidia,tegra30-pinmux", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static struct platform_driver tegra30_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .name = "tegra30-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .of_match_table = tegra30_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .probe = tegra30_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) static int __init tegra30_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) return platform_driver_register(&tegra30_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) arch_initcall(tegra30_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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