^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pinctrl data for the NVIDIA Tegra210 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pinctrl-tegra.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Most pins affected by the pinmux can also be GPIOs. Define these first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * These must match how the GPIO driver names/numbers its pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define _GPIO(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA_PIN_PEX_WAKE_N_PA2 _GPIO(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA_PIN_PEX_L1_RST_N_PA3 _GPIO(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4 _GPIO(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA_PIN_SATA_LED_ACTIVE_PA5 _GPIO(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA_PIN_PA6 _GPIO(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_PIN_DAP1_FS_PB0 _GPIO(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA_PIN_DAP1_DIN_PB1 _GPIO(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA_PIN_DAP1_DOUT_PB2 _GPIO(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA_PIN_DAP1_SCLK_PB3 _GPIO(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA_PIN_SPI2_MOSI_PB4 _GPIO(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA_PIN_SPI2_MISO_PB5 _GPIO(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_PIN_SPI2_SCK_PB6 _GPIO(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA_PIN_SPI2_CS0_PB7 _GPIO(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA_PIN_SPI1_MOSI_PC0 _GPIO(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA_PIN_SPI1_MISO_PC1 _GPIO(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA_PIN_SPI1_SCK_PC2 _GPIO(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA_PIN_SPI1_CS0_PC3 _GPIO(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA_PIN_SPI1_CS1_PC4 _GPIO(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA_PIN_SPI4_SCK_PC5 _GPIO(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA_PIN_SPI4_CS0_PC6 _GPIO(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA_PIN_SPI4_MOSI_PC7 _GPIO(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA_PIN_SPI4_MISO_PD0 _GPIO(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA_PIN_UART3_TX_PD1 _GPIO(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA_PIN_UART3_RX_PD2 _GPIO(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA_PIN_UART3_RTS_PD3 _GPIO(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA_PIN_UART3_CTS_PD4 _GPIO(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA_PIN_DMIC1_CLK_PE0 _GPIO(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA_PIN_DMIC1_DAT_PE1 _GPIO(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA_PIN_DMIC2_CLK_PE2 _GPIO(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA_PIN_DMIC2_DAT_PE3 _GPIO(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA_PIN_DMIC3_CLK_PE4 _GPIO(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA_PIN_DMIC3_DAT_PE5 _GPIO(37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA_PIN_PE6 _GPIO(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA_PIN_PE7 _GPIO(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA_PIN_GEN3_I2C_SCL_PF0 _GPIO(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA_PIN_GEN3_I2C_SDA_PF1 _GPIO(41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA_PIN_UART2_TX_PG0 _GPIO(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA_PIN_UART2_RX_PG1 _GPIO(49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA_PIN_UART2_RTS_PG2 _GPIO(50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA_PIN_UART2_CTS_PG3 _GPIO(51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA_PIN_WIFI_EN_PH0 _GPIO(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA_PIN_WIFI_RST_PH1 _GPIO(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA_PIN_WIFI_WAKE_AP_PH2 _GPIO(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA_PIN_AP_WAKE_BT_PH3 _GPIO(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA_PIN_BT_RST_PH4 _GPIO(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA_PIN_BT_WAKE_AP_PH5 _GPIO(61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA_PIN_PH6 _GPIO(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA_PIN_AP_WAKE_NFC_PH7 _GPIO(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA_PIN_NFC_EN_PI0 _GPIO(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA_PIN_NFC_INT_PI1 _GPIO(65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA_PIN_GPS_EN_PI2 _GPIO(66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA_PIN_GPS_RST_PI3 _GPIO(67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA_PIN_UART4_TX_PI4 _GPIO(68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA_PIN_UART4_RX_PI5 _GPIO(69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA_PIN_UART4_RTS_PI6 _GPIO(70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA_PIN_UART4_CTS_PI7 _GPIO(71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA_PIN_GEN1_I2C_SDA_PJ0 _GPIO(72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEGRA_PIN_GEN1_I2C_SCL_PJ1 _GPIO(73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA_PIN_GEN2_I2C_SCL_PJ2 _GPIO(74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA_PIN_GEN2_I2C_SDA_PJ3 _GPIO(75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA_PIN_DAP4_FS_PJ4 _GPIO(76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA_PIN_DAP4_DIN_PJ5 _GPIO(77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA_PIN_DAP4_DOUT_PJ6 _GPIO(78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA_PIN_DAP4_SCLK_PJ7 _GPIO(79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA_PIN_PK0 _GPIO(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEGRA_PIN_PK1 _GPIO(81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA_PIN_PK2 _GPIO(82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA_PIN_PK3 _GPIO(83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA_PIN_PK4 _GPIO(84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA_PIN_PK5 _GPIO(85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA_PIN_PK6 _GPIO(86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA_PIN_PK7 _GPIO(87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEGRA_PIN_PL0 _GPIO(88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA_PIN_PL1 _GPIO(89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA_PIN_SDMMC1_CLK_PM0 _GPIO(96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEGRA_PIN_SDMMC1_CMD_PM1 _GPIO(97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA_PIN_SDMMC1_DAT3_PM2 _GPIO(98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA_PIN_SDMMC1_DAT2_PM3 _GPIO(99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA_PIN_SDMMC1_DAT1_PM4 _GPIO(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA_PIN_SDMMC1_DAT0_PM5 _GPIO(101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA_PIN_SDMMC3_CLK_PP0 _GPIO(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA_PIN_SDMMC3_CMD_PP1 _GPIO(121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA_PIN_SDMMC3_DAT3_PP2 _GPIO(122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA_PIN_SDMMC3_DAT2_PP3 _GPIO(123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA_PIN_SDMMC3_DAT1_PP4 _GPIO(124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA_PIN_SDMMC3_DAT0_PP5 _GPIO(125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA_PIN_CAM1_MCLK_PS0 _GPIO(144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA_PIN_CAM2_MCLK_PS1 _GPIO(145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA_PIN_CAM_I2C_SCL_PS2 _GPIO(146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA_PIN_CAM_I2C_SDA_PS3 _GPIO(147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA_PIN_CAM_RST_PS4 _GPIO(148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA_PIN_CAM_AF_EN_PS5 _GPIO(149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA_PIN_CAM_FLASH_EN_PS6 _GPIO(150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA_PIN_CAM1_PWDN_PS7 _GPIO(151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA_PIN_CAM2_PWDN_PT0 _GPIO(152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA_PIN_CAM1_STROBE_PT1 _GPIO(153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA_PIN_UART1_TX_PU0 _GPIO(160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA_PIN_UART1_RX_PU1 _GPIO(161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA_PIN_UART1_RTS_PU2 _GPIO(162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA_PIN_UART1_CTS_PU3 _GPIO(163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA_PIN_LCD_BL_PWM_PV0 _GPIO(168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA_PIN_LCD_BL_EN_PV1 _GPIO(169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA_PIN_LCD_RST_PV2 _GPIO(170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA_PIN_LCD_GPIO1_PV3 _GPIO(171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA_PIN_LCD_GPIO2_PV4 _GPIO(172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA_PIN_AP_READY_PV5 _GPIO(173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA_PIN_TOUCH_RST_PV6 _GPIO(174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA_PIN_TOUCH_CLK_PV7 _GPIO(175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA_PIN_MODEM_WAKE_AP_PX0 _GPIO(184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA_PIN_TOUCH_INT_PX1 _GPIO(185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA_PIN_MOTION_INT_PX2 _GPIO(186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA_PIN_ALS_PROX_INT_PX3 _GPIO(187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA_PIN_TEMP_ALERT_PX4 _GPIO(188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA_PIN_BUTTON_POWER_ON_PX5 _GPIO(189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA_PIN_BUTTON_VOL_UP_PX6 _GPIO(190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA_PIN_BUTTON_VOL_DOWN_PX7 _GPIO(191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA_PIN_BUTTON_SLIDE_SW_PY0 _GPIO(192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA_PIN_BUTTON_HOME_PY1 _GPIO(193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA_PIN_LCD_TE_PY2 _GPIO(194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA_PIN_PWR_I2C_SCL_PY3 _GPIO(195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA_PIN_PWR_I2C_SDA_PY4 _GPIO(196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA_PIN_CLK_32K_OUT_PY5 _GPIO(197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA_PIN_PZ0 _GPIO(200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA_PIN_PZ1 _GPIO(201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA_PIN_PZ2 _GPIO(202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA_PIN_PZ3 _GPIO(203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA_PIN_PZ4 _GPIO(204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TEGRA_PIN_PZ5 _GPIO(205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA_PIN_DAP2_FS_PAA0 _GPIO(208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA_PIN_DAP2_SCLK_PAA1 _GPIO(209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA_PIN_DAP2_DIN_PAA2 _GPIO(210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TEGRA_PIN_DAP2_DOUT_PAA3 _GPIO(211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEGRA_PIN_AUD_MCLK_PBB0 _GPIO(216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TEGRA_PIN_DVFS_PWM_PBB1 _GPIO(217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA_PIN_DVFS_CLK_PBB2 _GPIO(218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TEGRA_PIN_GPIO_X1_AUD_PBB3 _GPIO(219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA_PIN_GPIO_X3_AUD_PBB4 _GPIO(220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TEGRA_PIN_HDMI_CEC_PCC0 _GPIO(224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TEGRA_PIN_HDMI_INT_DP_HPD_PCC1 _GPIO(225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TEGRA_PIN_SPDIF_OUT_PCC2 _GPIO(226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA_PIN_SPDIF_IN_PCC3 _GPIO(227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TEGRA_PIN_USB_VBUS_EN0_PCC4 _GPIO(228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TEGRA_PIN_USB_VBUS_EN1_PCC5 _GPIO(229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEGRA_PIN_DP_HPD0_PCC6 _GPIO(230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA_PIN_PCC7 _GPIO(231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA_PIN_SPI2_CS1_PDD0 _GPIO(232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA_PIN_QSPI_SCK_PEE0 _GPIO(240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA_PIN_QSPI_CS_N_PEE1 _GPIO(241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA_PIN_QSPI_IO0_PEE2 _GPIO(242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TEGRA_PIN_QSPI_IO1_PEE3 _GPIO(243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA_PIN_QSPI_IO2_PEE4 _GPIO(244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TEGRA_PIN_QSPI_IO3_PEE5 _GPIO(245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* All non-GPIO pins follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define _PIN(offset) (NUM_GPIOS + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Non-GPIO pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TEGRA_PIN_PWR_INT_N _PIN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TEGRA_PIN_CLK_32K_IN _PIN(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA_PIN_JTAG_RTCK _PIN(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA_PIN_BATT_BCL _PIN(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA_PIN_CLK_REQ _PIN(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TEGRA_PIN_SHUTDOWN _PIN(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct pinctrl_pin_desc tegra210_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N PA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N PA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N PA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N PA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N PA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(TEGRA_PIN_SATA_LED_ACTIVE_PA5, "SATA_LED_ACTIVE PA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(TEGRA_PIN_PA6, "PA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PB0, "DAP1_FS PB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PB1, "DAP1_DIN PB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PB2, "DAP1_DOUT PB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PB3, "DAP1_SCLK PB3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PB4, "SPI2_MOSI PB4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PB5, "SPI2_MISO PB5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PB6, "SPI2_SCK PB6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PB7, "SPI2_CS0 PB7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PC0, "SPI1_MOSI PC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PC1, "SPI1_MISO PC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PC2, "SPI1_SCK PC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PC3, "SPI1_CS0 PC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PC4, "SPI1_CS1 PC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(TEGRA_PIN_SPI4_SCK_PC5, "SPI4_SCK PC5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(TEGRA_PIN_SPI4_CS0_PC6, "SPI4_CS0 PC6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(TEGRA_PIN_SPI4_MOSI_PC7, "SPI4_MOSI PC7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(TEGRA_PIN_SPI4_MISO_PD0, "SPI4_MISO PD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(TEGRA_PIN_UART3_TX_PD1, "UART3_TX PD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(TEGRA_PIN_UART3_RX_PD2, "UART3_RX PD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PD3, "UART3_RTS PD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PD4, "UART3_CTS PD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PE0, "DMIC1_CLK PE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PE1, "DMIC1_DAT PE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PE2, "DMIC2_CLK PE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PE3, "DMIC2_DAT PE3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(TEGRA_PIN_DMIC3_CLK_PE4, "DMIC3_CLK PE4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(TEGRA_PIN_DMIC3_DAT_PE5, "DMIC3_DAT PE5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(TEGRA_PIN_PE6, "PE6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(TEGRA_PIN_PE7, "PE7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PF0, "GEN3_I2C_SCL PF0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PF1, "GEN3_I2C_SDA PF1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(TEGRA_PIN_UART2_TX_PG0, "UART2_TX PG0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(TEGRA_PIN_UART2_RX_PG1, "UART2_RX PG1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PG2, "UART2_RTS PG2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PG3, "UART2_CTS PG3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(TEGRA_PIN_WIFI_EN_PH0, "WIFI_EN PH0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(TEGRA_PIN_WIFI_RST_PH1, "WIFI_RST PH1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(TEGRA_PIN_WIFI_WAKE_AP_PH2, "WIFI_WAKE_AP PH2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(TEGRA_PIN_AP_WAKE_BT_PH3, "AP_WAKE_BT PH3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(TEGRA_PIN_BT_RST_PH4, "BT_RST PH4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(TEGRA_PIN_BT_WAKE_AP_PH5, "BT_WAKE_AP PH5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(TEGRA_PIN_AP_WAKE_NFC_PH7, "AP_WAKE_NFC PH7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(TEGRA_PIN_NFC_EN_PI0, "NFC_EN PI0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(TEGRA_PIN_NFC_INT_PI1, "NFC_INT PI1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(TEGRA_PIN_GPS_EN_PI2, "GPS_EN PI2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(TEGRA_PIN_GPS_RST_PI3, "GPS_RST PI3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(TEGRA_PIN_UART4_TX_PI4, "UART4_TX PI4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(TEGRA_PIN_UART4_RX_PI5, "UART4_RX PI5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PI6, "UART4_RTS PI6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PI7, "UART4_CTS PI7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PJ0, "GEN1_I2C_SDA PJ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PJ1, "GEN1_I2C_SCL PJ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PJ2, "GEN2_I2C_SCL PJ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PJ3, "GEN2_I2C_SDA PJ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PJ4, "DAP4_FS PJ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PJ5, "DAP4_DIN PJ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PJ6, "DAP4_DOUT PJ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PJ7, "DAP4_SCLK PJ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(TEGRA_PIN_PK5, "PK5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(TEGRA_PIN_PK6, "PK6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(TEGRA_PIN_PL0, "PL0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(TEGRA_PIN_PL1, "PL1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PM0, "SDMMC1_CLK PM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PM1, "SDMMC1_CMD PM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PM2, "SDMMC1_DAT3 PM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PM3, "SDMMC1_DAT2 PM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PM4, "SDMMC1_DAT1 PM4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PM5, "SDMMC1_DAT0 PM5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PP0, "SDMMC3_CLK PP0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PP1, "SDMMC3_CMD PP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PP2, "SDMMC3_DAT3 PP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PP3, "SDMMC3_DAT2 PP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PP4, "SDMMC3_DAT1 PP4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PP5, "SDMMC3_DAT0 PP5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(TEGRA_PIN_CAM1_MCLK_PS0, "CAM1_MCLK PS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(TEGRA_PIN_CAM2_MCLK_PS1, "CAM2_MCLK PS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PS2, "CAM_I2C_SCL PS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PS3, "CAM_I2C_SDA PS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(TEGRA_PIN_CAM_RST_PS4, "CAM_RST PS4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(TEGRA_PIN_CAM_AF_EN_PS5, "CAM_AF_EN PS5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(TEGRA_PIN_CAM_FLASH_EN_PS6, "CAM_FLASH_EN PS6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(TEGRA_PIN_CAM1_PWDN_PS7, "CAM1_PWDN PS7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(TEGRA_PIN_CAM2_PWDN_PT0, "CAM2_PWDN PT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(TEGRA_PIN_CAM1_STROBE_PT1, "CAM1_STROBE PT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(TEGRA_PIN_UART1_TX_PU0, "UART1_TX PU0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(TEGRA_PIN_UART1_RX_PU1, "UART1_RX PU1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PU2, "UART1_RTS PU2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PU3, "UART1_CTS PU3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(TEGRA_PIN_LCD_BL_PWM_PV0, "LCD_BL_PWM PV0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(TEGRA_PIN_LCD_BL_EN_PV1, "LCD_BL_EN PV1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(TEGRA_PIN_LCD_RST_PV2, "LCD_RST PV2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(TEGRA_PIN_LCD_GPIO1_PV3, "LCD_GPIO1 PV3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(TEGRA_PIN_LCD_GPIO2_PV4, "LCD_GPIO2 PV4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(TEGRA_PIN_AP_READY_PV5, "AP_READY PV5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(TEGRA_PIN_TOUCH_RST_PV6, "TOUCH_RST PV6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PV7, "TOUCH_CLK PV7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(TEGRA_PIN_MODEM_WAKE_AP_PX0, "MODEM_WAKE_AP PX0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(TEGRA_PIN_TOUCH_INT_PX1, "TOUCH_INT PX1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(TEGRA_PIN_MOTION_INT_PX2, "MOTION_INT PX2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(TEGRA_PIN_ALS_PROX_INT_PX3, "ALS_PROX_INT PX3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(TEGRA_PIN_TEMP_ALERT_PX4, "TEMP_ALERT PX4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(TEGRA_PIN_BUTTON_POWER_ON_PX5, "BUTTON_POWER_ON PX5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_UP_PX6, "BUTTON_VOL_UP PX6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_DOWN_PX7, "BUTTON_VOL_DOWN PX7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(TEGRA_PIN_BUTTON_SLIDE_SW_PY0, "BUTTON_SLIDE_SW PY0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(TEGRA_PIN_BUTTON_HOME_PY1, "BUTTON_HOME PY1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(TEGRA_PIN_LCD_TE_PY2, "LCD_TE PY2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PY3, "PWR_I2C_SCL PY3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PY4, "PWR_I2C_SDA PY4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PY5, "CLK_32K_OUT PY5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(TEGRA_PIN_PZ0, "PZ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(TEGRA_PIN_PZ1, "PZ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(TEGRA_PIN_PZ2, "PZ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(TEGRA_PIN_PZ3, "PZ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(TEGRA_PIN_PZ4, "PZ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(TEGRA_PIN_PZ5, "PZ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PAA0, "DAP2_FS PAA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PAA1, "DAP2_SCLK PAA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PAA2, "DAP2_DIN PAA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PAA3, "DAP2_DOUT PAA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PBB0, "AUD_MCLK PBB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PBB1, "DVFS_PWM PBB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PBB2, "DVFS_CLK PBB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PBB3, "GPIO_X1_AUD PBB3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PBB4, "GPIO_X3_AUD PBB4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PCC0, "HDMI_CEC PCC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, "HDMI_INT_DP_HPD PCC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PCC2, "SPDIF_OUT PCC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PCC3, "SPDIF_IN PCC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PCC4, "USB_VBUS_EN0 PCC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PCC5, "USB_VBUS_EN1 PCC5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(TEGRA_PIN_DP_HPD0_PCC6, "DP_HPD0 PCC6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(TEGRA_PIN_PCC7, "PCC7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PDD0, "SPI2_CS1 PDD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PEE0, "QSPI_SCK PEE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PEE1, "QSPI_CS_N PEE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PEE2, "QSPI_IO0 PEE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PEE3, "QSPI_IO1 PEE3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PEE4, "QSPI_IO2 PEE4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PEE5, "QSPI_IO3 PEE5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(TEGRA_PIN_BATT_BCL, "BATT_BCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(TEGRA_PIN_CLK_REQ, "CLK_REQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const unsigned pex_l0_rst_n_pa0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) TEGRA_PIN_PEX_L0_RST_N_PA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const unsigned pex_l0_clkreq_n_pa1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const unsigned pex_wake_n_pa2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) TEGRA_PIN_PEX_WAKE_N_PA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const unsigned pex_l1_rst_n_pa3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) TEGRA_PIN_PEX_L1_RST_N_PA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const unsigned pex_l1_clkreq_n_pa4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const unsigned sata_led_active_pa5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) TEGRA_PIN_SATA_LED_ACTIVE_PA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const unsigned pa6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) TEGRA_PIN_PA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const unsigned dap1_fs_pb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) TEGRA_PIN_DAP1_FS_PB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const unsigned dap1_din_pb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) TEGRA_PIN_DAP1_DIN_PB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const unsigned dap1_dout_pb2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) TEGRA_PIN_DAP1_DOUT_PB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const unsigned dap1_sclk_pb3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) TEGRA_PIN_DAP1_SCLK_PB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const unsigned spi2_mosi_pb4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) TEGRA_PIN_SPI2_MOSI_PB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const unsigned spi2_miso_pb5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) TEGRA_PIN_SPI2_MISO_PB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const unsigned spi2_sck_pb6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) TEGRA_PIN_SPI2_SCK_PB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const unsigned spi2_cs0_pb7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) TEGRA_PIN_SPI2_CS0_PB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const unsigned spi1_mosi_pc0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) TEGRA_PIN_SPI1_MOSI_PC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const unsigned spi1_miso_pc1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) TEGRA_PIN_SPI1_MISO_PC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const unsigned spi1_sck_pc2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) TEGRA_PIN_SPI1_SCK_PC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const unsigned spi1_cs0_pc3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) TEGRA_PIN_SPI1_CS0_PC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const unsigned spi1_cs1_pc4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) TEGRA_PIN_SPI1_CS1_PC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const unsigned spi4_sck_pc5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) TEGRA_PIN_SPI4_SCK_PC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const unsigned spi4_cs0_pc6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) TEGRA_PIN_SPI4_CS0_PC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const unsigned spi4_mosi_pc7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) TEGRA_PIN_SPI4_MOSI_PC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const unsigned spi4_miso_pd0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) TEGRA_PIN_SPI4_MISO_PD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const unsigned uart3_tx_pd1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) TEGRA_PIN_UART3_TX_PD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const unsigned uart3_rx_pd2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) TEGRA_PIN_UART3_RX_PD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const unsigned uart3_rts_pd3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) TEGRA_PIN_UART3_RTS_PD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const unsigned uart3_cts_pd4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) TEGRA_PIN_UART3_CTS_PD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const unsigned dmic1_clk_pe0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) TEGRA_PIN_DMIC1_CLK_PE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const unsigned dmic1_dat_pe1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) TEGRA_PIN_DMIC1_DAT_PE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const unsigned dmic2_clk_pe2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) TEGRA_PIN_DMIC2_CLK_PE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const unsigned dmic2_dat_pe3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) TEGRA_PIN_DMIC2_DAT_PE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const unsigned dmic3_clk_pe4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) TEGRA_PIN_DMIC3_CLK_PE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const unsigned dmic3_dat_pe5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) TEGRA_PIN_DMIC3_DAT_PE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const unsigned pe6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) TEGRA_PIN_PE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const unsigned pe7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) TEGRA_PIN_PE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const unsigned gen3_i2c_scl_pf0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) TEGRA_PIN_GEN3_I2C_SCL_PF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const unsigned gen3_i2c_sda_pf1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) TEGRA_PIN_GEN3_I2C_SDA_PF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const unsigned uart2_tx_pg0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) TEGRA_PIN_UART2_TX_PG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const unsigned uart2_rx_pg1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) TEGRA_PIN_UART2_RX_PG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const unsigned uart2_rts_pg2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) TEGRA_PIN_UART2_RTS_PG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const unsigned uart2_cts_pg3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) TEGRA_PIN_UART2_CTS_PG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const unsigned wifi_en_ph0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) TEGRA_PIN_WIFI_EN_PH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const unsigned wifi_rst_ph1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) TEGRA_PIN_WIFI_RST_PH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const unsigned wifi_wake_ap_ph2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) TEGRA_PIN_WIFI_WAKE_AP_PH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const unsigned ap_wake_bt_ph3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) TEGRA_PIN_AP_WAKE_BT_PH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const unsigned bt_rst_ph4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) TEGRA_PIN_BT_RST_PH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const unsigned bt_wake_ap_ph5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) TEGRA_PIN_BT_WAKE_AP_PH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const unsigned ph6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) TEGRA_PIN_PH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const unsigned ap_wake_nfc_ph7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) TEGRA_PIN_AP_WAKE_NFC_PH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const unsigned nfc_en_pi0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) TEGRA_PIN_NFC_EN_PI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const unsigned nfc_int_pi1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) TEGRA_PIN_NFC_INT_PI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const unsigned gps_en_pi2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) TEGRA_PIN_GPS_EN_PI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const unsigned gps_rst_pi3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) TEGRA_PIN_GPS_RST_PI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const unsigned uart4_tx_pi4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) TEGRA_PIN_UART4_TX_PI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const unsigned uart4_rx_pi5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) TEGRA_PIN_UART4_RX_PI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const unsigned uart4_rts_pi6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) TEGRA_PIN_UART4_RTS_PI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const unsigned uart4_cts_pi7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) TEGRA_PIN_UART4_CTS_PI7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const unsigned gen1_i2c_sda_pj0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) TEGRA_PIN_GEN1_I2C_SDA_PJ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const unsigned gen1_i2c_scl_pj1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) TEGRA_PIN_GEN1_I2C_SCL_PJ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const unsigned gen2_i2c_scl_pj2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) TEGRA_PIN_GEN2_I2C_SCL_PJ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const unsigned gen2_i2c_sda_pj3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) TEGRA_PIN_GEN2_I2C_SDA_PJ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const unsigned dap4_fs_pj4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) TEGRA_PIN_DAP4_FS_PJ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const unsigned dap4_din_pj5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) TEGRA_PIN_DAP4_DIN_PJ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const unsigned dap4_dout_pj6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) TEGRA_PIN_DAP4_DOUT_PJ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const unsigned dap4_sclk_pj7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) TEGRA_PIN_DAP4_SCLK_PJ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const unsigned pk0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) TEGRA_PIN_PK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const unsigned pk1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) TEGRA_PIN_PK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const unsigned pk2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) TEGRA_PIN_PK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const unsigned pk3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) TEGRA_PIN_PK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const unsigned pk4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) TEGRA_PIN_PK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const unsigned pk5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) TEGRA_PIN_PK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const unsigned pk6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) TEGRA_PIN_PK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const unsigned pk7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) TEGRA_PIN_PK7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const unsigned pl0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) TEGRA_PIN_PL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const unsigned pl1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) TEGRA_PIN_PL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const unsigned sdmmc1_clk_pm0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) TEGRA_PIN_SDMMC1_CLK_PM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const unsigned sdmmc1_cmd_pm1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) TEGRA_PIN_SDMMC1_CMD_PM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const unsigned sdmmc1_dat3_pm2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) TEGRA_PIN_SDMMC1_DAT3_PM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const unsigned sdmmc1_dat2_pm3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) TEGRA_PIN_SDMMC1_DAT2_PM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const unsigned sdmmc1_dat1_pm4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) TEGRA_PIN_SDMMC1_DAT1_PM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const unsigned sdmmc1_dat0_pm5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) TEGRA_PIN_SDMMC1_DAT0_PM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const unsigned sdmmc3_clk_pp0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) TEGRA_PIN_SDMMC3_CLK_PP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const unsigned sdmmc3_cmd_pp1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) TEGRA_PIN_SDMMC3_CMD_PP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const unsigned sdmmc3_dat3_pp2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) TEGRA_PIN_SDMMC3_DAT3_PP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const unsigned sdmmc3_dat2_pp3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) TEGRA_PIN_SDMMC3_DAT2_PP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const unsigned sdmmc3_dat1_pp4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) TEGRA_PIN_SDMMC3_DAT1_PP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const unsigned sdmmc3_dat0_pp5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) TEGRA_PIN_SDMMC3_DAT0_PP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const unsigned cam1_mclk_ps0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) TEGRA_PIN_CAM1_MCLK_PS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const unsigned cam2_mclk_ps1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) TEGRA_PIN_CAM2_MCLK_PS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static const unsigned cam_i2c_scl_ps2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) TEGRA_PIN_CAM_I2C_SCL_PS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const unsigned cam_i2c_sda_ps3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) TEGRA_PIN_CAM_I2C_SDA_PS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const unsigned cam_rst_ps4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) TEGRA_PIN_CAM_RST_PS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const unsigned cam_af_en_ps5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) TEGRA_PIN_CAM_AF_EN_PS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const unsigned cam_flash_en_ps6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) TEGRA_PIN_CAM_FLASH_EN_PS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const unsigned cam1_pwdn_ps7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) TEGRA_PIN_CAM1_PWDN_PS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const unsigned cam2_pwdn_pt0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) TEGRA_PIN_CAM2_PWDN_PT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const unsigned cam1_strobe_pt1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) TEGRA_PIN_CAM1_STROBE_PT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const unsigned uart1_tx_pu0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) TEGRA_PIN_UART1_TX_PU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const unsigned uart1_rx_pu1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) TEGRA_PIN_UART1_RX_PU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const unsigned uart1_rts_pu2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) TEGRA_PIN_UART1_RTS_PU2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const unsigned uart1_cts_pu3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) TEGRA_PIN_UART1_CTS_PU3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const unsigned lcd_bl_pwm_pv0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) TEGRA_PIN_LCD_BL_PWM_PV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const unsigned lcd_bl_en_pv1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) TEGRA_PIN_LCD_BL_EN_PV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const unsigned lcd_rst_pv2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) TEGRA_PIN_LCD_RST_PV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const unsigned lcd_gpio1_pv3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) TEGRA_PIN_LCD_GPIO1_PV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const unsigned lcd_gpio2_pv4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) TEGRA_PIN_LCD_GPIO2_PV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const unsigned ap_ready_pv5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) TEGRA_PIN_AP_READY_PV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const unsigned touch_rst_pv6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) TEGRA_PIN_TOUCH_RST_PV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const unsigned touch_clk_pv7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TEGRA_PIN_TOUCH_CLK_PV7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const unsigned modem_wake_ap_px0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) TEGRA_PIN_MODEM_WAKE_AP_PX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const unsigned touch_int_px1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) TEGRA_PIN_TOUCH_INT_PX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const unsigned motion_int_px2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TEGRA_PIN_MOTION_INT_PX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static const unsigned als_prox_int_px3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) TEGRA_PIN_ALS_PROX_INT_PX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const unsigned temp_alert_px4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) TEGRA_PIN_TEMP_ALERT_PX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const unsigned button_power_on_px5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) TEGRA_PIN_BUTTON_POWER_ON_PX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const unsigned button_vol_up_px6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) TEGRA_PIN_BUTTON_VOL_UP_PX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const unsigned button_vol_down_px7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) TEGRA_PIN_BUTTON_VOL_DOWN_PX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const unsigned button_slide_sw_py0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) TEGRA_PIN_BUTTON_SLIDE_SW_PY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const unsigned button_home_py1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) TEGRA_PIN_BUTTON_HOME_PY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const unsigned lcd_te_py2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) TEGRA_PIN_LCD_TE_PY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static const unsigned pwr_i2c_scl_py3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) TEGRA_PIN_PWR_I2C_SCL_PY3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const unsigned pwr_i2c_sda_py4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TEGRA_PIN_PWR_I2C_SDA_PY4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const unsigned clk_32k_out_py5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TEGRA_PIN_CLK_32K_OUT_PY5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const unsigned pz0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) TEGRA_PIN_PZ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const unsigned pz1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) TEGRA_PIN_PZ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const unsigned pz2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) TEGRA_PIN_PZ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const unsigned pz3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) TEGRA_PIN_PZ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const unsigned pz4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) TEGRA_PIN_PZ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const unsigned pz5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) TEGRA_PIN_PZ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const unsigned dap2_fs_paa0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) TEGRA_PIN_DAP2_FS_PAA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static const unsigned dap2_sclk_paa1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) TEGRA_PIN_DAP2_SCLK_PAA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const unsigned dap2_din_paa2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) TEGRA_PIN_DAP2_DIN_PAA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static const unsigned dap2_dout_paa3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) TEGRA_PIN_DAP2_DOUT_PAA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const unsigned aud_mclk_pbb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) TEGRA_PIN_AUD_MCLK_PBB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const unsigned dvfs_pwm_pbb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) TEGRA_PIN_DVFS_PWM_PBB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const unsigned dvfs_clk_pbb2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) TEGRA_PIN_DVFS_CLK_PBB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static const unsigned gpio_x1_aud_pbb3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) TEGRA_PIN_GPIO_X1_AUD_PBB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static const unsigned gpio_x3_aud_pbb4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) TEGRA_PIN_GPIO_X3_AUD_PBB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const unsigned hdmi_cec_pcc0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) TEGRA_PIN_HDMI_CEC_PCC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const unsigned hdmi_int_dp_hpd_pcc1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) TEGRA_PIN_HDMI_INT_DP_HPD_PCC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static const unsigned spdif_out_pcc2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) TEGRA_PIN_SPDIF_OUT_PCC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const unsigned spdif_in_pcc3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) TEGRA_PIN_SPDIF_IN_PCC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static const unsigned usb_vbus_en0_pcc4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) TEGRA_PIN_USB_VBUS_EN0_PCC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const unsigned usb_vbus_en1_pcc5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) TEGRA_PIN_USB_VBUS_EN1_PCC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static const unsigned dp_hpd0_pcc6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) TEGRA_PIN_DP_HPD0_PCC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const unsigned pcc7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) TEGRA_PIN_PCC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const unsigned spi2_cs1_pdd0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) TEGRA_PIN_SPI2_CS1_PDD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const unsigned qspi_sck_pee0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) TEGRA_PIN_QSPI_SCK_PEE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static const unsigned qspi_cs_n_pee1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) TEGRA_PIN_QSPI_CS_N_PEE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const unsigned qspi_io0_pee2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) TEGRA_PIN_QSPI_IO0_PEE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const unsigned qspi_io1_pee3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) TEGRA_PIN_QSPI_IO1_PEE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const unsigned qspi_io2_pee4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) TEGRA_PIN_QSPI_IO2_PEE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const unsigned qspi_io3_pee5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) TEGRA_PIN_QSPI_IO3_PEE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const unsigned core_pwr_req_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) TEGRA_PIN_CORE_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const unsigned cpu_pwr_req_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) TEGRA_PIN_CPU_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const unsigned pwr_int_n_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) TEGRA_PIN_PWR_INT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static const unsigned clk_32k_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) TEGRA_PIN_CLK_32K_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static const unsigned jtag_rtck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) TEGRA_PIN_JTAG_RTCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const unsigned batt_bcl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) TEGRA_PIN_BATT_BCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const unsigned clk_req_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) TEGRA_PIN_CLK_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static const unsigned shutdown_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) TEGRA_PIN_SHUTDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const unsigned drive_pa6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) TEGRA_PIN_PA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const unsigned drive_pcc7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) TEGRA_PIN_PCC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static const unsigned drive_pe6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) TEGRA_PIN_PE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const unsigned drive_pe7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) TEGRA_PIN_PE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static const unsigned drive_ph6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) TEGRA_PIN_PH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static const unsigned drive_pk0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) TEGRA_PIN_PK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static const unsigned drive_pk1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) TEGRA_PIN_PK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static const unsigned drive_pk2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) TEGRA_PIN_PK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const unsigned drive_pk3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) TEGRA_PIN_PK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const unsigned drive_pk4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) TEGRA_PIN_PK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const unsigned drive_pk5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) TEGRA_PIN_PK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const unsigned drive_pk6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) TEGRA_PIN_PK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static const unsigned drive_pk7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) TEGRA_PIN_PK7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const unsigned drive_pl0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) TEGRA_PIN_PL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static const unsigned drive_pl1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) TEGRA_PIN_PL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const unsigned drive_pz0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) TEGRA_PIN_PZ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static const unsigned drive_pz1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) TEGRA_PIN_PZ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static const unsigned drive_pz2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) TEGRA_PIN_PZ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static const unsigned drive_pz3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) TEGRA_PIN_PZ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static const unsigned drive_pz4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) TEGRA_PIN_PZ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static const unsigned drive_pz5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) TEGRA_PIN_PZ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static const unsigned drive_sdmmc1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) TEGRA_PIN_SDMMC1_CLK_PM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) TEGRA_PIN_SDMMC1_CMD_PM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) TEGRA_PIN_SDMMC1_DAT3_PM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) TEGRA_PIN_SDMMC1_DAT2_PM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) TEGRA_PIN_SDMMC1_DAT1_PM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) TEGRA_PIN_SDMMC1_DAT0_PM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const unsigned drive_sdmmc2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static const unsigned drive_sdmmc3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) TEGRA_PIN_SDMMC3_CLK_PP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) TEGRA_PIN_SDMMC3_CMD_PP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) TEGRA_PIN_SDMMC3_DAT3_PP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) TEGRA_PIN_SDMMC3_DAT2_PP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) TEGRA_PIN_SDMMC3_DAT1_PP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) TEGRA_PIN_SDMMC3_DAT0_PP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const unsigned drive_sdmmc4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) enum tegra_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) TEGRA_MUX_AUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) TEGRA_MUX_BCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) TEGRA_MUX_BLINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) TEGRA_MUX_CCLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) TEGRA_MUX_CEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) TEGRA_MUX_CLDVFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) TEGRA_MUX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) TEGRA_MUX_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) TEGRA_MUX_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) TEGRA_MUX_DISPLAYA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) TEGRA_MUX_DISPLAYB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) TEGRA_MUX_DMIC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) TEGRA_MUX_DMIC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) TEGRA_MUX_DMIC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) TEGRA_MUX_DP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) TEGRA_MUX_DTV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) TEGRA_MUX_EXTPERIPH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) TEGRA_MUX_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) TEGRA_MUX_I2C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) TEGRA_MUX_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) TEGRA_MUX_I2CPMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) TEGRA_MUX_I2CVI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) TEGRA_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) TEGRA_MUX_I2S2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) TEGRA_MUX_I2S3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) TEGRA_MUX_I2S4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) TEGRA_MUX_I2S4B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) TEGRA_MUX_I2S5A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) TEGRA_MUX_I2S5B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) TEGRA_MUX_IQC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) TEGRA_MUX_IQC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) TEGRA_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) TEGRA_MUX_PE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) TEGRA_MUX_PE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) TEGRA_MUX_PE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) TEGRA_MUX_PMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) TEGRA_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) TEGRA_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) TEGRA_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) TEGRA_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) TEGRA_MUX_QSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) TEGRA_MUX_RSVD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) TEGRA_MUX_RSVD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) TEGRA_MUX_RSVD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) TEGRA_MUX_RSVD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) TEGRA_MUX_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) TEGRA_MUX_SDMMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) TEGRA_MUX_SDMMC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) TEGRA_MUX_SHUTDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) TEGRA_MUX_SOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) TEGRA_MUX_SOR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) TEGRA_MUX_SOR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) TEGRA_MUX_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) TEGRA_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) TEGRA_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) TEGRA_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) TEGRA_MUX_SPI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) TEGRA_MUX_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) TEGRA_MUX_TOUCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) TEGRA_MUX_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) TEGRA_MUX_UARTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) TEGRA_MUX_UARTB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) TEGRA_MUX_UARTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) TEGRA_MUX_UARTD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) TEGRA_MUX_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) TEGRA_MUX_VGP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) TEGRA_MUX_VGP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) TEGRA_MUX_VGP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) TEGRA_MUX_VGP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) TEGRA_MUX_VGP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) TEGRA_MUX_VGP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) TEGRA_MUX_VIMCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) TEGRA_MUX_VIMCLK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static struct tegra_function tegra210_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) FUNCTION(aud),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) FUNCTION(bcl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) FUNCTION(blink),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) FUNCTION(ccla),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) FUNCTION(cec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) FUNCTION(cldvfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) FUNCTION(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) FUNCTION(core),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) FUNCTION(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) FUNCTION(displaya),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) FUNCTION(displayb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) FUNCTION(dmic1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) FUNCTION(dmic2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) FUNCTION(dmic3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) FUNCTION(dp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) FUNCTION(dtv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) FUNCTION(extperiph3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) FUNCTION(i2cpmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) FUNCTION(i2cvi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) FUNCTION(i2s1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) FUNCTION(i2s2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) FUNCTION(i2s3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) FUNCTION(i2s4a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) FUNCTION(i2s4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) FUNCTION(i2s5a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) FUNCTION(i2s5b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) FUNCTION(iqc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) FUNCTION(iqc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) FUNCTION(jtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) FUNCTION(pe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) FUNCTION(pe0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) FUNCTION(pe1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) FUNCTION(pmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) FUNCTION(qspi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) FUNCTION(rsvd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) FUNCTION(rsvd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) FUNCTION(rsvd2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) FUNCTION(rsvd3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) FUNCTION(sata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) FUNCTION(sdmmc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) FUNCTION(sdmmc3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) FUNCTION(shutdown),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) FUNCTION(soc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) FUNCTION(sor0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) FUNCTION(sor1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) FUNCTION(spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) FUNCTION(spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) FUNCTION(spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) FUNCTION(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) FUNCTION(spi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) FUNCTION(sys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) FUNCTION(touch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) FUNCTION(uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) FUNCTION(uarta),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) FUNCTION(uartb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) FUNCTION(uartc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) FUNCTION(uartd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) FUNCTION(usb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) FUNCTION(vgp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) FUNCTION(vgp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) FUNCTION(vgp3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) FUNCTION(vgp4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) FUNCTION(vgp5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) FUNCTION(vgp6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) FUNCTION(vimclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) FUNCTION(vimclk2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define PINGROUP_REG_A 0x3000 /* bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define PINGROUP_BIT_Y(b) (b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define PINGROUP_BIT_N(b) (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define PINGROUP(pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) slwr_w, slwf_b, slwf_w) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .funcs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) TEGRA_MUX_##f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) TEGRA_MUX_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) TEGRA_MUX_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) TEGRA_MUX_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .mux_reg = PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .mux_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .mux_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .pupd_reg = PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .pupd_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .pupd_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .tri_reg = PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .tri_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .tri_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .einput_bit = 6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .odrain_bit = 11, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .lock_bit = 7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .ioreset_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .hsm_bit = PINGROUP_BIT_##hsm(9), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .schmitt_bit = 12, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .drvtype_bit = PINGROUP_BIT_##drvtype(13), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .drv_reg = DRV_PINGROUP_REG(rdrv), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .drv_bank = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .lpmd_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .drvdn_bit = drvdn_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .drvdn_width = drvdn_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .drvup_bit = drvup_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .drvup_width = drvup_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .slwr_bit = slwr_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .slwr_width = slwr_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .slwf_bit = slwf_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .slwf_width = slwf_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .parked_bitmask = BIT(5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define DRV_PINGROUP(pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) drvup_w, slwr_b, slwr_w, slwf_b, slwf_w) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .name = "drive_" #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .pins = drive_##pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .mux_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .pupd_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .tri_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .einput_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .odrain_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .lock_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .ioreset_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .rcv_sel_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .drv_reg = DRV_PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .drv_bank = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .hsm_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .schmitt_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .lpmd_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .drvdn_bit = drvdn_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .drvdn_width = drvdn_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .drvup_bit = drvup_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .drvup_width = drvup_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .slwr_bit = slwr_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .slwr_width = slwr_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .slwf_bit = slwf_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .slwf_width = slwf_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .drvtype_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .parked_bitmask = prk_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static const struct tegra_pingroup tegra210_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PINGROUP(sdmmc1_dat2_pm3, SDMMC1, SPI3, RSVD2, RSVD3, 0x300c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINGROUP(sdmmc1_dat1_pm4, SDMMC1, SPI3, RSVD2, RSVD3, 0x3010, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PINGROUP(sdmmc1_dat0_pm5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3014, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PINGROUP(sdmmc3_clk_pp0, SDMMC3, RSVD1, RSVD2, RSVD3, 0x301c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PINGROUP(sdmmc3_cmd_pp1, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3020, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINGROUP(sdmmc3_dat0_pp5, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3024, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINGROUP(sdmmc3_dat1_pp4, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3028, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PINGROUP(sdmmc3_dat2_pp3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x302c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINGROUP(sdmmc3_dat3_pp2, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3030, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x3038, N, N, Y, 0xa5c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x303c, N, N, Y, 0xa58, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x3040, N, N, Y, 0xa68, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x3044, N, N, Y, 0xa64, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x3048, N, N, Y, 0xa60, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PINGROUP(sata_led_active_pa5, SATA, RSVD1, RSVD2, RSVD3, 0x304c, N, N, N, 0xa94, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINGROUP(spi1_mosi_pc0, SPI1, RSVD1, RSVD2, RSVD3, 0x3050, Y, Y, N, 0xae0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINGROUP(spi1_miso_pc1, SPI1, RSVD1, RSVD2, RSVD3, 0x3054, Y, Y, N, 0xadc, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINGROUP(spi1_sck_pc2, SPI1, RSVD1, RSVD2, RSVD3, 0x3058, Y, Y, N, 0xae4, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINGROUP(spi1_cs0_pc3, SPI1, RSVD1, RSVD2, RSVD3, 0x305c, Y, Y, N, 0xad4, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINGROUP(spi1_cs1_pc4, SPI1, RSVD1, RSVD2, RSVD3, 0x3060, Y, Y, N, 0xad8, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PINGROUP(spi2_mosi_pb4, SPI2, DTV, RSVD2, RSVD3, 0x3064, Y, Y, N, 0xaf4, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINGROUP(spi2_miso_pb5, SPI2, DTV, RSVD2, RSVD3, 0x3068, Y, Y, N, 0xaf0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PINGROUP(spi2_sck_pb6, SPI2, DTV, RSVD2, RSVD3, 0x306c, Y, Y, N, 0xaf8, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) PINGROUP(spi2_cs0_pb7, SPI2, DTV, RSVD2, RSVD3, 0x3070, Y, Y, N, 0xae8, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINGROUP(spi2_cs1_pdd0, SPI2, RSVD1, RSVD2, RSVD3, 0x3074, Y, Y, N, 0xaec, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINGROUP(spi4_mosi_pc7, SPI4, RSVD1, RSVD2, RSVD3, 0x3078, Y, Y, N, 0xb04, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINGROUP(spi4_miso_pd0, SPI4, RSVD1, RSVD2, RSVD3, 0x307c, Y, Y, N, 0xb00, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINGROUP(spi4_sck_pc5, SPI4, RSVD1, RSVD2, RSVD3, 0x3080, Y, Y, N, 0xb08, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PINGROUP(spi4_cs0_pc6, SPI4, RSVD1, RSVD2, RSVD3, 0x3084, Y, Y, N, 0xafc, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PINGROUP(qspi_sck_pee0, QSPI, RSVD1, RSVD2, RSVD3, 0x3088, Y, Y, N, 0xa90, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINGROUP(qspi_cs_n_pee1, QSPI, RSVD1, RSVD2, RSVD3, 0x308c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINGROUP(qspi_io0_pee2, QSPI, RSVD1, RSVD2, RSVD3, 0x3090, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINGROUP(qspi_io1_pee3, QSPI, RSVD1, RSVD2, RSVD3, 0x3094, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PINGROUP(qspi_io2_pee4, QSPI, RSVD1, RSVD2, RSVD3, 0x3098, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) PINGROUP(qspi_io3_pee5, QSPI, RSVD1, RSVD2, RSVD3, 0x309c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PINGROUP(dmic1_clk_pe0, DMIC1, I2S3, RSVD2, RSVD3, 0x30a4, N, N, N, 0x984, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINGROUP(dmic1_dat_pe1, DMIC1, I2S3, RSVD2, RSVD3, 0x30a8, N, N, N, 0x988, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PINGROUP(dmic2_clk_pe2, DMIC2, I2S3, RSVD2, RSVD3, 0x30ac, N, N, N, 0x98c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINGROUP(dmic2_dat_pe3, DMIC2, I2S3, RSVD2, RSVD3, 0x30b0, N, N, N, 0x990, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINGROUP(dmic3_clk_pe4, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b4, N, N, N, 0x994, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PINGROUP(dmic3_dat_pe5, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b8, N, N, N, 0x998, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PINGROUP(gen1_i2c_scl_pj1, I2C1, RSVD1, RSVD2, RSVD3, 0x30bc, N, N, Y, 0x9a8, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINGROUP(gen1_i2c_sda_pj0, I2C1, RSVD1, RSVD2, RSVD3, 0x30c0, N, N, Y, 0x9ac, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINGROUP(gen2_i2c_scl_pj2, I2C2, RSVD1, RSVD2, RSVD3, 0x30c4, N, N, Y, 0x9b0, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PINGROUP(gen2_i2c_sda_pj3, I2C2, RSVD1, RSVD2, RSVD3, 0x30c8, N, N, Y, 0x9b4, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PINGROUP(gen3_i2c_scl_pf0, I2C3, RSVD1, RSVD2, RSVD3, 0x30cc, N, N, Y, 0x9b8, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PINGROUP(gen3_i2c_sda_pf1, I2C3, RSVD1, RSVD2, RSVD3, 0x30d0, N, N, Y, 0x9bc, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) PINGROUP(cam_i2c_scl_ps2, I2C3, I2CVI, RSVD2, RSVD3, 0x30d4, N, N, Y, 0x934, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PINGROUP(cam_i2c_sda_ps3, I2C3, I2CVI, RSVD2, RSVD3, 0x30d8, N, N, Y, 0x938, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PINGROUP(pwr_i2c_scl_py3, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30dc, N, N, Y, 0xa6c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PINGROUP(pwr_i2c_sda_py4, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30e0, N, N, Y, 0xa70, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PINGROUP(uart1_tx_pu0, UARTA, RSVD1, RSVD2, RSVD3, 0x30e4, N, N, N, 0xb28, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) PINGROUP(uart1_rx_pu1, UARTA, RSVD1, RSVD2, RSVD3, 0x30e8, N, N, N, 0xb24, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PINGROUP(uart1_rts_pu2, UARTA, RSVD1, RSVD2, RSVD3, 0x30ec, N, N, N, 0xb20, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PINGROUP(uart1_cts_pu3, UARTA, RSVD1, RSVD2, RSVD3, 0x30f0, N, N, N, 0xb1c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PINGROUP(uart2_tx_pg0, UARTB, I2S4A, SPDIF, UART, 0x30f4, N, N, N, 0xb38, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) PINGROUP(uart2_rx_pg1, UARTB, I2S4A, SPDIF, UART, 0x30f8, N, N, N, 0xb34, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PINGROUP(uart2_rts_pg2, UARTB, I2S4A, RSVD2, UART, 0x30fc, N, N, N, 0xb30, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PINGROUP(uart2_cts_pg3, UARTB, I2S4A, RSVD2, UART, 0x3100, N, N, N, 0xb2c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PINGROUP(uart3_tx_pd1, UARTC, SPI4, RSVD2, RSVD3, 0x3104, N, N, N, 0xb48, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PINGROUP(uart3_rx_pd2, UARTC, SPI4, RSVD2, RSVD3, 0x3108, N, N, N, 0xb44, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PINGROUP(uart3_rts_pd3, UARTC, SPI4, RSVD2, RSVD3, 0x310c, N, N, N, 0xb40, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PINGROUP(uart3_cts_pd4, UARTC, SPI4, RSVD2, RSVD3, 0x3110, N, N, N, 0xb3c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PINGROUP(uart4_tx_pi4, UARTD, UART, RSVD2, RSVD3, 0x3114, N, N, N, 0xb58, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PINGROUP(uart4_rx_pi5, UARTD, UART, RSVD2, RSVD3, 0x3118, N, N, N, 0xb54, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PINGROUP(uart4_rts_pi6, UARTD, UART, RSVD2, RSVD3, 0x311c, N, N, N, 0xb50, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PINGROUP(uart4_cts_pi7, UARTD, UART, RSVD2, RSVD3, 0x3120, N, N, N, 0xb4c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PINGROUP(dap1_fs_pb0, I2S1, RSVD1, RSVD2, RSVD3, 0x3124, Y, Y, N, 0x95c, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PINGROUP(dap1_din_pb1, I2S1, RSVD1, RSVD2, RSVD3, 0x3128, Y, Y, N, 0x954, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PINGROUP(dap1_dout_pb2, I2S1, RSVD1, RSVD2, RSVD3, 0x312c, Y, Y, N, 0x958, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PINGROUP(dap1_sclk_pb3, I2S1, RSVD1, RSVD2, RSVD3, 0x3130, Y, Y, N, 0x960, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PINGROUP(dap2_fs_paa0, I2S2, RSVD1, RSVD2, RSVD3, 0x3134, Y, Y, N, 0x96c, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PINGROUP(dap2_din_paa2, I2S2, RSVD1, RSVD2, RSVD3, 0x3138, Y, Y, N, 0x964, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PINGROUP(dap2_dout_paa3, I2S2, RSVD1, RSVD2, RSVD3, 0x313c, Y, Y, N, 0x968, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) PINGROUP(dap2_sclk_paa1, I2S2, RSVD1, RSVD2, RSVD3, 0x3140, Y, Y, N, 0x970, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PINGROUP(dap4_fs_pj4, I2S4B, RSVD1, RSVD2, RSVD3, 0x3144, N, N, N, 0x97c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PINGROUP(dap4_din_pj5, I2S4B, RSVD1, RSVD2, RSVD3, 0x3148, N, N, N, 0x974, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) PINGROUP(dap4_dout_pj6, I2S4B, RSVD1, RSVD2, RSVD3, 0x314c, N, N, N, 0x978, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) PINGROUP(dap4_sclk_pj7, I2S4B, RSVD1, RSVD2, RSVD3, 0x3150, N, N, N, 0x980, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PINGROUP(cam1_mclk_ps0, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3154, N, N, N, 0x918, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) PINGROUP(cam2_mclk_ps1, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3158, N, N, N, 0x924, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) PINGROUP(jtag_rtck, JTAG, RSVD1, RSVD2, RSVD3, 0x315c, N, N, N, 0xa2c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, 0x940, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) PINGROUP(clk_32k_out_py5, SOC, BLINK, RSVD2, RSVD3, 0x3164, N, N, N, 0x944, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PINGROUP(batt_bcl, BCL, RSVD1, RSVD2, RSVD3, 0x3168, N, N, Y, 0x8f8, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PINGROUP(clk_req, SYS, RSVD1, RSVD2, RSVD3, 0x316c, N, N, N, 0x948, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) PINGROUP(cpu_pwr_req, CPU, RSVD1, RSVD2, RSVD3, 0x3170, N, N, N, 0x950, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PINGROUP(pwr_int_n, PMI, RSVD1, RSVD2, RSVD3, 0x3174, N, N, N, 0xa74, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) PINGROUP(shutdown, SHUTDOWN, RSVD1, RSVD2, RSVD3, 0x3178, N, N, N, 0xac8, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) PINGROUP(core_pwr_req, CORE, RSVD1, RSVD2, RSVD3, 0x317c, N, N, N, 0x94c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) PINGROUP(aud_mclk_pbb0, AUD, RSVD1, RSVD2, RSVD3, 0x3180, N, N, N, 0x8f4, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) PINGROUP(dvfs_pwm_pbb1, RSVD0, CLDVFS, SPI3, RSVD3, 0x3184, N, N, N, 0x9a4, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) PINGROUP(dvfs_clk_pbb2, RSVD0, CLDVFS, SPI3, RSVD3, 0x3188, N, N, N, 0x9a0, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) PINGROUP(gpio_x1_aud_pbb3, RSVD0, RSVD1, SPI3, RSVD3, 0x318c, N, N, N, 0xa14, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) PINGROUP(gpio_x3_aud_pbb4, RSVD0, RSVD1, SPI3, RSVD3, 0x3190, N, N, N, 0xa18, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) PINGROUP(pcc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3194, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) PINGROUP(hdmi_cec_pcc0, CEC, RSVD1, RSVD2, RSVD3, 0x3198, N, N, Y, 0xa24, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PINGROUP(hdmi_int_dp_hpd_pcc1, DP, RSVD1, RSVD2, RSVD3, 0x319c, N, N, Y, 0xa28, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) PINGROUP(spdif_out_pcc2, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a0, N, N, N, 0xad0, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PINGROUP(spdif_in_pcc3, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a4, N, N, N, 0xacc, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) PINGROUP(usb_vbus_en0_pcc4, USB, RSVD1, RSVD2, RSVD3, 0x31a8, N, N, Y, 0xb5c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) PINGROUP(usb_vbus_en1_pcc5, USB, RSVD1, RSVD2, RSVD3, 0x31ac, N, N, Y, 0xb60, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) PINGROUP(dp_hpd0_pcc6, DP, RSVD1, RSVD2, RSVD3, 0x31b0, N, N, N, 0x99c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) PINGROUP(wifi_en_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b4, N, N, N, 0xb64, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) PINGROUP(wifi_rst_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b8, N, N, N, 0xb68, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) PINGROUP(wifi_wake_ap_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31bc, N, N, N, 0xb6c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) PINGROUP(ap_wake_bt_ph3, RSVD0, UARTB, SPDIF, RSVD3, 0x31c0, N, N, N, 0x8ec, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) PINGROUP(bt_rst_ph4, RSVD0, UARTB, SPDIF, RSVD3, 0x31c4, N, N, N, 0x8fc, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) PINGROUP(bt_wake_ap_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x31c8, N, N, N, 0x900, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) PINGROUP(ap_wake_nfc_ph7, RSVD0, RSVD1, RSVD2, RSVD3, 0x31cc, N, N, N, 0x8f0, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) PINGROUP(nfc_en_pi0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d0, N, N, N, 0xa50, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PINGROUP(nfc_int_pi1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d4, N, N, N, 0xa54, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) PINGROUP(gps_en_pi2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d8, N, N, N, 0xa1c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PINGROUP(gps_rst_pi3, RSVD0, RSVD1, RSVD2, RSVD3, 0x31dc, N, N, N, 0xa20, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) PINGROUP(cam_rst_ps4, VGP1, RSVD1, RSVD2, RSVD3, 0x31e0, N, N, N, 0x93c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) PINGROUP(cam_af_en_ps5, VIMCLK, VGP2, RSVD2, RSVD3, 0x31e4, N, N, N, 0x92c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) PINGROUP(cam_flash_en_ps6, VIMCLK, VGP3, RSVD2, RSVD3, 0x31e8, N, N, N, 0x930, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) PINGROUP(cam1_pwdn_ps7, VGP4, RSVD1, RSVD2, RSVD3, 0x31ec, N, N, N, 0x91c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) PINGROUP(cam2_pwdn_pt0, VGP5, RSVD1, RSVD2, RSVD3, 0x31f0, N, N, N, 0x928, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) PINGROUP(cam1_strobe_pt1, VGP6, RSVD1, RSVD2, RSVD3, 0x31f4, N, N, N, 0x920, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) PINGROUP(lcd_te_py2, DISPLAYA, RSVD1, RSVD2, RSVD3, 0x31f8, N, N, N, 0xa44, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) PINGROUP(lcd_bl_pwm_pv0, DISPLAYA, PWM0, SOR0, RSVD3, 0x31fc, N, N, N, 0xa34, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) PINGROUP(lcd_bl_en_pv1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3200, N, N, N, 0xa30, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) PINGROUP(lcd_rst_pv2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3204, N, N, N, 0xa40, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) PINGROUP(lcd_gpio1_pv3, DISPLAYB, RSVD1, RSVD2, RSVD3, 0x3208, N, N, N, 0xa38, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) PINGROUP(lcd_gpio2_pv4, DISPLAYB, PWM1, RSVD2, SOR1, 0x320c, N, N, N, 0xa3c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) PINGROUP(ap_ready_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3210, N, N, N, 0x8e8, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) PINGROUP(touch_rst_pv6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3214, N, N, N, 0xb18, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) PINGROUP(touch_clk_pv7, TOUCH, RSVD1, RSVD2, RSVD3, 0x3218, N, N, N, 0xb10, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) PINGROUP(modem_wake_ap_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x321c, N, N, N, 0xa48, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) PINGROUP(touch_int_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3220, N, N, N, 0xb14, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) PINGROUP(motion_int_px2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3224, N, N, N, 0xa4c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) PINGROUP(als_prox_int_px3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3228, N, N, N, 0x8e4, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) PINGROUP(temp_alert_px4, RSVD0, RSVD1, RSVD2, RSVD3, 0x322c, N, N, N, 0xb0c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) PINGROUP(button_power_on_px5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3230, N, N, N, 0x908, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) PINGROUP(button_vol_up_px6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3234, N, N, N, 0x914, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) PINGROUP(button_vol_down_px7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3238, N, N, N, 0x910, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) PINGROUP(button_slide_sw_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0x323c, N, N, N, 0x90c, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) PINGROUP(button_home_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3240, N, N, N, 0x904, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) PINGROUP(pa6, SATA, RSVD1, RSVD2, RSVD3, 0x3244, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) PINGROUP(pe6, RSVD0, I2S5A, PWM2, RSVD3, 0x3248, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) PINGROUP(pe7, RSVD0, I2S5A, PWM3, RSVD3, 0x324c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) PINGROUP(ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3250, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) PINGROUP(pk0, IQC0, I2S5B, RSVD2, RSVD3, 0x3254, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) PINGROUP(pk1, IQC0, I2S5B, RSVD2, RSVD3, 0x3258, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) PINGROUP(pk2, IQC0, I2S5B, RSVD2, RSVD3, 0x325c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) PINGROUP(pk3, IQC0, I2S5B, RSVD2, RSVD3, 0x3260, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) PINGROUP(pk4, IQC1, RSVD1, RSVD2, RSVD3, 0x3264, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) PINGROUP(pk5, IQC1, RSVD1, RSVD2, RSVD3, 0x3268, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) PINGROUP(pk6, IQC1, RSVD1, RSVD2, RSVD3, 0x326c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) PINGROUP(pk7, IQC1, RSVD1, RSVD2, RSVD3, 0x3270, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) PINGROUP(pl0, RSVD0, RSVD1, RSVD2, RSVD3, 0x3274, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) PINGROUP(pz0, VIMCLK2, RSVD1, RSVD2, RSVD3, 0x327c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) PINGROUP(pz1, VIMCLK2, SDMMC1, RSVD2, RSVD3, 0x3280, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) PINGROUP(pz2, SDMMC3, CCLA, RSVD2, RSVD3, 0x3284, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) PINGROUP(pz3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3288, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) PINGROUP(pz4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x328c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) PINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* pg_name, r, prk_mask, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) DRV_PINGROUP(pa6, 0x9c0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) DRV_PINGROUP(pcc7, 0x9c4, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) DRV_PINGROUP(pe6, 0x9c8, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) DRV_PINGROUP(pe7, 0x9cc, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) DRV_PINGROUP(ph6, 0x9d0, 0x0, 12, 5, 20, 5, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) DRV_PINGROUP(pk0, 0x9d4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) DRV_PINGROUP(pk1, 0x9d8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) DRV_PINGROUP(pk2, 0x9dc, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) DRV_PINGROUP(pk3, 0x9e0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) DRV_PINGROUP(pk4, 0x9e4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) DRV_PINGROUP(pk5, 0x9e8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) DRV_PINGROUP(pk6, 0x9ec, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) DRV_PINGROUP(pk7, 0x9f0, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) DRV_PINGROUP(pl0, 0x9f4, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) DRV_PINGROUP(pl1, 0x9f8, 0x0, -1, -1, -1, -1, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) DRV_PINGROUP(pz0, 0x9fc, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) DRV_PINGROUP(pz1, 0xa00, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) DRV_PINGROUP(pz2, 0xa04, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) DRV_PINGROUP(pz3, 0xa08, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) DRV_PINGROUP(pz4, 0xa0c, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) DRV_PINGROUP(pz5, 0xa10, 0x0, 12, 7, 20, 7, -1, -1, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) DRV_PINGROUP(sdmmc1, 0xa98, 0x0, 12, 7, 20, 7, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) DRV_PINGROUP(sdmmc2, 0xa9c, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) DRV_PINGROUP(sdmmc3, 0xab0, 0x0, 12, 7, 20, 7, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) DRV_PINGROUP(sdmmc4, 0xab4, 0x7ffc000, 2, 6, 8, 6, 28, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .ngpios = NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .gpio_compatible = "nvidia,tegra210-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .pins = tegra210_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .npins = ARRAY_SIZE(tegra210_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .functions = tegra210_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .nfunctions = ARRAY_SIZE(tegra210_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .groups = tegra210_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .ngroups = ARRAY_SIZE(tegra210_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .hsm_in_mux = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .schmitt_in_mux = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .drvtype_in_mux = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static int tegra210_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return tegra_pinctrl_probe(pdev, &tegra210_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static const struct of_device_id tegra210_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) { .compatible = "nvidia,tegra210-pinmux", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static struct platform_driver tegra210_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .name = "tegra210-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .of_match_table = tegra210_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .pm = &tegra_pinctrl_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .probe = tegra210_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static int __init tegra210_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return platform_driver_register(&tegra210_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) arch_initcall(tegra210_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags