^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pinctrl data for the NVIDIA Tegra20 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Stephen Warren <swarren@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Derived from code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2010 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2010 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pinctrl-tegra.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Most pins affected by the pinmux can also be GPIOs. Define these first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * These must match how the GPIO driver names/numbers its pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define _GPIO(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_PIN_VI_GP6_PA0 _GPIO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA_PIN_VI_GP5_PD2 _GPIO(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA_PIN_VI_D1_PD5 _GPIO(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA_PIN_LCD_D0_PE0 _GPIO(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA_PIN_LCD_D1_PE1 _GPIO(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA_PIN_LCD_D2_PE2 _GPIO(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA_PIN_LCD_D3_PE3 _GPIO(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA_PIN_LCD_D4_PE4 _GPIO(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA_PIN_LCD_D5_PE5 _GPIO(37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA_PIN_LCD_D6_PE6 _GPIO(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA_PIN_LCD_D7_PE7 _GPIO(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA_PIN_LCD_D8_PF0 _GPIO(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA_PIN_LCD_D9_PF1 _GPIO(41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA_PIN_LCD_D10_PF2 _GPIO(42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA_PIN_LCD_D11_PF3 _GPIO(43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA_PIN_LCD_D12_PF4 _GPIO(44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA_PIN_LCD_D13_PF5 _GPIO(45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA_PIN_LCD_D14_PF6 _GPIO(46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA_PIN_LCD_D15_PF7 _GPIO(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA_PIN_VI_D2_PL0 _GPIO(88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA_PIN_VI_D3_PL1 _GPIO(89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA_PIN_VI_D4_PL2 _GPIO(90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA_PIN_VI_D5_PL3 _GPIO(91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA_PIN_VI_D6_PL4 _GPIO(92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA_PIN_VI_D7_PL5 _GPIO(93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA_PIN_VI_D8_PL6 _GPIO(94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA_PIN_VI_D9_PL7 _GPIO(95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA_PIN_LCD_D16_PM0 _GPIO(96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA_PIN_LCD_D17_PM1 _GPIO(97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA_PIN_LCD_D18_PM2 _GPIO(98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA_PIN_LCD_D19_PM3 _GPIO(99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA_PIN_LCD_D20_PM4 _GPIO(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA_PIN_LCD_D21_PM5 _GPIO(101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA_PIN_LCD_D22_PM6 _GPIO(102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA_PIN_LCD_D23_PM7 _GPIO(103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TEGRA_PIN_VI_D10_PT2 _GPIO(154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TEGRA_PIN_VI_D11_PT3 _GPIO(155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TEGRA_PIN_VI_D0_PT4 _GPIO(156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TEGRA_PIN_PU0 _GPIO(160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TEGRA_PIN_PU1 _GPIO(161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TEGRA_PIN_PU2 _GPIO(162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA_PIN_PU3 _GPIO(163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TEGRA_PIN_PU4 _GPIO(164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA_PIN_PU5 _GPIO(165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TEGRA_PIN_PU6 _GPIO(166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TEGRA_PIN_PV0 _GPIO(168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA_PIN_PV1 _GPIO(169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA_PIN_PV2 _GPIO(170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA_PIN_PV3 _GPIO(171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TEGRA_PIN_PV4 _GPIO(172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEGRA_PIN_PV5 _GPIO(173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEGRA_PIN_PV6 _GPIO(174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TEGRA_PIN_LCD_M1_PW1 _GPIO(177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TEGRA_PIN_PBB6 _GPIO(222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TEGRA_PIN_PBB7 _GPIO(223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* All non-GPIO pins follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define NUM_GPIOS (TEGRA_PIN_PBB7 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define _PIN(offset) (NUM_GPIOS + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TEGRA_PIN_CRT_HSYNC _PIN(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TEGRA_PIN_CRT_VSYNC _PIN(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEGRA_PIN_DDC_SCL _PIN(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TEGRA_PIN_DDC_SDA _PIN(33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TEGRA_PIN_OWC _PIN(34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TEGRA_PIN_CORE_PWR_REQ _PIN(35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TEGRA_PIN_CPU_PWR_REQ _PIN(36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TEGRA_PIN_PWR_INT_N _PIN(37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TEGRA_PIN_CLK_32_K_IN _PIN(38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TEGRA_PIN_DDR_COMP_PD _PIN(39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEGRA_PIN_DDR_COMP_PU _PIN(40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TEGRA_PIN_DDR_A0 _PIN(41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEGRA_PIN_DDR_A1 _PIN(42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TEGRA_PIN_DDR_A2 _PIN(43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TEGRA_PIN_DDR_A3 _PIN(44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TEGRA_PIN_DDR_A4 _PIN(45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TEGRA_PIN_DDR_A5 _PIN(46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TEGRA_PIN_DDR_A6 _PIN(47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TEGRA_PIN_DDR_A7 _PIN(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TEGRA_PIN_DDR_A8 _PIN(49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TEGRA_PIN_DDR_A9 _PIN(50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TEGRA_PIN_DDR_A10 _PIN(51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TEGRA_PIN_DDR_A11 _PIN(52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TEGRA_PIN_DDR_A12 _PIN(53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TEGRA_PIN_DDR_A13 _PIN(54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TEGRA_PIN_DDR_A14 _PIN(55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TEGRA_PIN_DDR_CAS_N _PIN(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TEGRA_PIN_DDR_BA0 _PIN(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TEGRA_PIN_DDR_BA1 _PIN(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TEGRA_PIN_DDR_BA2 _PIN(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TEGRA_PIN_DDR_DQS0P _PIN(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TEGRA_PIN_DDR_DQS0N _PIN(61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TEGRA_PIN_DDR_DQS1P _PIN(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TEGRA_PIN_DDR_DQS1N _PIN(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TEGRA_PIN_DDR_DQS2P _PIN(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TEGRA_PIN_DDR_DQS2N _PIN(65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TEGRA_PIN_DDR_DQS3P _PIN(66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TEGRA_PIN_DDR_DQS3N _PIN(67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TEGRA_PIN_DDR_CKE0 _PIN(68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TEGRA_PIN_DDR_CKE1 _PIN(69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TEGRA_PIN_DDR_CLK _PIN(70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TEGRA_PIN_DDR_CLK_N _PIN(71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TEGRA_PIN_DDR_DM0 _PIN(72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TEGRA_PIN_DDR_DM1 _PIN(73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TEGRA_PIN_DDR_DM2 _PIN(74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TEGRA_PIN_DDR_DM3 _PIN(75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define TEGRA_PIN_DDR_ODT _PIN(76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TEGRA_PIN_DDR_QUSE0 _PIN(77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TEGRA_PIN_DDR_QUSE1 _PIN(78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TEGRA_PIN_DDR_QUSE2 _PIN(79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TEGRA_PIN_DDR_QUSE3 _PIN(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define TEGRA_PIN_DDR_RAS_N _PIN(81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TEGRA_PIN_DDR_WE_N _PIN(82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TEGRA_PIN_DDR_DQ0 _PIN(83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TEGRA_PIN_DDR_DQ1 _PIN(84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TEGRA_PIN_DDR_DQ2 _PIN(85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TEGRA_PIN_DDR_DQ3 _PIN(86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TEGRA_PIN_DDR_DQ4 _PIN(87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TEGRA_PIN_DDR_DQ5 _PIN(88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TEGRA_PIN_DDR_DQ6 _PIN(89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TEGRA_PIN_DDR_DQ7 _PIN(90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TEGRA_PIN_DDR_DQ8 _PIN(91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TEGRA_PIN_DDR_DQ9 _PIN(92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TEGRA_PIN_DDR_DQ10 _PIN(93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TEGRA_PIN_DDR_DQ11 _PIN(94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define TEGRA_PIN_DDR_DQ12 _PIN(95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TEGRA_PIN_DDR_DQ13 _PIN(96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TEGRA_PIN_DDR_DQ14 _PIN(97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TEGRA_PIN_DDR_DQ15 _PIN(98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TEGRA_PIN_DDR_DQ16 _PIN(99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TEGRA_PIN_DDR_DQ17 _PIN(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TEGRA_PIN_DDR_DQ18 _PIN(101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TEGRA_PIN_DDR_DQ19 _PIN(102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TEGRA_PIN_DDR_DQ20 _PIN(103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TEGRA_PIN_DDR_DQ21 _PIN(104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define TEGRA_PIN_DDR_DQ22 _PIN(105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TEGRA_PIN_DDR_DQ23 _PIN(106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TEGRA_PIN_DDR_DQ24 _PIN(107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TEGRA_PIN_DDR_DQ25 _PIN(108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define TEGRA_PIN_DDR_DQ26 _PIN(109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TEGRA_PIN_DDR_DQ27 _PIN(110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define TEGRA_PIN_DDR_DQ28 _PIN(111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define TEGRA_PIN_DDR_DQ29 _PIN(112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TEGRA_PIN_DDR_DQ30 _PIN(113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TEGRA_PIN_DDR_DQ31 _PIN(114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TEGRA_PIN_DDR_CS0_N _PIN(115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TEGRA_PIN_DDR_CS1_N _PIN(116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define TEGRA_PIN_SYS_RESET _PIN(117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TEGRA_PIN_JTAG_TRST_N _PIN(118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TEGRA_PIN_JTAG_TDO _PIN(119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define TEGRA_PIN_JTAG_TMS _PIN(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define TEGRA_PIN_JTAG_TCK _PIN(121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TEGRA_PIN_JTAG_TDI _PIN(122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define TEGRA_PIN_TEST_MODE_EN _PIN(123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct pinctrl_pin_desc tegra20_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(TEGRA_PIN_VI_GP6_PA0, "VI_GP6 PA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_PIN(TEGRA_PIN_SDIO3_CLK_PA6, "SDIO3_CLK PA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_PIN(TEGRA_PIN_SDIO3_CMD_PA7, "SDIO3_CMD PA7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_PIN(TEGRA_PIN_GMI_AD17_PB0, "GMI_AD17 PB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_PIN(TEGRA_PIN_GMI_AD18_PB1, "GMI_AD18 PB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_PIN(TEGRA_PIN_LCD_PWR0_PB2, "LCD_PWR0 PB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_PIN(TEGRA_PIN_LCD_PCLK_PB3, "LCD_PCLK PB3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT3_PB4, "SDIO3_DAT3 PB4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT2_PB5, "SDIO3_DAT2 PB5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT1_PB6, "SDIO3_DAT1 PB6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT0_PB7, "SDIO3_DAT0 PB7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINCTRL_PIN(TEGRA_PIN_LCD_PWR1_PC1, "LCD_PWR1 PC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_PIN(TEGRA_PIN_LCD_PWR2_PC6, "LCD_PWR2 PC6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT5_PD0, "SDIO3_DAT5 PD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT4_PD1, "SDIO3_DAT4 PD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(TEGRA_PIN_VI_GP5_PD2, "VI_GP5 PD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT6_PD3, "SDIO3_DAT6 PD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_PIN(TEGRA_PIN_SDIO3_DAT7_PD4, "SDIO3_DAT7 PD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(TEGRA_PIN_VI_D1_PD5, "VI_D1 PD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(TEGRA_PIN_VI_VSYNC_PD6, "VI_VSYNC PD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(TEGRA_PIN_VI_HSYNC_PD7, "VI_HSYNC PD7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(TEGRA_PIN_LCD_D0_PE0, "LCD_D0 PE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(TEGRA_PIN_LCD_D1_PE1, "LCD_D1 PE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_PIN(TEGRA_PIN_LCD_D2_PE2, "LCD_D2 PE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(TEGRA_PIN_LCD_D3_PE3, "LCD_D3 PE3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(TEGRA_PIN_LCD_D4_PE4, "LCD_D4 PE4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(TEGRA_PIN_LCD_D5_PE5, "LCD_D5 PE5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(TEGRA_PIN_LCD_D6_PE6, "LCD_D6 PE6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(TEGRA_PIN_LCD_D7_PE7, "LCD_D7 PE7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(TEGRA_PIN_LCD_D8_PF0, "LCD_D8 PF0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(TEGRA_PIN_LCD_D9_PF1, "LCD_D9 PF1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINCTRL_PIN(TEGRA_PIN_LCD_D10_PF2, "LCD_D10 PF2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_PIN(TEGRA_PIN_LCD_D11_PF3, "LCD_D11 PF3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(TEGRA_PIN_LCD_D12_PF4, "LCD_D12 PF4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(TEGRA_PIN_LCD_D13_PF5, "LCD_D13 PF5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(TEGRA_PIN_LCD_D14_PF6, "LCD_D14 PF6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_PIN(TEGRA_PIN_LCD_D15_PF7, "LCD_D15 PF7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(TEGRA_PIN_GMI_HIOW_N_PI0, "GMI_HIOW_N PI0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINCTRL_PIN(TEGRA_PIN_GMI_HIOR_N_PI1, "GMI_HIOR_N PI1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(TEGRA_PIN_GMI_CS5_N_PI2, "GMI_CS5_N PI2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(TEGRA_PIN_LCD_DE_PJ1, "LCD_DE PJ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(TEGRA_PIN_LCD_HSYNC_PJ3, "LCD_HSYNC PJ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(TEGRA_PIN_LCD_VSYNC_PJ4, "LCD_VSYNC PJ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(TEGRA_PIN_GMI_AD16_PJ7, "GMI_AD16 PJ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(TEGRA_PIN_GMI_AD19_PK7, "GMI_AD19 PK7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINCTRL_PIN(TEGRA_PIN_VI_D2_PL0, "VI_D2 PL0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(TEGRA_PIN_VI_D3_PL1, "VI_D3 PL1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(TEGRA_PIN_VI_D4_PL2, "VI_D4 PL2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(TEGRA_PIN_VI_D5_PL3, "VI_D5 PL3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINCTRL_PIN(TEGRA_PIN_VI_D6_PL4, "VI_D6 PL4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINCTRL_PIN(TEGRA_PIN_VI_D7_PL5, "VI_D7 PL5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINCTRL_PIN(TEGRA_PIN_VI_D8_PL6, "VI_D8 PL6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINCTRL_PIN(TEGRA_PIN_VI_D9_PL7, "VI_D9 PL7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINCTRL_PIN(TEGRA_PIN_LCD_D16_PM0, "LCD_D16 PM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINCTRL_PIN(TEGRA_PIN_LCD_D17_PM1, "LCD_D17 PM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINCTRL_PIN(TEGRA_PIN_LCD_D18_PM2, "LCD_D18 PM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINCTRL_PIN(TEGRA_PIN_LCD_D19_PM3, "LCD_D19 PM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINCTRL_PIN(TEGRA_PIN_LCD_D20_PM4, "LCD_D20 PM4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINCTRL_PIN(TEGRA_PIN_LCD_D21_PM5, "LCD_D21 PM5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINCTRL_PIN(TEGRA_PIN_LCD_D22_PM6, "LCD_D22 PM6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINCTRL_PIN(TEGRA_PIN_LCD_D23_PM7, "LCD_D23 PM7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINCTRL_PIN(TEGRA_PIN_LCD_CS0_N_PN4, "LCD_CS0_N PN4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINCTRL_PIN(TEGRA_PIN_LCD_SDOUT_PN5, "LCD_SDOUT PN5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINCTRL_PIN(TEGRA_PIN_LCD_DC0_PN6, "LCD_DC0 PN6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINCTRL_PIN(TEGRA_PIN_HDMI_INT_N_PN7, "HDMI_INT_N PN7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINCTRL_PIN(TEGRA_PIN_VI_PCLK_PT0, "VI_PCLK PT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINCTRL_PIN(TEGRA_PIN_VI_MCLK_PT1, "VI_MCLK PT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINCTRL_PIN(TEGRA_PIN_VI_D10_PT2, "VD_D10 PT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINCTRL_PIN(TEGRA_PIN_VI_D11_PT3, "VI_D11 PT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINCTRL_PIN(TEGRA_PIN_VI_D0_PT4, "VI_D0 PT4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINCTRL_PIN(TEGRA_PIN_GMI_DPD_PT7, "GMI_DPD PT7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* PU0..6: GPIO only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK_PU7, "JTAG_RTCK PU7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* PV0..1: GPIO only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* PV2..3: Balls are named after GPIO not function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINCTRL_PIN(TEGRA_PIN_PV2, "PV2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINCTRL_PIN(TEGRA_PIN_PV3, "PV3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* PV4..6: GPIO only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINCTRL_PIN(TEGRA_PIN_PV4, "PV4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINCTRL_PIN(TEGRA_PIN_PV5, "PV5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINCTRL_PIN(TEGRA_PIN_PV6, "PV6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINCTRL_PIN(TEGRA_PIN_LCD_DC1_PV7, "LCD_DC1 PV7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINCTRL_PIN(TEGRA_PIN_LCD_CS1_N_PW0, "LCD_CS1_N PW0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINCTRL_PIN(TEGRA_PIN_LCD_M1_PW1, "LCD_M1 PW1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_N_PW2, "SPI2_CS1_N PW2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINCTRL_PIN(TEGRA_PIN_SPI2_CS2_N_PW3, "SPI2_CS2_N PW3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINCTRL_PIN(TEGRA_PIN_DAP_MCLK2_PW5, "DAP_MCLK2 PW5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PX0, "SPI2_MOSI PX0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PX1, "SPI2_MISO PX1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PX2, "SPI2_SCK PX2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PX3, "SPI2_CS0_N PX3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PX4, "SPI1_MOSI PX4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PX5, "SPI1_SCK PX5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_N_PX6, "SPI1_CS0_N PX6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PX7, "SPI1_MISO PX7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT3_PY4, "SDIO1_DAT3 PY4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT2_PY5, "SDIO1_DAT2 PY5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT1_PY6, "SDIO1_DAT1 PY6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINCTRL_PIN(TEGRA_PIN_SDIO1_DAT0_PY7, "SDIO1_DAT0 PY7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINCTRL_PIN(TEGRA_PIN_SDIO1_CLK_PZ0, "SDIO1_CLK PZ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINCTRL_PIN(TEGRA_PIN_SDIO1_CMD_PZ1, "SDIO1_CMD PZ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINCTRL_PIN(TEGRA_PIN_LCD_SDIN_PZ2, "LCD_SDIN PZ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINCTRL_PIN(TEGRA_PIN_LCD_WR_N_PZ3, "LCD_WR_N PZ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINCTRL_PIN(TEGRA_PIN_LCD_SCK_PZ4, "LCD_SCK PZ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINCTRL_PIN(TEGRA_PIN_GMI_AD20_PAA0, "GMI_AD20 PAA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINCTRL_PIN(TEGRA_PIN_GMI_AD21_PAA1, "GMI_AD21 PAA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINCTRL_PIN(TEGRA_PIN_GMI_AD22_PAA2, "GMI_AD22 PAA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINCTRL_PIN(TEGRA_PIN_GMI_AD23_PAA3, "GMI_AD23 PAA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINCTRL_PIN(TEGRA_PIN_GMI_AD24_PAA4, "GMI_AD24 PAA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINCTRL_PIN(TEGRA_PIN_GMI_AD25_PAA5, "GMI_AD25 PAA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINCTRL_PIN(TEGRA_PIN_GMI_AD26_PAA6, "GMI_AD26 PAA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINCTRL_PIN(TEGRA_PIN_GMI_AD27_PAA7, "GMI_AD27 PAA7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINCTRL_PIN(TEGRA_PIN_LED_BLINK_PBB0, "LED_BLINK PBB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINCTRL_PIN(TEGRA_PIN_VI_GP0_PBB1, "VI_GP0 PBB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB2, "CAM_I2C_SCL PBB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB3, "CAM_I2C_SDA PBB3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINCTRL_PIN(TEGRA_PIN_VI_GP3_PBB4, "VI_GP3 PBB4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINCTRL_PIN(TEGRA_PIN_VI_GP4_PBB5, "VI_GP4 PBB5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINCTRL_PIN(TEGRA_PIN_CRT_HSYNC, "CRT_HSYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINCTRL_PIN(TEGRA_PIN_CRT_VSYNC, "CRT_VSYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINCTRL_PIN(TEGRA_PIN_DDC_SCL, "DDC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINCTRL_PIN(TEGRA_PIN_DDC_SDA, "DDC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINCTRL_PIN(TEGRA_PIN_OWC, "OWC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINCTRL_PIN(TEGRA_PIN_CLK_32_K_IN, "CLK_32_K_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PD, "DDR_COMP_PD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINCTRL_PIN(TEGRA_PIN_DDR_COMP_PU, "DDR_COMP_PU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINCTRL_PIN(TEGRA_PIN_DDR_A0, "DDR_A0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINCTRL_PIN(TEGRA_PIN_DDR_A1, "DDR_A1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINCTRL_PIN(TEGRA_PIN_DDR_A2, "DDR_A2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINCTRL_PIN(TEGRA_PIN_DDR_A3, "DDR_A3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINCTRL_PIN(TEGRA_PIN_DDR_A4, "DDR_A4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINCTRL_PIN(TEGRA_PIN_DDR_A5, "DDR_A5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINCTRL_PIN(TEGRA_PIN_DDR_A6, "DDR_A6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINCTRL_PIN(TEGRA_PIN_DDR_A7, "DDR_A7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINCTRL_PIN(TEGRA_PIN_DDR_A8, "DDR_A8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINCTRL_PIN(TEGRA_PIN_DDR_A9, "DDR_A9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINCTRL_PIN(TEGRA_PIN_DDR_A10, "DDR_A10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINCTRL_PIN(TEGRA_PIN_DDR_A11, "DDR_A11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINCTRL_PIN(TEGRA_PIN_DDR_A12, "DDR_A12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINCTRL_PIN(TEGRA_PIN_DDR_A13, "DDR_A13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINCTRL_PIN(TEGRA_PIN_DDR_A14, "DDR_A14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINCTRL_PIN(TEGRA_PIN_DDR_CAS_N, "DDR_CAS_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINCTRL_PIN(TEGRA_PIN_DDR_BA0, "DDR_BA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINCTRL_PIN(TEGRA_PIN_DDR_BA1, "DDR_BA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINCTRL_PIN(TEGRA_PIN_DDR_BA2, "DDR_BA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINCTRL_PIN(TEGRA_PIN_DDR_DQS0P, "DDR_DQS0P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINCTRL_PIN(TEGRA_PIN_DDR_DQS0N, "DDR_DQS0N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINCTRL_PIN(TEGRA_PIN_DDR_DQS1P, "DDR_DQS1P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINCTRL_PIN(TEGRA_PIN_DDR_DQS1N, "DDR_DQS1N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINCTRL_PIN(TEGRA_PIN_DDR_DQS2P, "DDR_DQS2P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINCTRL_PIN(TEGRA_PIN_DDR_DQS2N, "DDR_DQS2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINCTRL_PIN(TEGRA_PIN_DDR_DQS3P, "DDR_DQS3P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINCTRL_PIN(TEGRA_PIN_DDR_DQS3N, "DDR_DQS3N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINCTRL_PIN(TEGRA_PIN_DDR_CKE0, "DDR_CKE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINCTRL_PIN(TEGRA_PIN_DDR_CKE1, "DDR_CKE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINCTRL_PIN(TEGRA_PIN_DDR_CLK, "DDR_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINCTRL_PIN(TEGRA_PIN_DDR_CLK_N, "DDR_CLK_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINCTRL_PIN(TEGRA_PIN_DDR_DM0, "DDR_DM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINCTRL_PIN(TEGRA_PIN_DDR_DM1, "DDR_DM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINCTRL_PIN(TEGRA_PIN_DDR_DM2, "DDR_DM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINCTRL_PIN(TEGRA_PIN_DDR_DM3, "DDR_DM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINCTRL_PIN(TEGRA_PIN_DDR_ODT, "DDR_ODT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINCTRL_PIN(TEGRA_PIN_DDR_QUSE0, "DDR_QUSE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINCTRL_PIN(TEGRA_PIN_DDR_QUSE1, "DDR_QUSE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINCTRL_PIN(TEGRA_PIN_DDR_QUSE2, "DDR_QUSE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINCTRL_PIN(TEGRA_PIN_DDR_QUSE3, "DDR_QUSE3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINCTRL_PIN(TEGRA_PIN_DDR_RAS_N, "DDR_RAS_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINCTRL_PIN(TEGRA_PIN_DDR_WE_N, "DDR_WE_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINCTRL_PIN(TEGRA_PIN_DDR_DQ0, "DDR_DQ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINCTRL_PIN(TEGRA_PIN_DDR_DQ1, "DDR_DQ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINCTRL_PIN(TEGRA_PIN_DDR_DQ2, "DDR_DQ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINCTRL_PIN(TEGRA_PIN_DDR_DQ3, "DDR_DQ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINCTRL_PIN(TEGRA_PIN_DDR_DQ4, "DDR_DQ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINCTRL_PIN(TEGRA_PIN_DDR_DQ5, "DDR_DQ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINCTRL_PIN(TEGRA_PIN_DDR_DQ6, "DDR_DQ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINCTRL_PIN(TEGRA_PIN_DDR_DQ7, "DDR_DQ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINCTRL_PIN(TEGRA_PIN_DDR_DQ8, "DDR_DQ8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINCTRL_PIN(TEGRA_PIN_DDR_DQ9, "DDR_DQ9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINCTRL_PIN(TEGRA_PIN_DDR_DQ10, "DDR_DQ10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINCTRL_PIN(TEGRA_PIN_DDR_DQ11, "DDR_DQ11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINCTRL_PIN(TEGRA_PIN_DDR_DQ12, "DDR_DQ12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINCTRL_PIN(TEGRA_PIN_DDR_DQ13, "DDR_DQ13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINCTRL_PIN(TEGRA_PIN_DDR_DQ14, "DDR_DQ14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINCTRL_PIN(TEGRA_PIN_DDR_DQ15, "DDR_DQ15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINCTRL_PIN(TEGRA_PIN_DDR_DQ16, "DDR_DQ16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINCTRL_PIN(TEGRA_PIN_DDR_DQ17, "DDR_DQ17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINCTRL_PIN(TEGRA_PIN_DDR_DQ18, "DDR_DQ18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINCTRL_PIN(TEGRA_PIN_DDR_DQ19, "DDR_DQ19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINCTRL_PIN(TEGRA_PIN_DDR_DQ20, "DDR_DQ20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINCTRL_PIN(TEGRA_PIN_DDR_DQ21, "DDR_DQ21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINCTRL_PIN(TEGRA_PIN_DDR_DQ22, "DDR_DQ22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINCTRL_PIN(TEGRA_PIN_DDR_DQ23, "DDR_DQ23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINCTRL_PIN(TEGRA_PIN_DDR_DQ24, "DDR_DQ24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINCTRL_PIN(TEGRA_PIN_DDR_DQ25, "DDR_DQ25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINCTRL_PIN(TEGRA_PIN_DDR_DQ26, "DDR_DQ26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PINCTRL_PIN(TEGRA_PIN_DDR_DQ27, "DDR_DQ27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINCTRL_PIN(TEGRA_PIN_DDR_DQ28, "DDR_DQ28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINCTRL_PIN(TEGRA_PIN_DDR_DQ29, "DDR_DQ29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINCTRL_PIN(TEGRA_PIN_DDR_DQ30, "DDR_DQ30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINCTRL_PIN(TEGRA_PIN_DDR_DQ31, "DDR_DQ31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINCTRL_PIN(TEGRA_PIN_DDR_CS0_N, "DDR_CS0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINCTRL_PIN(TEGRA_PIN_DDR_CS1_N, "DDR_CS1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINCTRL_PIN(TEGRA_PIN_SYS_RESET, "SYS_RESET"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINCTRL_PIN(TEGRA_PIN_JTAG_TRST_N, "JTAG_TRST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINCTRL_PIN(TEGRA_PIN_JTAG_TDO, "JTAG_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINCTRL_PIN(TEGRA_PIN_JTAG_TMS, "JTAG_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINCTRL_PIN(TEGRA_PIN_JTAG_TCK, "JTAG_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINCTRL_PIN(TEGRA_PIN_JTAG_TDI, "JTAG_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINCTRL_PIN(TEGRA_PIN_TEST_MODE_EN, "TEST_MODE_EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const unsigned ata_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) TEGRA_PIN_GMI_CS6_N_PI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) TEGRA_PIN_GMI_CS7_N_PI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) TEGRA_PIN_GMI_RST_N_PI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const unsigned atb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) TEGRA_PIN_GMI_CS5_N_PI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) TEGRA_PIN_GMI_DPD_PT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const unsigned atc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) TEGRA_PIN_GMI_IORDY_PI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) TEGRA_PIN_GMI_WAIT_PI7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) TEGRA_PIN_GMI_ADV_N_PK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) TEGRA_PIN_GMI_CLK_PK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) TEGRA_PIN_GMI_CS2_N_PK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) TEGRA_PIN_GMI_CS3_N_PK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) TEGRA_PIN_GMI_CS4_N_PK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) TEGRA_PIN_GMI_AD0_PG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) TEGRA_PIN_GMI_AD1_PG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) TEGRA_PIN_GMI_AD2_PG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) TEGRA_PIN_GMI_AD3_PG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) TEGRA_PIN_GMI_AD4_PG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) TEGRA_PIN_GMI_AD5_PG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) TEGRA_PIN_GMI_AD6_PG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) TEGRA_PIN_GMI_AD7_PG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) TEGRA_PIN_GMI_HIOW_N_PI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) TEGRA_PIN_GMI_HIOR_N_PI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const unsigned atd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) TEGRA_PIN_GMI_AD8_PH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) TEGRA_PIN_GMI_AD9_PH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) TEGRA_PIN_GMI_AD10_PH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) TEGRA_PIN_GMI_AD11_PH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static const unsigned ate_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) TEGRA_PIN_GMI_AD12_PH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) TEGRA_PIN_GMI_AD13_PH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) TEGRA_PIN_GMI_AD14_PH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) TEGRA_PIN_GMI_AD15_PH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const unsigned cdev1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) TEGRA_PIN_DAP_MCLK1_PW4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const unsigned cdev2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) TEGRA_PIN_DAP_MCLK2_PW5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const unsigned crtp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) TEGRA_PIN_CRT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) TEGRA_PIN_CRT_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const unsigned csus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) TEGRA_PIN_VI_MCLK_PT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const unsigned dap1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) TEGRA_PIN_DAP1_FS_PN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) TEGRA_PIN_DAP1_DIN_PN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) TEGRA_PIN_DAP1_DOUT_PN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) TEGRA_PIN_DAP1_SCLK_PN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const unsigned dap2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) TEGRA_PIN_DAP2_FS_PA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) TEGRA_PIN_DAP2_SCLK_PA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) TEGRA_PIN_DAP2_DIN_PA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) TEGRA_PIN_DAP2_DOUT_PA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const unsigned dap3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) TEGRA_PIN_DAP3_FS_PP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) TEGRA_PIN_DAP3_DIN_PP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) TEGRA_PIN_DAP3_DOUT_PP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) TEGRA_PIN_DAP3_SCLK_PP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const unsigned dap4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) TEGRA_PIN_DAP4_FS_PP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) TEGRA_PIN_DAP4_DIN_PP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) TEGRA_PIN_DAP4_DOUT_PP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) TEGRA_PIN_DAP4_SCLK_PP7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const unsigned ddc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) TEGRA_PIN_DDC_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) TEGRA_PIN_DDC_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const unsigned dta_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) TEGRA_PIN_VI_D0_PT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) TEGRA_PIN_VI_D1_PD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static const unsigned dtb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) TEGRA_PIN_VI_D10_PT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) TEGRA_PIN_VI_D11_PT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static const unsigned dtc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) TEGRA_PIN_VI_HSYNC_PD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) TEGRA_PIN_VI_VSYNC_PD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const unsigned dtd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) TEGRA_PIN_VI_PCLK_PT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) TEGRA_PIN_VI_D2_PL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) TEGRA_PIN_VI_D3_PL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) TEGRA_PIN_VI_D4_PL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TEGRA_PIN_VI_D5_PL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) TEGRA_PIN_VI_D6_PL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) TEGRA_PIN_VI_D7_PL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) TEGRA_PIN_VI_D8_PL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) TEGRA_PIN_VI_D9_PL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const unsigned dte_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) TEGRA_PIN_VI_GP0_PBB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) TEGRA_PIN_VI_GP3_PBB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) TEGRA_PIN_VI_GP4_PBB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) TEGRA_PIN_VI_GP5_PD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TEGRA_PIN_VI_GP6_PA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static const unsigned dtf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) TEGRA_PIN_CAM_I2C_SCL_PBB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) TEGRA_PIN_CAM_I2C_SDA_PBB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static const unsigned gma_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) TEGRA_PIN_GMI_AD20_PAA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) TEGRA_PIN_GMI_AD21_PAA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) TEGRA_PIN_GMI_AD22_PAA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) TEGRA_PIN_GMI_AD23_PAA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const unsigned gmb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) TEGRA_PIN_GMI_WP_N_PC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const unsigned gmc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) TEGRA_PIN_GMI_AD16_PJ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) TEGRA_PIN_GMI_AD17_PB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) TEGRA_PIN_GMI_AD18_PB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) TEGRA_PIN_GMI_AD19_PK7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const unsigned gmd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) TEGRA_PIN_GMI_CS0_N_PJ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) TEGRA_PIN_GMI_CS1_N_PJ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const unsigned gme_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) TEGRA_PIN_GMI_AD24_PAA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) TEGRA_PIN_GMI_AD25_PAA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) TEGRA_PIN_GMI_AD26_PAA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) TEGRA_PIN_GMI_AD27_PAA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const unsigned gpu_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) TEGRA_PIN_PU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TEGRA_PIN_PU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) TEGRA_PIN_PU2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) TEGRA_PIN_PU3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) TEGRA_PIN_PU4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TEGRA_PIN_PU5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) TEGRA_PIN_PU6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const unsigned gpu7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) TEGRA_PIN_JTAG_RTCK_PU7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const unsigned gpv_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) TEGRA_PIN_PV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) TEGRA_PIN_PV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) TEGRA_PIN_PV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const unsigned hdint_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) TEGRA_PIN_HDMI_INT_N_PN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const unsigned i2cp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) TEGRA_PIN_PWR_I2C_SCL_PZ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) TEGRA_PIN_PWR_I2C_SDA_PZ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const unsigned irrx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) TEGRA_PIN_UART2_RTS_N_PJ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const unsigned irtx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) TEGRA_PIN_UART2_CTS_N_PJ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static const unsigned kbca_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) TEGRA_PIN_KB_ROW0_PR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) TEGRA_PIN_KB_ROW1_PR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) TEGRA_PIN_KB_ROW2_PR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const unsigned kbcb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) TEGRA_PIN_KB_ROW7_PR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) TEGRA_PIN_KB_ROW8_PS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) TEGRA_PIN_KB_ROW9_PS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) TEGRA_PIN_KB_ROW10_PS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) TEGRA_PIN_KB_ROW11_PS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) TEGRA_PIN_KB_ROW12_PS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) TEGRA_PIN_KB_ROW13_PS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) TEGRA_PIN_KB_ROW14_PS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) TEGRA_PIN_KB_ROW15_PS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static const unsigned kbcc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) TEGRA_PIN_KB_COL0_PQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) TEGRA_PIN_KB_COL1_PQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const unsigned kbcd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) TEGRA_PIN_KB_ROW3_PR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) TEGRA_PIN_KB_ROW4_PR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) TEGRA_PIN_KB_ROW5_PR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) TEGRA_PIN_KB_ROW6_PR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static const unsigned kbce_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) TEGRA_PIN_KB_COL7_PQ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const unsigned kbcf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) TEGRA_PIN_KB_COL2_PQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) TEGRA_PIN_KB_COL3_PQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) TEGRA_PIN_KB_COL4_PQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) TEGRA_PIN_KB_COL5_PQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) TEGRA_PIN_KB_COL6_PQ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const unsigned lcsn_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) TEGRA_PIN_LCD_CS0_N_PN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static const unsigned ld0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) TEGRA_PIN_LCD_D0_PE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const unsigned ld1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) TEGRA_PIN_LCD_D1_PE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const unsigned ld2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) TEGRA_PIN_LCD_D2_PE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const unsigned ld3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) TEGRA_PIN_LCD_D3_PE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const unsigned ld4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) TEGRA_PIN_LCD_D4_PE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const unsigned ld5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) TEGRA_PIN_LCD_D5_PE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const unsigned ld6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) TEGRA_PIN_LCD_D6_PE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const unsigned ld7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) TEGRA_PIN_LCD_D7_PE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static const unsigned ld8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) TEGRA_PIN_LCD_D8_PF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const unsigned ld9_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) TEGRA_PIN_LCD_D9_PF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static const unsigned ld10_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) TEGRA_PIN_LCD_D10_PF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const unsigned ld11_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) TEGRA_PIN_LCD_D11_PF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const unsigned ld12_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) TEGRA_PIN_LCD_D12_PF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const unsigned ld13_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) TEGRA_PIN_LCD_D13_PF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const unsigned ld14_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) TEGRA_PIN_LCD_D14_PF6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const unsigned ld15_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) TEGRA_PIN_LCD_D15_PF7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const unsigned ld16_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) TEGRA_PIN_LCD_D16_PM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const unsigned ld17_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) TEGRA_PIN_LCD_D17_PM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const unsigned ldc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) TEGRA_PIN_LCD_DC0_PN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static const unsigned ldi_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) TEGRA_PIN_LCD_D22_PM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const unsigned lhp0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) TEGRA_PIN_LCD_D21_PM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const unsigned lhp1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) TEGRA_PIN_LCD_D18_PM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static const unsigned lhp2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) TEGRA_PIN_LCD_D19_PM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static const unsigned lhs_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) TEGRA_PIN_LCD_HSYNC_PJ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const unsigned lm0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) TEGRA_PIN_LCD_CS1_N_PW0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static const unsigned lm1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) TEGRA_PIN_LCD_M1_PW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static const unsigned lpp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) TEGRA_PIN_LCD_D23_PM7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const unsigned lpw0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) TEGRA_PIN_LCD_PWR0_PB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const unsigned lpw1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) TEGRA_PIN_LCD_PWR1_PC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static const unsigned lpw2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) TEGRA_PIN_LCD_PWR2_PC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static const unsigned lsc0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) TEGRA_PIN_LCD_PCLK_PB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static const unsigned lsc1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) TEGRA_PIN_LCD_WR_N_PZ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static const unsigned lsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) TEGRA_PIN_LCD_SCK_PZ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const unsigned lsda_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) TEGRA_PIN_LCD_SDOUT_PN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static const unsigned lsdi_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) TEGRA_PIN_LCD_SDIN_PZ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static const unsigned lspi_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) TEGRA_PIN_LCD_DE_PJ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static const unsigned lvp0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) TEGRA_PIN_LCD_DC1_PV7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static const unsigned lvp1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) TEGRA_PIN_LCD_D20_PM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static const unsigned lvs_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) TEGRA_PIN_LCD_VSYNC_PJ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static const unsigned ls_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) TEGRA_PIN_LCD_PWR0_PB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) TEGRA_PIN_LCD_PWR1_PC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) TEGRA_PIN_LCD_PWR2_PC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) TEGRA_PIN_LCD_SDIN_PZ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) TEGRA_PIN_LCD_SDOUT_PN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) TEGRA_PIN_LCD_WR_N_PZ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) TEGRA_PIN_LCD_CS0_N_PN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) TEGRA_PIN_LCD_DC0_PN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) TEGRA_PIN_LCD_SCK_PZ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static const unsigned lc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) TEGRA_PIN_LCD_PCLK_PB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) TEGRA_PIN_LCD_DE_PJ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) TEGRA_PIN_LCD_HSYNC_PJ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) TEGRA_PIN_LCD_VSYNC_PJ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) TEGRA_PIN_LCD_CS1_N_PW0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) TEGRA_PIN_LCD_M1_PW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) TEGRA_PIN_LCD_DC1_PV7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) TEGRA_PIN_HDMI_INT_N_PN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static const unsigned ld17_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) TEGRA_PIN_LCD_D0_PE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) TEGRA_PIN_LCD_D1_PE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) TEGRA_PIN_LCD_D2_PE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) TEGRA_PIN_LCD_D3_PE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) TEGRA_PIN_LCD_D4_PE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) TEGRA_PIN_LCD_D5_PE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) TEGRA_PIN_LCD_D6_PE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) TEGRA_PIN_LCD_D7_PE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) TEGRA_PIN_LCD_D8_PF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) TEGRA_PIN_LCD_D9_PF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) TEGRA_PIN_LCD_D10_PF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) TEGRA_PIN_LCD_D11_PF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) TEGRA_PIN_LCD_D12_PF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) TEGRA_PIN_LCD_D13_PF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) TEGRA_PIN_LCD_D14_PF6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) TEGRA_PIN_LCD_D15_PF7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) TEGRA_PIN_LCD_D16_PM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) TEGRA_PIN_LCD_D17_PM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static const unsigned ld19_18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) TEGRA_PIN_LCD_D18_PM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) TEGRA_PIN_LCD_D19_PM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static const unsigned ld21_20_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) TEGRA_PIN_LCD_D20_PM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) TEGRA_PIN_LCD_D21_PM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const unsigned ld23_22_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) TEGRA_PIN_LCD_D22_PM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) TEGRA_PIN_LCD_D23_PM7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static const unsigned owc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) TEGRA_PIN_OWC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static const unsigned pmc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) TEGRA_PIN_LED_BLINK_PBB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) TEGRA_PIN_SYS_CLK_REQ_PZ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) TEGRA_PIN_CORE_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) TEGRA_PIN_CPU_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) TEGRA_PIN_PWR_INT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static const unsigned pta_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) TEGRA_PIN_GEN2_I2C_SCL_PT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) TEGRA_PIN_GEN2_I2C_SDA_PT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const unsigned rm_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) TEGRA_PIN_GEN1_I2C_SCL_PC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) TEGRA_PIN_GEN1_I2C_SDA_PC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const unsigned sdb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) TEGRA_PIN_SDIO3_CMD_PA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static const unsigned sdc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) TEGRA_PIN_SDIO3_DAT0_PB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) TEGRA_PIN_SDIO3_DAT1_PB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) TEGRA_PIN_SDIO3_DAT2_PB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) TEGRA_PIN_SDIO3_DAT3_PB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const unsigned sdd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) TEGRA_PIN_SDIO3_CLK_PA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static const unsigned sdio1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) TEGRA_PIN_SDIO1_CLK_PZ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) TEGRA_PIN_SDIO1_CMD_PZ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) TEGRA_PIN_SDIO1_DAT0_PY7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) TEGRA_PIN_SDIO1_DAT1_PY6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) TEGRA_PIN_SDIO1_DAT2_PY5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) TEGRA_PIN_SDIO1_DAT3_PY4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static const unsigned slxa_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) TEGRA_PIN_SDIO3_DAT4_PD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static const unsigned slxc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) TEGRA_PIN_SDIO3_DAT6_PD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static const unsigned slxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) TEGRA_PIN_SDIO3_DAT7_PD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static const unsigned slxk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) TEGRA_PIN_SDIO3_DAT5_PD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static const unsigned spdi_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) TEGRA_PIN_SPDIF_IN_PK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static const unsigned spdo_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) TEGRA_PIN_SPDIF_OUT_PK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static const unsigned spia_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) TEGRA_PIN_SPI2_MOSI_PX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static const unsigned spib_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) TEGRA_PIN_SPI2_MISO_PX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static const unsigned spic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) TEGRA_PIN_SPI2_CS0_N_PX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) TEGRA_PIN_SPI2_SCK_PX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static const unsigned spid_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) TEGRA_PIN_SPI1_MOSI_PX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static const unsigned spie_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) TEGRA_PIN_SPI1_CS0_N_PX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) TEGRA_PIN_SPI1_SCK_PX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const unsigned spif_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) TEGRA_PIN_SPI1_MISO_PX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static const unsigned spig_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) TEGRA_PIN_SPI2_CS1_N_PW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static const unsigned spih_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) TEGRA_PIN_SPI2_CS2_N_PW3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static const unsigned uaa_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) TEGRA_PIN_ULPI_DATA0_PO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) TEGRA_PIN_ULPI_DATA1_PO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) TEGRA_PIN_ULPI_DATA2_PO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) TEGRA_PIN_ULPI_DATA3_PO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static const unsigned uab_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) TEGRA_PIN_ULPI_DATA4_PO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) TEGRA_PIN_ULPI_DATA5_PO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) TEGRA_PIN_ULPI_DATA6_PO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) TEGRA_PIN_ULPI_DATA7_PO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static const unsigned uac_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) TEGRA_PIN_PV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) TEGRA_PIN_PV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) TEGRA_PIN_PV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) TEGRA_PIN_PV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static const unsigned ck32_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) TEGRA_PIN_CLK_32_K_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const unsigned uad_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) TEGRA_PIN_UART2_RXD_PC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) TEGRA_PIN_UART2_TXD_PC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static const unsigned uca_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) TEGRA_PIN_UART3_RXD_PW7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) TEGRA_PIN_UART3_TXD_PW6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static const unsigned ucb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) TEGRA_PIN_UART3_CTS_N_PA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) TEGRA_PIN_UART3_RTS_N_PC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const unsigned uda_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) TEGRA_PIN_ULPI_CLK_PY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) TEGRA_PIN_ULPI_DIR_PY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) TEGRA_PIN_ULPI_NXT_PY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) TEGRA_PIN_ULPI_STP_PY3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static const unsigned ddrc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) TEGRA_PIN_DDR_COMP_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) TEGRA_PIN_DDR_COMP_PU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static const unsigned pmca_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) TEGRA_PIN_LED_BLINK_PBB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static const unsigned pmcb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) TEGRA_PIN_SYS_CLK_REQ_PZ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static const unsigned pmcc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) TEGRA_PIN_CORE_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const unsigned pmcd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) TEGRA_PIN_CPU_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static const unsigned pmce_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) TEGRA_PIN_PWR_INT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static const unsigned xm2c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) TEGRA_PIN_DDR_A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) TEGRA_PIN_DDR_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) TEGRA_PIN_DDR_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) TEGRA_PIN_DDR_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) TEGRA_PIN_DDR_A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) TEGRA_PIN_DDR_A5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) TEGRA_PIN_DDR_A6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) TEGRA_PIN_DDR_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) TEGRA_PIN_DDR_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) TEGRA_PIN_DDR_A9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) TEGRA_PIN_DDR_A10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) TEGRA_PIN_DDR_A11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) TEGRA_PIN_DDR_A12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) TEGRA_PIN_DDR_A13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) TEGRA_PIN_DDR_A14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) TEGRA_PIN_DDR_CAS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) TEGRA_PIN_DDR_BA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) TEGRA_PIN_DDR_BA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) TEGRA_PIN_DDR_BA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) TEGRA_PIN_DDR_DQS0P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) TEGRA_PIN_DDR_DQS0N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) TEGRA_PIN_DDR_DQS1P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) TEGRA_PIN_DDR_DQS1N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) TEGRA_PIN_DDR_DQS2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) TEGRA_PIN_DDR_DQS2N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) TEGRA_PIN_DDR_DQS3P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) TEGRA_PIN_DDR_DQS3N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) TEGRA_PIN_DDR_CS0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) TEGRA_PIN_DDR_CS1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) TEGRA_PIN_DDR_CKE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) TEGRA_PIN_DDR_CKE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) TEGRA_PIN_DDR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) TEGRA_PIN_DDR_CLK_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) TEGRA_PIN_DDR_DM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) TEGRA_PIN_DDR_DM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) TEGRA_PIN_DDR_DM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) TEGRA_PIN_DDR_DM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) TEGRA_PIN_DDR_ODT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) TEGRA_PIN_DDR_RAS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) TEGRA_PIN_DDR_WE_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) TEGRA_PIN_DDR_QUSE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) TEGRA_PIN_DDR_QUSE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) TEGRA_PIN_DDR_QUSE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) TEGRA_PIN_DDR_QUSE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static const unsigned xm2d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) TEGRA_PIN_DDR_DQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) TEGRA_PIN_DDR_DQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) TEGRA_PIN_DDR_DQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) TEGRA_PIN_DDR_DQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) TEGRA_PIN_DDR_DQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) TEGRA_PIN_DDR_DQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) TEGRA_PIN_DDR_DQ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) TEGRA_PIN_DDR_DQ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) TEGRA_PIN_DDR_DQ8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) TEGRA_PIN_DDR_DQ9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) TEGRA_PIN_DDR_DQ10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) TEGRA_PIN_DDR_DQ11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) TEGRA_PIN_DDR_DQ12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) TEGRA_PIN_DDR_DQ13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) TEGRA_PIN_DDR_DQ14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) TEGRA_PIN_DDR_DQ15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) TEGRA_PIN_DDR_DQ16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) TEGRA_PIN_DDR_DQ17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) TEGRA_PIN_DDR_DQ18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) TEGRA_PIN_DDR_DQ19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) TEGRA_PIN_DDR_DQ20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) TEGRA_PIN_DDR_DQ21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) TEGRA_PIN_DDR_DQ22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) TEGRA_PIN_DDR_DQ23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) TEGRA_PIN_DDR_DQ24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) TEGRA_PIN_DDR_DQ25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) TEGRA_PIN_DDR_DQ26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) TEGRA_PIN_DDR_DQ27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) TEGRA_PIN_DDR_DQ28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) TEGRA_PIN_DDR_DQ29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) TEGRA_PIN_DDR_DQ30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) TEGRA_PIN_DDR_DQ31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static const unsigned drive_ao1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) TEGRA_PIN_SYS_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) TEGRA_PIN_PWR_I2C_SCL_PZ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) TEGRA_PIN_PWR_I2C_SDA_PZ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) TEGRA_PIN_KB_ROW0_PR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) TEGRA_PIN_KB_ROW1_PR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) TEGRA_PIN_KB_ROW2_PR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) TEGRA_PIN_KB_ROW3_PR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) TEGRA_PIN_KB_ROW4_PR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) TEGRA_PIN_KB_ROW5_PR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) TEGRA_PIN_KB_ROW6_PR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) TEGRA_PIN_KB_ROW7_PR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static const unsigned drive_ao2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) TEGRA_PIN_KB_ROW8_PS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) TEGRA_PIN_KB_ROW9_PS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) TEGRA_PIN_KB_ROW10_PS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) TEGRA_PIN_KB_ROW11_PS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) TEGRA_PIN_KB_ROW12_PS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) TEGRA_PIN_KB_ROW13_PS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) TEGRA_PIN_KB_ROW14_PS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) TEGRA_PIN_KB_ROW15_PS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) TEGRA_PIN_KB_COL0_PQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) TEGRA_PIN_KB_COL1_PQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) TEGRA_PIN_KB_COL2_PQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) TEGRA_PIN_KB_COL3_PQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) TEGRA_PIN_KB_COL4_PQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) TEGRA_PIN_KB_COL5_PQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) TEGRA_PIN_KB_COL6_PQ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) TEGRA_PIN_KB_COL7_PQ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) TEGRA_PIN_LED_BLINK_PBB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) TEGRA_PIN_SYS_CLK_REQ_PZ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) TEGRA_PIN_CORE_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) TEGRA_PIN_CPU_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) TEGRA_PIN_PWR_INT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) TEGRA_PIN_CLK_32_K_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static const unsigned drive_at1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) TEGRA_PIN_GMI_IORDY_PI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) TEGRA_PIN_GMI_AD8_PH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) TEGRA_PIN_GMI_AD9_PH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) TEGRA_PIN_GMI_AD10_PH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) TEGRA_PIN_GMI_AD11_PH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) TEGRA_PIN_GMI_AD12_PH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) TEGRA_PIN_GMI_AD13_PH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) TEGRA_PIN_GMI_AD14_PH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) TEGRA_PIN_GMI_AD15_PH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) TEGRA_PIN_GMI_CS7_N_PI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) TEGRA_PIN_GMI_DPD_PT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) TEGRA_PIN_GEN2_I2C_SCL_PT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) TEGRA_PIN_GEN2_I2C_SDA_PT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static const unsigned drive_at2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) TEGRA_PIN_GMI_WAIT_PI7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) TEGRA_PIN_GMI_ADV_N_PK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) TEGRA_PIN_GMI_CLK_PK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) TEGRA_PIN_GMI_CS6_N_PI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) TEGRA_PIN_GMI_CS5_N_PI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) TEGRA_PIN_GMI_CS4_N_PK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) TEGRA_PIN_GMI_CS3_N_PK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) TEGRA_PIN_GMI_CS2_N_PK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) TEGRA_PIN_GMI_AD0_PG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) TEGRA_PIN_GMI_AD1_PG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) TEGRA_PIN_GMI_AD2_PG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) TEGRA_PIN_GMI_AD3_PG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) TEGRA_PIN_GMI_AD4_PG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) TEGRA_PIN_GMI_AD5_PG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) TEGRA_PIN_GMI_AD6_PG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) TEGRA_PIN_GMI_AD7_PG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) TEGRA_PIN_GMI_HIOW_N_PI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) TEGRA_PIN_GMI_HIOR_N_PI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) TEGRA_PIN_GMI_RST_N_PI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static const unsigned drive_cdev1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) TEGRA_PIN_DAP_MCLK1_PW4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static const unsigned drive_cdev2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) TEGRA_PIN_DAP_MCLK2_PW5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static const unsigned drive_csus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) TEGRA_PIN_VI_MCLK_PT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static const unsigned drive_dap1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) TEGRA_PIN_DAP1_FS_PN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) TEGRA_PIN_DAP1_DIN_PN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) TEGRA_PIN_DAP1_DOUT_PN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) TEGRA_PIN_DAP1_SCLK_PN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) TEGRA_PIN_SPDIF_OUT_PK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) TEGRA_PIN_SPDIF_IN_PK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static const unsigned drive_dap2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) TEGRA_PIN_DAP2_FS_PA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) TEGRA_PIN_DAP2_SCLK_PA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) TEGRA_PIN_DAP2_DIN_PA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) TEGRA_PIN_DAP2_DOUT_PA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static const unsigned drive_dap3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) TEGRA_PIN_DAP3_FS_PP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) TEGRA_PIN_DAP3_DIN_PP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) TEGRA_PIN_DAP3_DOUT_PP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) TEGRA_PIN_DAP3_SCLK_PP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static const unsigned drive_dap4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) TEGRA_PIN_DAP4_FS_PP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) TEGRA_PIN_DAP4_DIN_PP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) TEGRA_PIN_DAP4_DOUT_PP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) TEGRA_PIN_DAP4_SCLK_PP7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static const unsigned drive_dbg_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) TEGRA_PIN_PU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) TEGRA_PIN_PU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) TEGRA_PIN_PU2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) TEGRA_PIN_PU3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) TEGRA_PIN_PU4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) TEGRA_PIN_PU5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) TEGRA_PIN_PU6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) TEGRA_PIN_JTAG_RTCK_PU7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) TEGRA_PIN_GEN1_I2C_SDA_PC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) TEGRA_PIN_GEN1_I2C_SCL_PC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) TEGRA_PIN_JTAG_TRST_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) TEGRA_PIN_JTAG_TDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) TEGRA_PIN_JTAG_TMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) TEGRA_PIN_JTAG_TCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) TEGRA_PIN_JTAG_TDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) TEGRA_PIN_TEST_MODE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static const unsigned drive_lcd1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) TEGRA_PIN_LCD_PWR1_PC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) TEGRA_PIN_LCD_PWR2_PC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) TEGRA_PIN_LCD_SDIN_PZ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) TEGRA_PIN_LCD_SDOUT_PN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) TEGRA_PIN_LCD_WR_N_PZ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) TEGRA_PIN_LCD_CS0_N_PN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) TEGRA_PIN_LCD_DC0_PN6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) TEGRA_PIN_LCD_SCK_PZ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static const unsigned drive_lcd2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) TEGRA_PIN_LCD_PWR0_PB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) TEGRA_PIN_LCD_PCLK_PB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) TEGRA_PIN_LCD_DE_PJ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) TEGRA_PIN_LCD_HSYNC_PJ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) TEGRA_PIN_LCD_VSYNC_PJ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) TEGRA_PIN_LCD_D0_PE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) TEGRA_PIN_LCD_D1_PE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) TEGRA_PIN_LCD_D2_PE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) TEGRA_PIN_LCD_D3_PE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) TEGRA_PIN_LCD_D4_PE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) TEGRA_PIN_LCD_D5_PE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) TEGRA_PIN_LCD_D6_PE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) TEGRA_PIN_LCD_D7_PE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) TEGRA_PIN_LCD_D8_PF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) TEGRA_PIN_LCD_D9_PF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) TEGRA_PIN_LCD_D10_PF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) TEGRA_PIN_LCD_D11_PF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) TEGRA_PIN_LCD_D12_PF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) TEGRA_PIN_LCD_D13_PF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) TEGRA_PIN_LCD_D14_PF6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) TEGRA_PIN_LCD_D15_PF7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) TEGRA_PIN_LCD_D16_PM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) TEGRA_PIN_LCD_D17_PM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) TEGRA_PIN_LCD_D18_PM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) TEGRA_PIN_LCD_D19_PM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) TEGRA_PIN_LCD_D20_PM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) TEGRA_PIN_LCD_D21_PM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) TEGRA_PIN_LCD_D22_PM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) TEGRA_PIN_LCD_D23_PM7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) TEGRA_PIN_LCD_CS1_N_PW0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) TEGRA_PIN_LCD_M1_PW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) TEGRA_PIN_LCD_DC1_PV7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) TEGRA_PIN_HDMI_INT_N_PN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static const unsigned drive_sdmmc2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) TEGRA_PIN_SDIO3_DAT4_PD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) TEGRA_PIN_SDIO3_DAT5_PD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) TEGRA_PIN_SDIO3_DAT6_PD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) TEGRA_PIN_SDIO3_DAT7_PD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static const unsigned drive_sdmmc3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) TEGRA_PIN_SDIO3_CLK_PA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) TEGRA_PIN_SDIO3_CMD_PA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) TEGRA_PIN_SDIO3_DAT0_PB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) TEGRA_PIN_SDIO3_DAT1_PB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) TEGRA_PIN_SDIO3_DAT2_PB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) TEGRA_PIN_SDIO3_DAT3_PB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) TEGRA_PIN_PV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) TEGRA_PIN_PV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) TEGRA_PIN_PV6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static const unsigned drive_spi_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) TEGRA_PIN_SPI2_MOSI_PX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) TEGRA_PIN_SPI2_MISO_PX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) TEGRA_PIN_SPI2_SCK_PX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) TEGRA_PIN_SPI2_CS0_N_PX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) TEGRA_PIN_SPI1_MOSI_PX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) TEGRA_PIN_SPI1_SCK_PX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) TEGRA_PIN_SPI1_CS0_N_PX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) TEGRA_PIN_SPI1_MISO_PX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) TEGRA_PIN_SPI2_CS1_N_PW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) TEGRA_PIN_SPI2_CS2_N_PW3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static const unsigned drive_uaa_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) TEGRA_PIN_ULPI_DATA0_PO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) TEGRA_PIN_ULPI_DATA1_PO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) TEGRA_PIN_ULPI_DATA2_PO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) TEGRA_PIN_ULPI_DATA3_PO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static const unsigned drive_uab_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) TEGRA_PIN_ULPI_DATA4_PO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) TEGRA_PIN_ULPI_DATA5_PO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) TEGRA_PIN_ULPI_DATA6_PO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) TEGRA_PIN_ULPI_DATA7_PO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) TEGRA_PIN_PV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) TEGRA_PIN_PV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) TEGRA_PIN_PV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) TEGRA_PIN_PV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static const unsigned drive_uart2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) TEGRA_PIN_UART2_TXD_PC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) TEGRA_PIN_UART2_RXD_PC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) TEGRA_PIN_UART2_RTS_N_PJ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) TEGRA_PIN_UART2_CTS_N_PJ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static const unsigned drive_uart3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) TEGRA_PIN_UART3_TXD_PW6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) TEGRA_PIN_UART3_RXD_PW7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) TEGRA_PIN_UART3_RTS_N_PC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) TEGRA_PIN_UART3_CTS_N_PA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static const unsigned drive_vi1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) TEGRA_PIN_VI_D0_PT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) TEGRA_PIN_VI_D1_PD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) TEGRA_PIN_VI_D2_PL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) TEGRA_PIN_VI_D3_PL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) TEGRA_PIN_VI_D4_PL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) TEGRA_PIN_VI_D5_PL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) TEGRA_PIN_VI_D6_PL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) TEGRA_PIN_VI_D7_PL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) TEGRA_PIN_VI_D8_PL6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) TEGRA_PIN_VI_D9_PL7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) TEGRA_PIN_VI_D10_PT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) TEGRA_PIN_VI_D11_PT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) TEGRA_PIN_VI_PCLK_PT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) TEGRA_PIN_VI_VSYNC_PD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) TEGRA_PIN_VI_HSYNC_PD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static const unsigned drive_vi2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) TEGRA_PIN_VI_GP0_PBB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) TEGRA_PIN_CAM_I2C_SCL_PBB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) TEGRA_PIN_CAM_I2C_SDA_PBB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) TEGRA_PIN_VI_GP3_PBB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) TEGRA_PIN_VI_GP4_PBB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) TEGRA_PIN_VI_GP5_PD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) TEGRA_PIN_VI_GP6_PA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) static const unsigned drive_xm2a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) TEGRA_PIN_DDR_A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) TEGRA_PIN_DDR_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) TEGRA_PIN_DDR_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) TEGRA_PIN_DDR_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) TEGRA_PIN_DDR_A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) TEGRA_PIN_DDR_A5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) TEGRA_PIN_DDR_A6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) TEGRA_PIN_DDR_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) TEGRA_PIN_DDR_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) TEGRA_PIN_DDR_A9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) TEGRA_PIN_DDR_A10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) TEGRA_PIN_DDR_A11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) TEGRA_PIN_DDR_A12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) TEGRA_PIN_DDR_A13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) TEGRA_PIN_DDR_A14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) TEGRA_PIN_DDR_BA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) TEGRA_PIN_DDR_BA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) TEGRA_PIN_DDR_BA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) TEGRA_PIN_DDR_CS0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) TEGRA_PIN_DDR_CS1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) TEGRA_PIN_DDR_ODT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) TEGRA_PIN_DDR_RAS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) TEGRA_PIN_DDR_CAS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) TEGRA_PIN_DDR_WE_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) TEGRA_PIN_DDR_CKE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) TEGRA_PIN_DDR_CKE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static const unsigned drive_xm2c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) TEGRA_PIN_DDR_DQS0P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) TEGRA_PIN_DDR_DQS0N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) TEGRA_PIN_DDR_DQS1P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) TEGRA_PIN_DDR_DQS1N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) TEGRA_PIN_DDR_DQS2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) TEGRA_PIN_DDR_DQS2N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) TEGRA_PIN_DDR_DQS3P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) TEGRA_PIN_DDR_DQS3N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) TEGRA_PIN_DDR_QUSE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) TEGRA_PIN_DDR_QUSE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) TEGRA_PIN_DDR_QUSE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) TEGRA_PIN_DDR_QUSE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static const unsigned drive_xm2d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) TEGRA_PIN_DDR_DQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) TEGRA_PIN_DDR_DQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) TEGRA_PIN_DDR_DQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) TEGRA_PIN_DDR_DQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) TEGRA_PIN_DDR_DQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) TEGRA_PIN_DDR_DQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) TEGRA_PIN_DDR_DQ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) TEGRA_PIN_DDR_DQ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) TEGRA_PIN_DDR_DQ8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) TEGRA_PIN_DDR_DQ9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) TEGRA_PIN_DDR_DQ10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) TEGRA_PIN_DDR_DQ11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) TEGRA_PIN_DDR_DQ12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) TEGRA_PIN_DDR_DQ13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) TEGRA_PIN_DDR_DQ14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) TEGRA_PIN_DDR_DQ15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) TEGRA_PIN_DDR_DQ16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) TEGRA_PIN_DDR_DQ17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) TEGRA_PIN_DDR_DQ18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) TEGRA_PIN_DDR_DQ19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) TEGRA_PIN_DDR_DQ20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) TEGRA_PIN_DDR_DQ21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) TEGRA_PIN_DDR_DQ22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) TEGRA_PIN_DDR_DQ23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) TEGRA_PIN_DDR_DQ24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) TEGRA_PIN_DDR_DQ25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) TEGRA_PIN_DDR_DQ26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) TEGRA_PIN_DDR_DQ27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) TEGRA_PIN_DDR_DQ28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) TEGRA_PIN_DDR_DQ29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) TEGRA_PIN_DDR_DQ30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) TEGRA_PIN_DDR_DQ31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) TEGRA_PIN_DDR_DM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) TEGRA_PIN_DDR_DM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) TEGRA_PIN_DDR_DM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) TEGRA_PIN_DDR_DM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static const unsigned drive_xm2clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) TEGRA_PIN_DDR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) TEGRA_PIN_DDR_CLK_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static const unsigned drive_sdio1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) TEGRA_PIN_SDIO1_CLK_PZ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) TEGRA_PIN_SDIO1_CMD_PZ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) TEGRA_PIN_SDIO1_DAT0_PY7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) TEGRA_PIN_SDIO1_DAT1_PY6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) TEGRA_PIN_SDIO1_DAT2_PY5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) TEGRA_PIN_SDIO1_DAT3_PY4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static const unsigned drive_crt_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) TEGRA_PIN_CRT_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) TEGRA_PIN_CRT_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static const unsigned drive_ddc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) TEGRA_PIN_DDC_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) TEGRA_PIN_DDC_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static const unsigned drive_gma_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) TEGRA_PIN_GMI_AD20_PAA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) TEGRA_PIN_GMI_AD21_PAA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) TEGRA_PIN_GMI_AD22_PAA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) TEGRA_PIN_GMI_AD23_PAA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static const unsigned drive_gmb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) TEGRA_PIN_GMI_WP_N_PC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static const unsigned drive_gmc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) TEGRA_PIN_GMI_AD16_PJ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) TEGRA_PIN_GMI_AD17_PB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) TEGRA_PIN_GMI_AD18_PB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) TEGRA_PIN_GMI_AD19_PK7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static const unsigned drive_gmd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) TEGRA_PIN_GMI_CS0_N_PJ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) TEGRA_PIN_GMI_CS1_N_PJ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static const unsigned drive_gme_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) TEGRA_PIN_GMI_AD24_PAA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) TEGRA_PIN_GMI_AD25_PAA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) TEGRA_PIN_GMI_AD26_PAA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) TEGRA_PIN_GMI_AD27_PAA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static const unsigned drive_owr_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) TEGRA_PIN_OWC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static const unsigned drive_uda_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) TEGRA_PIN_ULPI_CLK_PY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) TEGRA_PIN_ULPI_DIR_PY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) TEGRA_PIN_ULPI_NXT_PY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) TEGRA_PIN_ULPI_STP_PY3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) enum tegra_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) TEGRA_MUX_AHB_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) TEGRA_MUX_APB_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) TEGRA_MUX_AUDIO_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) TEGRA_MUX_CRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) TEGRA_MUX_DAP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) TEGRA_MUX_DAP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) TEGRA_MUX_DAP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) TEGRA_MUX_DAP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) TEGRA_MUX_DAP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) TEGRA_MUX_DISPLAYA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) TEGRA_MUX_DISPLAYB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) TEGRA_MUX_EMC_TEST0_DLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) TEGRA_MUX_EMC_TEST1_DLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) TEGRA_MUX_GMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) TEGRA_MUX_GMI_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) TEGRA_MUX_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) TEGRA_MUX_I2CP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) TEGRA_MUX_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) TEGRA_MUX_I2C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) TEGRA_MUX_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) TEGRA_MUX_IDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) TEGRA_MUX_IRDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) TEGRA_MUX_KBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) TEGRA_MUX_MIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) TEGRA_MUX_MIPI_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) TEGRA_MUX_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) TEGRA_MUX_OSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) TEGRA_MUX_OWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) TEGRA_MUX_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) TEGRA_MUX_PLLA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) TEGRA_MUX_PLLC_OUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) TEGRA_MUX_PLLM_OUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) TEGRA_MUX_PLLP_OUT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) TEGRA_MUX_PLLP_OUT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) TEGRA_MUX_PLLP_OUT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) TEGRA_MUX_PWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) TEGRA_MUX_PWR_INTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) TEGRA_MUX_PWR_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) TEGRA_MUX_RSVD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) TEGRA_MUX_RSVD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) TEGRA_MUX_RSVD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) TEGRA_MUX_RSVD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) TEGRA_MUX_RTCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) TEGRA_MUX_SDIO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) TEGRA_MUX_SDIO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) TEGRA_MUX_SDIO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) TEGRA_MUX_SDIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) TEGRA_MUX_SFLASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) TEGRA_MUX_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) TEGRA_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) TEGRA_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) TEGRA_MUX_SPI2_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) TEGRA_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) TEGRA_MUX_SPI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) TEGRA_MUX_TRACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) TEGRA_MUX_TWC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) TEGRA_MUX_UARTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) TEGRA_MUX_UARTB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) TEGRA_MUX_UARTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) TEGRA_MUX_UARTD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) TEGRA_MUX_UARTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) TEGRA_MUX_ULPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) TEGRA_MUX_VI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) TEGRA_MUX_VI_SENSOR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) TEGRA_MUX_XIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static struct tegra_function tegra20_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) FUNCTION(ahb_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) FUNCTION(apb_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) FUNCTION(audio_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) FUNCTION(crt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) FUNCTION(dap1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) FUNCTION(dap2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) FUNCTION(dap3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) FUNCTION(dap4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) FUNCTION(dap5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) FUNCTION(displaya),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) FUNCTION(displayb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) FUNCTION(emc_test0_dll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) FUNCTION(emc_test1_dll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) FUNCTION(gmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) FUNCTION(gmi_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) FUNCTION(hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) FUNCTION(i2cp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) FUNCTION(ide),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) FUNCTION(irda),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) FUNCTION(kbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) FUNCTION(mio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) FUNCTION(mipi_hs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) FUNCTION(nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) FUNCTION(osc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) FUNCTION(owr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) FUNCTION(pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) FUNCTION(plla_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) FUNCTION(pllc_out1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) FUNCTION(pllm_out1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) FUNCTION(pllp_out2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) FUNCTION(pllp_out3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) FUNCTION(pllp_out4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) FUNCTION(pwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) FUNCTION(pwr_intr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) FUNCTION(pwr_on),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) FUNCTION(rsvd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) FUNCTION(rsvd2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) FUNCTION(rsvd3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) FUNCTION(rsvd4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) FUNCTION(rtck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) FUNCTION(sdio1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) FUNCTION(sdio2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) FUNCTION(sdio3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) FUNCTION(sdio4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) FUNCTION(sflash),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) FUNCTION(spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) FUNCTION(spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) FUNCTION(spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) FUNCTION(spi2_alt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) FUNCTION(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) FUNCTION(spi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) FUNCTION(trace),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) FUNCTION(twc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) FUNCTION(uarta),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) FUNCTION(uartb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) FUNCTION(uartc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) FUNCTION(uartd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) FUNCTION(uarte),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) FUNCTION(ulpi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) FUNCTION(vi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) FUNCTION(vi_sensor_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) FUNCTION(xio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) #define TRISTATE_REG_A 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) #define PIN_MUX_CTL_REG_A 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) #define PULLUPDOWN_REG_A 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) #define PINGROUP_REG_A 0x868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /* Pin group with mux control, and typically tri-state and pull-up/down too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define MUX_PG(pg_name, f0, f1, f2, f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .funcs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) TEGRA_MUX_ ## f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) TEGRA_MUX_ ## f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) TEGRA_MUX_ ## f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) TEGRA_MUX_ ## f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .mux_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .mux_bit = mux_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .pupd_bank = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .pupd_bit = pupd_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .tri_reg = ((tri_r) - TRISTATE_REG_A), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .tri_bank = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .tri_bit = tri_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .einput_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .odrain_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .lock_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .ioreset_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .rcv_sel_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .drv_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .parked_bitmask = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /* Pin groups with only pull up and pull down control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) #define PULL_PG(pg_name, pupd_r, pupd_b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .mux_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .pupd_bank = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .pupd_bit = pupd_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .drv_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .parked_bitmask = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* Pin groups for drive strength registers (configurable version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) #define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) drvdn_b, drvup_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) slwr_b, slwr_w, slwf_b, slwf_w) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .name = "drive_" #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .pins = drive_##pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .mux_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .pupd_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .tri_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .drv_reg = ((r) - PINGROUP_REG_A), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .drv_bank = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .parked_bitmask = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .hsm_bit = hsm_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .schmitt_bit = schmitt_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .lpmd_bit = lpmd_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .drvdn_bit = drvdn_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .drvdn_width = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .drvup_bit = drvup_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .drvup_width = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .slwr_bit = slwr_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .slwr_width = slwr_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .slwf_bit = slwf_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .slwf_width = slwf_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .drvtype_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* Pin groups for drive strength registers (simple version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #define DRV_PG(pg_name, r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) DRV_PG_EXT(pg_name, r, 2, 3, 4, 12, 20, 28, 2, 30, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static const struct tegra_pingroup tegra20_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) /* name, f0, f1, f2, f3, tri r/b, mux r/b, pupd r/b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) MUX_PG(ata, IDE, NAND, GMI, RSVD4, 0x14, 0, 0x80, 24, 0xa0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) MUX_PG(atb, IDE, NAND, GMI, SDIO4, 0x14, 1, 0x80, 16, 0xa0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) MUX_PG(atc, IDE, NAND, GMI, SDIO4, 0x14, 2, 0x80, 22, 0xa0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) MUX_PG(atd, IDE, NAND, GMI, SDIO4, 0x14, 3, 0x80, 20, 0xa0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) MUX_PG(ate, IDE, NAND, GMI, RSVD4, 0x18, 25, 0x80, 12, 0xa0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) MUX_PG(crtp, CRT, RSVD2, RSVD3, RSVD4, 0x20, 14, 0x98, 20, 0xa4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) MUX_PG(csus, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, 0x14, 6, 0x88, 6, 0xac, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) MUX_PG(dap1, DAP1, RSVD2, GMI, SDIO2, 0x14, 7, 0x88, 20, 0xa0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) MUX_PG(dap2, DAP2, TWC, RSVD3, GMI, 0x14, 8, 0x88, 22, 0xa0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) MUX_PG(dap3, DAP3, RSVD2, RSVD3, RSVD4, 0x14, 9, 0x88, 24, 0xa0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) MUX_PG(dap4, DAP4, RSVD2, GMI, RSVD4, 0x14, 10, 0x88, 26, 0xa0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) MUX_PG(ddc, I2C2, RSVD2, RSVD3, RSVD4, 0x18, 31, 0x88, 0, 0xb0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) MUX_PG(dta, RSVD1, SDIO2, VI, RSVD4, 0x14, 11, 0x84, 20, 0xa0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) MUX_PG(dtb, RSVD1, RSVD2, VI, SPI1, 0x14, 12, 0x84, 22, 0xa0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) MUX_PG(dtc, RSVD1, RSVD2, VI, RSVD4, 0x14, 13, 0x84, 26, 0xa0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) MUX_PG(dtd, RSVD1, SDIO2, VI, RSVD4, 0x14, 14, 0x84, 28, 0xa0, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) MUX_PG(dte, RSVD1, RSVD2, VI, SPI1, 0x14, 15, 0x84, 30, 0xa0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) MUX_PG(dtf, I2C3, RSVD2, VI, RSVD4, 0x20, 12, 0x98, 30, 0xa0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) MUX_PG(gma, UARTE, SPI3, GMI, SDIO4, 0x14, 28, 0x84, 0, 0xb0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) MUX_PG(gmb, IDE, NAND, GMI, GMI_INT, 0x18, 29, 0x88, 28, 0xb0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) MUX_PG(gmc, UARTD, SPI4, GMI, SFLASH, 0x14, 29, 0x84, 2, 0xb0, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) MUX_PG(gmd, RSVD1, NAND, GMI, SFLASH, 0x18, 30, 0x88, 30, 0xb0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) MUX_PG(gme, RSVD1, DAP5, GMI, SDIO4, 0x18, 0, 0x8c, 0, 0xa8, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) MUX_PG(gpu, PWM, UARTA, GMI, RSVD4, 0x14, 16, 0x8c, 4, 0xa4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) MUX_PG(gpu7, RTCK, RSVD2, RSVD3, RSVD4, 0x20, 11, 0x98, 28, 0xa4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) MUX_PG(gpv, PCIE, RSVD2, RSVD3, RSVD4, 0x14, 17, 0x8c, 2, 0xa0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) MUX_PG(hdint, HDMI, RSVD2, RSVD3, RSVD4, 0x1c, 23, 0x84, 4, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) MUX_PG(i2cp, I2CP, RSVD2, RSVD3, RSVD4, 0x14, 18, 0x88, 8, 0xa4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) MUX_PG(irrx, UARTA, UARTB, GMI, SPI4, 0x14, 20, 0x88, 18, 0xa8, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) MUX_PG(irtx, UARTA, UARTB, GMI, SPI4, 0x14, 19, 0x88, 16, 0xa8, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) MUX_PG(kbca, KBC, NAND, SDIO2, EMC_TEST0_DLL, 0x14, 22, 0x88, 10, 0xa4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) MUX_PG(kbcb, KBC, NAND, SDIO2, MIO, 0x14, 21, 0x88, 12, 0xa4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) MUX_PG(kbcc, KBC, NAND, TRACE, EMC_TEST1_DLL, 0x18, 26, 0x88, 14, 0xa4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) MUX_PG(kbcd, KBC, NAND, SDIO2, MIO, 0x20, 10, 0x98, 26, 0xa4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) MUX_PG(kbce, KBC, NAND, OWR, RSVD4, 0x14, 26, 0x80, 28, 0xb0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) MUX_PG(kbcf, KBC, NAND, TRACE, MIO, 0x14, 27, 0x80, 26, 0xb0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) MUX_PG(lcsn, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 31, 0x90, 12, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) MUX_PG(ld0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 0, 0x94, 0, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) MUX_PG(ld1, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 1, 0x94, 2, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) MUX_PG(ld2, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 2, 0x94, 4, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) MUX_PG(ld3, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 3, 0x94, 6, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) MUX_PG(ld4, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 4, 0x94, 8, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) MUX_PG(ld5, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 5, 0x94, 10, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) MUX_PG(ld6, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 6, 0x94, 12, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) MUX_PG(ld7, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 7, 0x94, 14, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) MUX_PG(ld8, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 8, 0x94, 16, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) MUX_PG(ld9, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 9, 0x94, 18, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) MUX_PG(ld10, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 10, 0x94, 20, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) MUX_PG(ld11, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 11, 0x94, 22, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) MUX_PG(ld12, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 12, 0x94, 24, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) MUX_PG(ld13, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 13, 0x94, 26, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) MUX_PG(ld14, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 14, 0x94, 28, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) MUX_PG(ld15, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 15, 0x94, 30, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) MUX_PG(ld16, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 16, 0x98, 0, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) MUX_PG(ld17, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 17, 0x98, 2, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) MUX_PG(ldc, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 30, 0x90, 14, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) MUX_PG(ldi, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 6, 0x98, 16, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) MUX_PG(lhp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 18, 0x98, 10, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) MUX_PG(lhp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 19, 0x98, 4, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) MUX_PG(lhp2, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 20, 0x98, 6, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) MUX_PG(lhs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x20, 7, 0x90, 22, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) MUX_PG(lm0, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x1c, 24, 0x90, 26, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) MUX_PG(lm1, DISPLAYA, DISPLAYB, RSVD3, CRT, 0x1c, 25, 0x90, 28, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) MUX_PG(lpp, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 8, 0x98, 14, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) MUX_PG(lpw0, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 3, 0x90, 0, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) MUX_PG(lpw1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x20, 4, 0x90, 2, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) MUX_PG(lpw2, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 5, 0x90, 4, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) MUX_PG(lsc0, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 27, 0x90, 18, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) MUX_PG(lsc1, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 28, 0x90, 20, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) MUX_PG(lsck, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x1c, 29, 0x90, 16, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) MUX_PG(lsda, DISPLAYA, DISPLAYB, SPI3, HDMI, 0x20, 1, 0x90, 8, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) MUX_PG(lsdi, DISPLAYA, DISPLAYB, SPI3, RSVD4, 0x20, 2, 0x90, 6, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) MUX_PG(lspi, DISPLAYA, DISPLAYB, XIO, HDMI, 0x20, 0, 0x90, 10, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) MUX_PG(lvp0, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 21, 0x90, 30, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) MUX_PG(lvp1, DISPLAYA, DISPLAYB, RSVD3, RSVD4, 0x1c, 22, 0x98, 8, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) MUX_PG(lvs, DISPLAYA, DISPLAYB, XIO, RSVD4, 0x1c, 26, 0x90, 24, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) MUX_PG(owc, OWR, RSVD2, RSVD3, RSVD4, 0x14, 31, 0x84, 8, 0xb0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) MUX_PG(pmc, PWR_ON, PWR_INTR, RSVD3, RSVD4, 0x14, 23, 0x98, 18, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) MUX_PG(pta, I2C2, HDMI, GMI, RSVD4, 0x14, 24, 0x98, 22, 0xa4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) MUX_PG(rm, I2C1, RSVD2, RSVD3, RSVD4, 0x14, 25, 0x80, 14, 0xa4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) MUX_PG(sdb, UARTA, PWM, SDIO3, SPI2, 0x20, 15, 0x8c, 10, -1, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) MUX_PG(sdc, PWM, TWC, SDIO3, SPI3, 0x18, 1, 0x8c, 12, 0xac, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) MUX_PG(sdd, UARTA, PWM, SDIO3, SPI3, 0x18, 2, 0x8c, 14, 0xac, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) MUX_PG(sdio1, SDIO1, RSVD2, UARTE, UARTA, 0x14, 30, 0x80, 30, 0xb0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) MUX_PG(slxa, PCIE, SPI4, SDIO3, SPI2, 0x18, 3, 0x84, 6, 0xa4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) MUX_PG(slxc, SPDIF, SPI4, SDIO3, SPI2, 0x18, 5, 0x84, 10, 0xa4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) MUX_PG(slxd, SPDIF, SPI4, SDIO3, SPI2, 0x18, 6, 0x84, 12, 0xa4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) MUX_PG(slxk, PCIE, SPI4, SDIO3, SPI2, 0x18, 7, 0x84, 14, 0xa4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) MUX_PG(spdi, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 8, 0x8c, 8, 0xa4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) MUX_PG(spdo, SPDIF, RSVD2, I2C1, SDIO2, 0x18, 9, 0x8c, 6, 0xa4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) MUX_PG(spia, SPI1, SPI2, SPI3, GMI, 0x18, 10, 0x8c, 30, 0xa8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) MUX_PG(spib, SPI1, SPI2, SPI3, GMI, 0x18, 11, 0x8c, 28, 0xa8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) MUX_PG(spic, SPI1, SPI2, SPI3, GMI, 0x18, 12, 0x8c, 26, 0xa8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) MUX_PG(spid, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 13, 0x8c, 24, 0xa8, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) MUX_PG(spie, SPI2, SPI1, SPI2_ALT, GMI, 0x18, 14, 0x8c, 22, 0xa8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) MUX_PG(spif, SPI3, SPI1, SPI2, RSVD4, 0x18, 15, 0x8c, 20, 0xa8, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) MUX_PG(spig, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 16, 0x8c, 18, 0xa8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) MUX_PG(spih, SPI3, SPI2, SPI2_ALT, I2C1, 0x18, 17, 0x8c, 16, 0xa8, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) MUX_PG(uaa, SPI3, MIPI_HS, UARTA, ULPI, 0x18, 18, 0x80, 0, 0xac, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) MUX_PG(uab, SPI2, MIPI_HS, UARTA, ULPI, 0x18, 19, 0x80, 2, 0xac, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) MUX_PG(uac, OWR, RSVD2, RSVD3, RSVD4, 0x18, 20, 0x80, 4, 0xac, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) MUX_PG(uad, IRDA, SPDIF, UARTA, SPI4, 0x18, 21, 0x80, 6, 0xac, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) MUX_PG(uca, UARTC, RSVD2, GMI, RSVD4, 0x18, 22, 0x84, 16, 0xac, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) MUX_PG(ucb, UARTC, PWM, GMI, RSVD4, 0x18, 23, 0x84, 18, 0xac, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) MUX_PG(uda, SPI1, RSVD2, UARTD, ULPI, 0x20, 13, 0x80, 8, 0xb0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* pg_name, pupd_r/b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) PULL_PG(ck32, 0xb0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) PULL_PG(ddrc, 0xac, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) PULL_PG(pmca, 0xb0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) PULL_PG(pmcb, 0xb0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) PULL_PG(pmcc, 0xb0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) PULL_PG(pmcd, 0xb0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) PULL_PG(pmce, 0xb0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) PULL_PG(xm2c, 0xa8, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) PULL_PG(xm2d, 0xa8, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) PULL_PG(ls, 0xac, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) PULL_PG(lc, 0xac, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) PULL_PG(ld17_0, 0xac, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) PULL_PG(ld19_18, 0xac, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) PULL_PG(ld21_20, 0xac, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) PULL_PG(ld23_22, 0xac, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /* pg_name, r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) DRV_PG(ao1, 0x868),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) DRV_PG(ao2, 0x86c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) DRV_PG(at1, 0x870),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) DRV_PG(at2, 0x874),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) DRV_PG(cdev1, 0x878),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) DRV_PG(cdev2, 0x87c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) DRV_PG(csus, 0x880),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) DRV_PG(dap1, 0x884),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) DRV_PG(dap2, 0x888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) DRV_PG(dap3, 0x88c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) DRV_PG(dap4, 0x890),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) DRV_PG(dbg, 0x894),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) DRV_PG(lcd1, 0x898),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) DRV_PG(lcd2, 0x89c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) DRV_PG(sdmmc2, 0x8a0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) DRV_PG(sdmmc3, 0x8a4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) DRV_PG(spi, 0x8a8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) DRV_PG(uaa, 0x8ac),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) DRV_PG(uab, 0x8b0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) DRV_PG(uart2, 0x8b4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) DRV_PG(uart3, 0x8b8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) DRV_PG(vi1, 0x8bc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) DRV_PG(vi2, 0x8c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) DRV_PG_EXT(xm2a, 0x8c4, -1, -1, 4, 14, 19, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) DRV_PG_EXT(xm2c, 0x8c8, -1, 3, -1, 14, 19, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) DRV_PG_EXT(xm2d, 0x8cc, -1, 3, -1, 14, 19, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) DRV_PG_EXT(xm2clk, 0x8d0, -1, -1, -1, 14, 19, 24, 4, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /* pg_name, r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) DRV_PG(sdio1, 0x8e0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) DRV_PG(crt, 0x8ec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) DRV_PG(ddc, 0x8f0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) DRV_PG(gma, 0x8f4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) DRV_PG(gmb, 0x8f8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) DRV_PG(gmc, 0x8fc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) DRV_PG(gmd, 0x900),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) DRV_PG(gme, 0x904),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) DRV_PG(owr, 0x908),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) DRV_PG(uda, 0x90c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .ngpios = NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .gpio_compatible = "nvidia,tegra20-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .pins = tegra20_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .npins = ARRAY_SIZE(tegra20_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .functions = tegra20_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .nfunctions = ARRAY_SIZE(tegra20_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .groups = tegra20_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .ngroups = ARRAY_SIZE(tegra20_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .hsm_in_mux = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .schmitt_in_mux = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .drvtype_in_mux = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) static const char *cdev1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) "dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static const char *cdev2_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) "dev2_osc_div", "hclk", "pclk", "pll_p_out4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) struct tegra_pmx *pmx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) static int tegra20_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) tegra20_pinctrl_register_clock_muxes(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static const struct of_device_id tegra20_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) { .compatible = "nvidia,tegra20-pinmux", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) static struct platform_driver tegra20_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .name = "tegra20-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .of_match_table = tegra20_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .probe = tegra20_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) static int __init tegra20_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) return platform_driver_register(&tegra20_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) arch_initcall(tegra20_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags