^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pinctrl data for the NVIDIA Tegra194 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * under the terms and conditions of the GNU General Public License,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * version 2, as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed in the hope it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pinctrl-tegra.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Define unique ID for each pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum pin_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) TEGRA_PIN_PEX_L5_RST_N_PGG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Table for pin descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct pinctrl_pin_desc tegra194_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PGG1, "PEX_L5_RST_N_PGG1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const unsigned int pex_l5_clkreq_n_pgg0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const unsigned int pex_l5_rst_n_pgg1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) TEGRA_PIN_PEX_L5_RST_N_PGG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Define unique ID for each function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum tegra_mux_dt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) TEGRA_MUX_RSVD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) TEGRA_MUX_RSVD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) TEGRA_MUX_RSVD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) TEGRA_MUX_RSVD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) TEGRA_MUX_PE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Make list of each function name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA_PIN_FUNCTION(lid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .name = #lid, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct tegra_function tegra194_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) TEGRA_PIN_FUNCTION(rsvd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) TEGRA_PIN_FUNCTION(rsvd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) TEGRA_PIN_FUNCTION(rsvd2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) TEGRA_PIN_FUNCTION(rsvd3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) TEGRA_PIN_FUNCTION(pe5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) drvup_w, slwr_b, slwr_w, slwf_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) slwf_w, bank) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .drv_reg = ((r)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .drv_bank = bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .drvdn_bit = drvdn_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .drvdn_width = drvdn_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .drvup_bit = drvup_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .drvup_width = drvup_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .slwr_bit = slwr_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .slwr_width = slwr_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .slwf_bit = slwf_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .slwf_width = slwf_w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, e_input, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) e_od, schmitt_b, drvtype) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .mux_reg = ((r)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .lpmd_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .lock_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .hsm_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .mux_bank = bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .mux_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .pupd_reg = ((r)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .pupd_bank = bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .pupd_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .tri_reg = ((r)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .tri_bank = bank, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .tri_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .einput_bit = e_input, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .odrain_bit = e_od, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .sfsel_bit = 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .schmitt_bit = schmitt_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .drvtype_bit = 13, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .parked_bitmask = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define drive_pex_l5_clkreq_n_pgg0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DRV_PINGROUP_ENTRY_Y(0x14004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define drive_pex_l5_rst_n_pgg1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DRV_PINGROUP_ENTRY_Y(0x1400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_lpbk, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) e_input, e_lpdr, e_od, schmitt_b, drvtype, io_rail) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .funcs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) TEGRA_MUX_##f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) TEGRA_MUX_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) TEGRA_MUX_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) TEGRA_MUX_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_lpbk, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) e_input, e_od, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) schmitt_b, drvtype), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) drive_##pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct tegra_pingroup tegra194_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINGROUP(pex_l5_clkreq_n_pgg0, PE5, RSVD1, RSVD2, RSVD3, 0x14000, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINGROUP(pex_l5_rst_n_pgg1, PE5, RSVD1, RSVD2, RSVD3, 0x14008, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) Y, -1, 6, 8, 11, 12, N, "vddio_pex_ctl_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .pins = tegra194_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .npins = ARRAY_SIZE(tegra194_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .functions = tegra194_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .nfunctions = ARRAY_SIZE(tegra194_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .groups = tegra194_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .ngroups = ARRAY_SIZE(tegra194_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .hsm_in_mux = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .schmitt_in_mux = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .drvtype_in_mux = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .sfsel_in_mux = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int tegra194_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return tegra_pinctrl_probe(pdev, &tegra194_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct of_device_id tegra194_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .compatible = "nvidia,tegra194-pinmux", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct platform_driver tegra194_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "tegra194-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .of_match_table = tegra194_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .probe = tegra194_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int __init tegra194_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return platform_driver_register(&tegra194_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) arch_initcall(tegra194_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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