^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pinctrl data for the NVIDIA Tegra124 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Ashwini Ghuge <aghuge@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-tegra.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Most pins affected by the pinmux can also be GPIOs. Define these first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * These must match how the GPIO driver names/numbers its pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define _GPIO(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA_PIN_PB0 _GPIO(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA_PIN_PB1 _GPIO(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA_PIN_PC7 _GPIO(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA_PIN_PG0 _GPIO(48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA_PIN_PG1 _GPIO(49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA_PIN_PG2 _GPIO(50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA_PIN_PG3 _GPIO(51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA_PIN_PG4 _GPIO(52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA_PIN_PG5 _GPIO(53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA_PIN_PG6 _GPIO(54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA_PIN_PG7 _GPIO(55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA_PIN_PH0 _GPIO(56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA_PIN_PH1 _GPIO(57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA_PIN_PH2 _GPIO(58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA_PIN_PH3 _GPIO(59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA_PIN_PH4 _GPIO(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA_PIN_PH5 _GPIO(61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA_PIN_PH6 _GPIO(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA_PIN_PH7 _GPIO(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA_PIN_PI0 _GPIO(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA_PIN_PI1 _GPIO(65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA_PIN_PI2 _GPIO(66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA_PIN_PI3 _GPIO(67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA_PIN_PI4 _GPIO(68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA_PIN_PI5 _GPIO(69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA_PIN_PI6 _GPIO(70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA_PIN_PI7 _GPIO(71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA_PIN_PJ0 _GPIO(72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA_PIN_PJ2 _GPIO(74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA_PIN_PJ7 _GPIO(79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA_PIN_PK0 _GPIO(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA_PIN_PK1 _GPIO(81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA_PIN_PK2 _GPIO(82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA_PIN_PK3 _GPIO(83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA_PIN_PK4 _GPIO(84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA_PIN_PK7 _GPIO(87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA_PIN_KB_ROW16_PT0 _GPIO(152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA_PIN_KB_ROW17_PT1 _GPIO(153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA_PIN_PU0 _GPIO(160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA_PIN_PU1 _GPIO(161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA_PIN_PU2 _GPIO(162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA_PIN_PU3 _GPIO(163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA_PIN_PU4 _GPIO(164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA_PIN_PU5 _GPIO(165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA_PIN_PU6 _GPIO(166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA_PIN_PV0 _GPIO(168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA_PIN_PV1 _GPIO(169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEGRA_PIN_PBB0 _GPIO(216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TEGRA_PIN_PBB3 _GPIO(219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TEGRA_PIN_PBB4 _GPIO(220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TEGRA_PIN_PBB5 _GPIO(221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA_PIN_PBB6 _GPIO(222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA_PIN_PBB7 _GPIO(223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TEGRA_PIN_PCC1 _GPIO(225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TEGRA_PIN_PCC2 _GPIO(226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA_PIN_DAP_MCLK1_REQ_PEE2 _GPIO(242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA_PIN_DP_HPD_PFF0 _GPIO(248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TEGRA_PIN_USB_VBUS_EN2_PFF1 _GPIO(249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TEGRA_PIN_PFF2 _GPIO(250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* All non-GPIO pins follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define _PIN(offset) (NUM_GPIOS + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Non-GPIO pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TEGRA_PIN_PWR_INT_N _PIN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TEGRA_PIN_GMI_CLK_LB _PIN(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TEGRA_PIN_RESET_OUT_N _PIN(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TEGRA_PIN_OWR _PIN(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TEGRA_PIN_CLK_32K_IN _PIN(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TEGRA_PIN_JTAG_RTCK _PIN(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TEGRA_PIN_DSI_B_CLK_P _PIN(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA_PIN_DSI_B_CLK_N _PIN(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TEGRA_PIN_DSI_B_D0_P _PIN(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA_PIN_DSI_B_D0_N _PIN(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TEGRA_PIN_DSI_B_D1_P _PIN(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA_PIN_DSI_B_D1_N _PIN(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TEGRA_PIN_DSI_B_D2_P _PIN(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TEGRA_PIN_DSI_B_D2_N _PIN(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TEGRA_PIN_DSI_B_D3_P _PIN(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA_PIN_DSI_B_D3_N _PIN(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct pinctrl_pin_desc tegra124_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const unsigned clk_32k_out_pa0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) TEGRA_PIN_CLK_32K_OUT_PA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const unsigned uart3_cts_n_pa1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) TEGRA_PIN_UART3_CTS_N_PA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const unsigned dap2_fs_pa2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) TEGRA_PIN_DAP2_FS_PA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const unsigned dap2_sclk_pa3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) TEGRA_PIN_DAP2_SCLK_PA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const unsigned dap2_din_pa4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) TEGRA_PIN_DAP2_DIN_PA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const unsigned dap2_dout_pa5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) TEGRA_PIN_DAP2_DOUT_PA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const unsigned sdmmc3_clk_pa6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) TEGRA_PIN_SDMMC3_CLK_PA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const unsigned sdmmc3_cmd_pa7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) TEGRA_PIN_SDMMC3_CMD_PA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const unsigned pb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) TEGRA_PIN_PB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const unsigned pb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) TEGRA_PIN_PB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const unsigned sdmmc3_dat3_pb4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) TEGRA_PIN_SDMMC3_DAT3_PB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const unsigned sdmmc3_dat2_pb5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) TEGRA_PIN_SDMMC3_DAT2_PB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const unsigned sdmmc3_dat1_pb6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) TEGRA_PIN_SDMMC3_DAT1_PB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const unsigned sdmmc3_dat0_pb7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) TEGRA_PIN_SDMMC3_DAT0_PB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const unsigned uart3_rts_n_pc0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) TEGRA_PIN_UART3_RTS_N_PC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const unsigned uart2_txd_pc2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) TEGRA_PIN_UART2_TXD_PC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const unsigned uart2_rxd_pc3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) TEGRA_PIN_UART2_RXD_PC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const unsigned gen1_i2c_scl_pc4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) TEGRA_PIN_GEN1_I2C_SCL_PC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const unsigned gen1_i2c_sda_pc5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) TEGRA_PIN_GEN1_I2C_SDA_PC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const unsigned pc7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) TEGRA_PIN_PC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const unsigned pg0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) TEGRA_PIN_PG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const unsigned pg1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) TEGRA_PIN_PG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const unsigned pg2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) TEGRA_PIN_PG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const unsigned pg3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) TEGRA_PIN_PG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const unsigned pg4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) TEGRA_PIN_PG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const unsigned pg5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) TEGRA_PIN_PG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const unsigned pg6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) TEGRA_PIN_PG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const unsigned pg7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) TEGRA_PIN_PG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const unsigned ph0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) TEGRA_PIN_PH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const unsigned ph1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) TEGRA_PIN_PH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const unsigned ph2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) TEGRA_PIN_PH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const unsigned ph3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) TEGRA_PIN_PH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const unsigned ph4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) TEGRA_PIN_PH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const unsigned ph5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) TEGRA_PIN_PH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const unsigned ph6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) TEGRA_PIN_PH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const unsigned ph7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) TEGRA_PIN_PH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const unsigned pi0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) TEGRA_PIN_PI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const unsigned pi1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) TEGRA_PIN_PI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const unsigned pi2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) TEGRA_PIN_PI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const unsigned pi3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) TEGRA_PIN_PI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const unsigned pi4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) TEGRA_PIN_PI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const unsigned pi5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) TEGRA_PIN_PI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const unsigned pi6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) TEGRA_PIN_PI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const unsigned pi7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) TEGRA_PIN_PI7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const unsigned pj0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) TEGRA_PIN_PJ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const unsigned pj2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) TEGRA_PIN_PJ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const unsigned uart2_cts_n_pj5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) TEGRA_PIN_UART2_CTS_N_PJ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const unsigned uart2_rts_n_pj6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) TEGRA_PIN_UART2_RTS_N_PJ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const unsigned pj7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) TEGRA_PIN_PJ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const unsigned pk0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) TEGRA_PIN_PK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const unsigned pk1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) TEGRA_PIN_PK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const unsigned pk2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) TEGRA_PIN_PK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const unsigned pk3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) TEGRA_PIN_PK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const unsigned pk4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) TEGRA_PIN_PK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const unsigned spdif_out_pk5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) TEGRA_PIN_SPDIF_OUT_PK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const unsigned spdif_in_pk6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) TEGRA_PIN_SPDIF_IN_PK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const unsigned pk7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) TEGRA_PIN_PK7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const unsigned dap1_fs_pn0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) TEGRA_PIN_DAP1_FS_PN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const unsigned dap1_din_pn1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) TEGRA_PIN_DAP1_DIN_PN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const unsigned dap1_dout_pn2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) TEGRA_PIN_DAP1_DOUT_PN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const unsigned dap1_sclk_pn3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) TEGRA_PIN_DAP1_SCLK_PN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const unsigned usb_vbus_en0_pn4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) TEGRA_PIN_USB_VBUS_EN0_PN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const unsigned usb_vbus_en1_pn5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) TEGRA_PIN_USB_VBUS_EN1_PN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const unsigned hdmi_int_pn7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) TEGRA_PIN_HDMI_INT_PN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const unsigned ulpi_data7_po0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) TEGRA_PIN_ULPI_DATA7_PO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const unsigned ulpi_data0_po1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) TEGRA_PIN_ULPI_DATA0_PO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const unsigned ulpi_data1_po2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) TEGRA_PIN_ULPI_DATA1_PO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const unsigned ulpi_data2_po3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) TEGRA_PIN_ULPI_DATA2_PO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const unsigned ulpi_data3_po4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) TEGRA_PIN_ULPI_DATA3_PO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const unsigned ulpi_data4_po5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) TEGRA_PIN_ULPI_DATA4_PO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static const unsigned ulpi_data5_po6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) TEGRA_PIN_ULPI_DATA5_PO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const unsigned ulpi_data6_po7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) TEGRA_PIN_ULPI_DATA6_PO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const unsigned dap3_fs_pp0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) TEGRA_PIN_DAP3_FS_PP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const unsigned dap3_din_pp1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) TEGRA_PIN_DAP3_DIN_PP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const unsigned dap3_dout_pp2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) TEGRA_PIN_DAP3_DOUT_PP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const unsigned dap3_sclk_pp3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) TEGRA_PIN_DAP3_SCLK_PP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const unsigned dap4_fs_pp4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) TEGRA_PIN_DAP4_FS_PP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const unsigned dap4_din_pp5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) TEGRA_PIN_DAP4_DIN_PP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const unsigned dap4_dout_pp6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) TEGRA_PIN_DAP4_DOUT_PP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const unsigned dap4_sclk_pp7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) TEGRA_PIN_DAP4_SCLK_PP7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const unsigned kb_col0_pq0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) TEGRA_PIN_KB_COL0_PQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const unsigned kb_col1_pq1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) TEGRA_PIN_KB_COL1_PQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const unsigned kb_col2_pq2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) TEGRA_PIN_KB_COL2_PQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const unsigned kb_col3_pq3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) TEGRA_PIN_KB_COL3_PQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const unsigned kb_col4_pq4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) TEGRA_PIN_KB_COL4_PQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const unsigned kb_col5_pq5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) TEGRA_PIN_KB_COL5_PQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const unsigned kb_col6_pq6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) TEGRA_PIN_KB_COL6_PQ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const unsigned kb_col7_pq7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) TEGRA_PIN_KB_COL7_PQ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const unsigned kb_row0_pr0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) TEGRA_PIN_KB_ROW0_PR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const unsigned kb_row1_pr1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TEGRA_PIN_KB_ROW1_PR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const unsigned kb_row2_pr2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) TEGRA_PIN_KB_ROW2_PR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const unsigned kb_row3_pr3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) TEGRA_PIN_KB_ROW3_PR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const unsigned kb_row4_pr4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TEGRA_PIN_KB_ROW4_PR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static const unsigned kb_row5_pr5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) TEGRA_PIN_KB_ROW5_PR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const unsigned kb_row6_pr6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) TEGRA_PIN_KB_ROW6_PR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const unsigned kb_row7_pr7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) TEGRA_PIN_KB_ROW7_PR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const unsigned kb_row8_ps0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) TEGRA_PIN_KB_ROW8_PS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const unsigned kb_row9_ps1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) TEGRA_PIN_KB_ROW9_PS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const unsigned kb_row10_ps2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) TEGRA_PIN_KB_ROW10_PS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const unsigned kb_row11_ps3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) TEGRA_PIN_KB_ROW11_PS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const unsigned kb_row12_ps4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) TEGRA_PIN_KB_ROW12_PS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static const unsigned kb_row13_ps5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) TEGRA_PIN_KB_ROW13_PS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const unsigned kb_row14_ps6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TEGRA_PIN_KB_ROW14_PS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const unsigned kb_row15_ps7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TEGRA_PIN_KB_ROW15_PS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const unsigned kb_row16_pt0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) TEGRA_PIN_KB_ROW16_PT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const unsigned kb_row17_pt1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) TEGRA_PIN_KB_ROW17_PT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const unsigned gen2_i2c_scl_pt5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) TEGRA_PIN_GEN2_I2C_SCL_PT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const unsigned gen2_i2c_sda_pt6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) TEGRA_PIN_GEN2_I2C_SDA_PT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const unsigned sdmmc4_cmd_pt7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) TEGRA_PIN_SDMMC4_CMD_PT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const unsigned pu0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) TEGRA_PIN_PU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const unsigned pu1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) TEGRA_PIN_PU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static const unsigned pu2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) TEGRA_PIN_PU2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const unsigned pu3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) TEGRA_PIN_PU3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static const unsigned pu4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) TEGRA_PIN_PU4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const unsigned pu5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) TEGRA_PIN_PU5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const unsigned pu6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) TEGRA_PIN_PU6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const unsigned pv0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) TEGRA_PIN_PV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static const unsigned pv1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) TEGRA_PIN_PV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static const unsigned sdmmc3_cd_n_pv2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) TEGRA_PIN_SDMMC3_CD_N_PV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const unsigned sdmmc1_wp_n_pv3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) TEGRA_PIN_SDMMC1_WP_N_PV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const unsigned ddc_scl_pv4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) TEGRA_PIN_DDC_SCL_PV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static const unsigned ddc_sda_pv5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) TEGRA_PIN_DDC_SDA_PV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const unsigned gpio_w2_aud_pw2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) TEGRA_PIN_GPIO_W2_AUD_PW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static const unsigned gpio_w3_aud_pw3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) TEGRA_PIN_GPIO_W3_AUD_PW3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const unsigned dap_mclk1_pw4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) TEGRA_PIN_DAP_MCLK1_PW4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static const unsigned clk2_out_pw5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) TEGRA_PIN_CLK2_OUT_PW5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const unsigned uart3_txd_pw6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) TEGRA_PIN_UART3_TXD_PW6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const unsigned uart3_rxd_pw7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) TEGRA_PIN_UART3_RXD_PW7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const unsigned dvfs_pwm_px0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) TEGRA_PIN_DVFS_PWM_PX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static const unsigned gpio_x1_aud_px1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) TEGRA_PIN_GPIO_X1_AUD_PX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const unsigned dvfs_clk_px2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) TEGRA_PIN_DVFS_CLK_PX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const unsigned gpio_x3_aud_px3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) TEGRA_PIN_GPIO_X3_AUD_PX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const unsigned gpio_x4_aud_px4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) TEGRA_PIN_GPIO_X4_AUD_PX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const unsigned gpio_x5_aud_px5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) TEGRA_PIN_GPIO_X5_AUD_PX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const unsigned gpio_x6_aud_px6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) TEGRA_PIN_GPIO_X6_AUD_PX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const unsigned gpio_x7_aud_px7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) TEGRA_PIN_GPIO_X7_AUD_PX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const unsigned ulpi_clk_py0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) TEGRA_PIN_ULPI_CLK_PY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static const unsigned ulpi_dir_py1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) TEGRA_PIN_ULPI_DIR_PY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static const unsigned ulpi_nxt_py2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) TEGRA_PIN_ULPI_NXT_PY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const unsigned ulpi_stp_py3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) TEGRA_PIN_ULPI_STP_PY3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const unsigned sdmmc1_dat3_py4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) TEGRA_PIN_SDMMC1_DAT3_PY4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static const unsigned sdmmc1_dat2_py5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) TEGRA_PIN_SDMMC1_DAT2_PY5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const unsigned sdmmc1_dat1_py6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) TEGRA_PIN_SDMMC1_DAT1_PY6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const unsigned sdmmc1_dat0_py7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) TEGRA_PIN_SDMMC1_DAT0_PY7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static const unsigned sdmmc1_clk_pz0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) TEGRA_PIN_SDMMC1_CLK_PZ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const unsigned sdmmc1_cmd_pz1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) TEGRA_PIN_SDMMC1_CMD_PZ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static const unsigned pwr_i2c_scl_pz6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) TEGRA_PIN_PWR_I2C_SCL_PZ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static const unsigned pwr_i2c_sda_pz7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) TEGRA_PIN_PWR_I2C_SDA_PZ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static const unsigned sdmmc4_dat0_paa0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) TEGRA_PIN_SDMMC4_DAT0_PAA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static const unsigned sdmmc4_dat1_paa1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) TEGRA_PIN_SDMMC4_DAT1_PAA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const unsigned sdmmc4_dat2_paa2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) TEGRA_PIN_SDMMC4_DAT2_PAA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const unsigned sdmmc4_dat3_paa3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) TEGRA_PIN_SDMMC4_DAT3_PAA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const unsigned sdmmc4_dat4_paa4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) TEGRA_PIN_SDMMC4_DAT4_PAA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const unsigned sdmmc4_dat5_paa5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) TEGRA_PIN_SDMMC4_DAT5_PAA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static const unsigned sdmmc4_dat6_paa6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) TEGRA_PIN_SDMMC4_DAT6_PAA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const unsigned sdmmc4_dat7_paa7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) TEGRA_PIN_SDMMC4_DAT7_PAA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static const unsigned pbb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) TEGRA_PIN_PBB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const unsigned cam_i2c_scl_pbb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) TEGRA_PIN_CAM_I2C_SCL_PBB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static const unsigned cam_i2c_sda_pbb2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) TEGRA_PIN_CAM_I2C_SDA_PBB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static const unsigned pbb3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) TEGRA_PIN_PBB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static const unsigned pbb4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) TEGRA_PIN_PBB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static const unsigned pbb5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) TEGRA_PIN_PBB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static const unsigned pbb6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) TEGRA_PIN_PBB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static const unsigned pbb7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) TEGRA_PIN_PBB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static const unsigned cam_mclk_pcc0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) TEGRA_PIN_CAM_MCLK_PCC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static const unsigned pcc1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) TEGRA_PIN_PCC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static const unsigned pcc2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) TEGRA_PIN_PCC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static const unsigned sdmmc4_clk_pcc4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) TEGRA_PIN_SDMMC4_CLK_PCC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const unsigned clk2_req_pcc5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) TEGRA_PIN_CLK2_REQ_PCC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static const unsigned pex_l0_rst_n_pdd1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) TEGRA_PIN_PEX_L0_RST_N_PDD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static const unsigned pex_wake_n_pdd3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) TEGRA_PIN_PEX_WAKE_N_PDD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static const unsigned pex_l1_rst_n_pdd5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) TEGRA_PIN_PEX_L1_RST_N_PDD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static const unsigned clk3_out_pee0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) TEGRA_PIN_CLK3_OUT_PEE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const unsigned clk3_req_pee1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) TEGRA_PIN_CLK3_REQ_PEE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static const unsigned dap_mclk1_req_pee2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static const unsigned hdmi_cec_pee3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) TEGRA_PIN_HDMI_CEC_PEE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static const unsigned dp_hpd_pff0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) TEGRA_PIN_DP_HPD_PFF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static const unsigned usb_vbus_en2_pff1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) TEGRA_PIN_USB_VBUS_EN2_PFF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static const unsigned pff2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) TEGRA_PIN_PFF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static const unsigned core_pwr_req_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) TEGRA_PIN_CORE_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static const unsigned cpu_pwr_req_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) TEGRA_PIN_CPU_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static const unsigned pwr_int_n_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) TEGRA_PIN_PWR_INT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static const unsigned gmi_clk_lb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) TEGRA_PIN_GMI_CLK_LB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static const unsigned reset_out_n_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) TEGRA_PIN_RESET_OUT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static const unsigned owr_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) TEGRA_PIN_OWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static const unsigned clk_32k_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) TEGRA_PIN_CLK_32K_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static const unsigned jtag_rtck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) TEGRA_PIN_JTAG_RTCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const unsigned drive_ao1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) TEGRA_PIN_KB_ROW0_PR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) TEGRA_PIN_KB_ROW1_PR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) TEGRA_PIN_KB_ROW2_PR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) TEGRA_PIN_KB_ROW3_PR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) TEGRA_PIN_KB_ROW4_PR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) TEGRA_PIN_KB_ROW5_PR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) TEGRA_PIN_KB_ROW6_PR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) TEGRA_PIN_KB_ROW7_PR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) TEGRA_PIN_PWR_I2C_SCL_PZ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) TEGRA_PIN_PWR_I2C_SDA_PZ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static const unsigned drive_ao2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) TEGRA_PIN_CLK_32K_OUT_PA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) TEGRA_PIN_CLK_32K_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) TEGRA_PIN_KB_COL0_PQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) TEGRA_PIN_KB_COL1_PQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) TEGRA_PIN_KB_COL2_PQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) TEGRA_PIN_KB_COL3_PQ3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) TEGRA_PIN_KB_COL4_PQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) TEGRA_PIN_KB_COL5_PQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) TEGRA_PIN_KB_COL6_PQ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) TEGRA_PIN_KB_COL7_PQ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) TEGRA_PIN_KB_ROW8_PS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) TEGRA_PIN_KB_ROW9_PS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) TEGRA_PIN_KB_ROW10_PS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) TEGRA_PIN_KB_ROW11_PS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) TEGRA_PIN_KB_ROW12_PS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) TEGRA_PIN_KB_ROW13_PS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) TEGRA_PIN_KB_ROW14_PS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) TEGRA_PIN_KB_ROW15_PS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) TEGRA_PIN_KB_ROW16_PT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) TEGRA_PIN_KB_ROW17_PT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) TEGRA_PIN_SDMMC3_CD_N_PV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) TEGRA_PIN_CORE_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) TEGRA_PIN_CPU_PWR_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) TEGRA_PIN_PWR_INT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static const unsigned drive_at1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) TEGRA_PIN_PH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) TEGRA_PIN_PH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) TEGRA_PIN_PH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) TEGRA_PIN_PH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static const unsigned drive_at2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) TEGRA_PIN_PG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) TEGRA_PIN_PG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) TEGRA_PIN_PG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) TEGRA_PIN_PG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) TEGRA_PIN_PG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) TEGRA_PIN_PG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) TEGRA_PIN_PG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) TEGRA_PIN_PG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) TEGRA_PIN_PI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) TEGRA_PIN_PI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) TEGRA_PIN_PI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) TEGRA_PIN_PI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) TEGRA_PIN_PI7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) TEGRA_PIN_PK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) TEGRA_PIN_PK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static const unsigned drive_at3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) TEGRA_PIN_PC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) TEGRA_PIN_PJ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const unsigned drive_at4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) TEGRA_PIN_PB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) TEGRA_PIN_PB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) TEGRA_PIN_PJ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) TEGRA_PIN_PJ7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) TEGRA_PIN_PK7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static const unsigned drive_at5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) TEGRA_PIN_GEN2_I2C_SCL_PT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) TEGRA_PIN_GEN2_I2C_SDA_PT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static const unsigned drive_cdev1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) TEGRA_PIN_DAP_MCLK1_PW4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static const unsigned drive_cdev2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) TEGRA_PIN_CLK2_OUT_PW5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) TEGRA_PIN_CLK2_REQ_PCC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static const unsigned drive_dap1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) TEGRA_PIN_DAP1_FS_PN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) TEGRA_PIN_DAP1_DIN_PN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) TEGRA_PIN_DAP1_DOUT_PN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) TEGRA_PIN_DAP1_SCLK_PN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static const unsigned drive_dap2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) TEGRA_PIN_DAP2_FS_PA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) TEGRA_PIN_DAP2_SCLK_PA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) TEGRA_PIN_DAP2_DIN_PA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) TEGRA_PIN_DAP2_DOUT_PA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const unsigned drive_dap3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) TEGRA_PIN_DAP3_FS_PP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) TEGRA_PIN_DAP3_DIN_PP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) TEGRA_PIN_DAP3_DOUT_PP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) TEGRA_PIN_DAP3_SCLK_PP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const unsigned drive_dap4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) TEGRA_PIN_DAP4_FS_PP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) TEGRA_PIN_DAP4_DIN_PP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) TEGRA_PIN_DAP4_DOUT_PP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) TEGRA_PIN_DAP4_SCLK_PP7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static const unsigned drive_dbg_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) TEGRA_PIN_GEN1_I2C_SCL_PC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) TEGRA_PIN_GEN1_I2C_SDA_PC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) TEGRA_PIN_PU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) TEGRA_PIN_PU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) TEGRA_PIN_PU2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) TEGRA_PIN_PU3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) TEGRA_PIN_PU4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) TEGRA_PIN_PU5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) TEGRA_PIN_PU6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static const unsigned drive_sdio3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) TEGRA_PIN_SDMMC3_CLK_PA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) TEGRA_PIN_SDMMC3_CMD_PA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) TEGRA_PIN_SDMMC3_DAT3_PB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) TEGRA_PIN_SDMMC3_DAT2_PB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) TEGRA_PIN_SDMMC3_DAT1_PB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) TEGRA_PIN_SDMMC3_DAT0_PB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static const unsigned drive_spi_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) TEGRA_PIN_DVFS_PWM_PX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) TEGRA_PIN_GPIO_X1_AUD_PX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) TEGRA_PIN_DVFS_CLK_PX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) TEGRA_PIN_GPIO_X3_AUD_PX3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) TEGRA_PIN_GPIO_X4_AUD_PX4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) TEGRA_PIN_GPIO_X5_AUD_PX5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) TEGRA_PIN_GPIO_X6_AUD_PX6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) TEGRA_PIN_GPIO_X7_AUD_PX7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) TEGRA_PIN_GPIO_W2_AUD_PW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) TEGRA_PIN_GPIO_W3_AUD_PW3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) static const unsigned drive_uaa_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) TEGRA_PIN_ULPI_DATA0_PO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) TEGRA_PIN_ULPI_DATA1_PO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) TEGRA_PIN_ULPI_DATA2_PO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) TEGRA_PIN_ULPI_DATA3_PO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static const unsigned drive_uab_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) TEGRA_PIN_ULPI_DATA7_PO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) TEGRA_PIN_ULPI_DATA4_PO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) TEGRA_PIN_ULPI_DATA5_PO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) TEGRA_PIN_ULPI_DATA6_PO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) TEGRA_PIN_PV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) TEGRA_PIN_PV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static const unsigned drive_uart2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) TEGRA_PIN_UART2_TXD_PC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) TEGRA_PIN_UART2_RXD_PC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) TEGRA_PIN_UART2_CTS_N_PJ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) TEGRA_PIN_UART2_RTS_N_PJ6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static const unsigned drive_uart3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) TEGRA_PIN_UART3_CTS_N_PA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) TEGRA_PIN_UART3_RTS_N_PC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) TEGRA_PIN_UART3_TXD_PW6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) TEGRA_PIN_UART3_RXD_PW7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static const unsigned drive_sdio1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) TEGRA_PIN_SDMMC1_DAT3_PY4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) TEGRA_PIN_SDMMC1_DAT2_PY5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) TEGRA_PIN_SDMMC1_DAT1_PY6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) TEGRA_PIN_SDMMC1_DAT0_PY7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) TEGRA_PIN_SDMMC1_CLK_PZ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) TEGRA_PIN_SDMMC1_CMD_PZ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static const unsigned drive_ddc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) TEGRA_PIN_DDC_SCL_PV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) TEGRA_PIN_DDC_SDA_PV5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static const unsigned drive_gma_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) TEGRA_PIN_SDMMC4_CLK_PCC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) TEGRA_PIN_SDMMC4_CMD_PT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) TEGRA_PIN_SDMMC4_DAT0_PAA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) TEGRA_PIN_SDMMC4_DAT1_PAA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) TEGRA_PIN_SDMMC4_DAT2_PAA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) TEGRA_PIN_SDMMC4_DAT3_PAA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) TEGRA_PIN_SDMMC4_DAT4_PAA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) TEGRA_PIN_SDMMC4_DAT5_PAA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) TEGRA_PIN_SDMMC4_DAT6_PAA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) TEGRA_PIN_SDMMC4_DAT7_PAA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static const unsigned drive_gme_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) TEGRA_PIN_PBB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) TEGRA_PIN_CAM_I2C_SCL_PBB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) TEGRA_PIN_CAM_I2C_SDA_PBB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) TEGRA_PIN_PBB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) TEGRA_PIN_PCC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static const unsigned drive_gmf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) TEGRA_PIN_PBB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) TEGRA_PIN_PBB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) TEGRA_PIN_PBB6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) TEGRA_PIN_PBB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static const unsigned drive_gmg_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) TEGRA_PIN_CAM_MCLK_PCC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static const unsigned drive_gmh_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) TEGRA_PIN_PCC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static const unsigned drive_owr_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) TEGRA_PIN_SDMMC3_CD_N_PV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) TEGRA_PIN_OWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static const unsigned drive_uda_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) TEGRA_PIN_ULPI_CLK_PY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) TEGRA_PIN_ULPI_DIR_PY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) TEGRA_PIN_ULPI_NXT_PY2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) TEGRA_PIN_ULPI_STP_PY3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static const unsigned drive_gpv_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) TEGRA_PIN_PEX_L0_RST_N_PDD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) TEGRA_PIN_PEX_WAKE_N_PDD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) TEGRA_PIN_PEX_L1_RST_N_PDD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) TEGRA_PIN_USB_VBUS_EN2_PFF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) TEGRA_PIN_PFF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static const unsigned drive_dev3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) TEGRA_PIN_CLK3_OUT_PEE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) TEGRA_PIN_CLK3_REQ_PEE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static const unsigned drive_cec_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) TEGRA_PIN_HDMI_CEC_PEE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static const unsigned drive_at6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) TEGRA_PIN_PK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) TEGRA_PIN_PK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) TEGRA_PIN_PK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) TEGRA_PIN_PI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) TEGRA_PIN_PI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) TEGRA_PIN_PI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) TEGRA_PIN_PH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) TEGRA_PIN_PH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) TEGRA_PIN_PH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) TEGRA_PIN_PH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static const unsigned drive_dap5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) TEGRA_PIN_SPDIF_IN_PK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) TEGRA_PIN_SPDIF_OUT_PK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) TEGRA_PIN_DP_HPD_PFF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static const unsigned drive_usb_vbus_en_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) TEGRA_PIN_USB_VBUS_EN0_PN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) TEGRA_PIN_USB_VBUS_EN1_PN5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static const unsigned drive_ao3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) TEGRA_PIN_RESET_OUT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static const unsigned drive_ao0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) TEGRA_PIN_JTAG_RTCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static const unsigned drive_hv0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) TEGRA_PIN_HDMI_INT_PN7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static const unsigned drive_sdio4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) TEGRA_PIN_SDMMC1_WP_N_PV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const unsigned drive_ao4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) TEGRA_PIN_JTAG_RTCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) TEGRA_PIN_DSI_B_CLK_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) TEGRA_PIN_DSI_B_CLK_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) TEGRA_PIN_DSI_B_D0_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) TEGRA_PIN_DSI_B_D0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) TEGRA_PIN_DSI_B_D1_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) TEGRA_PIN_DSI_B_D1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) TEGRA_PIN_DSI_B_D2_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) TEGRA_PIN_DSI_B_D2_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) TEGRA_PIN_DSI_B_D3_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) TEGRA_PIN_DSI_B_D3_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) enum tegra_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) TEGRA_MUX_BLINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) TEGRA_MUX_CCLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) TEGRA_MUX_CEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) TEGRA_MUX_CLDVFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) TEGRA_MUX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) TEGRA_MUX_CLK12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) TEGRA_MUX_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) TEGRA_MUX_CSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) TEGRA_MUX_DAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) TEGRA_MUX_DAP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) TEGRA_MUX_DAP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) TEGRA_MUX_DEV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) TEGRA_MUX_DISPLAYA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) TEGRA_MUX_DISPLAYA_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) TEGRA_MUX_DISPLAYB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) TEGRA_MUX_DP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) TEGRA_MUX_DSI_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) TEGRA_MUX_DTV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) TEGRA_MUX_EXTPERIPH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) TEGRA_MUX_EXTPERIPH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) TEGRA_MUX_EXTPERIPH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) TEGRA_MUX_GMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) TEGRA_MUX_GMI_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) TEGRA_MUX_HDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) TEGRA_MUX_HSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) TEGRA_MUX_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) TEGRA_MUX_I2C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) TEGRA_MUX_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) TEGRA_MUX_I2C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) TEGRA_MUX_I2CPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) TEGRA_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) TEGRA_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) TEGRA_MUX_I2S2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) TEGRA_MUX_I2S3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) TEGRA_MUX_I2S4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) TEGRA_MUX_IRDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) TEGRA_MUX_KBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) TEGRA_MUX_OWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) TEGRA_MUX_PE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) TEGRA_MUX_PE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) TEGRA_MUX_PE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) TEGRA_MUX_PMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) TEGRA_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) TEGRA_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) TEGRA_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) TEGRA_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) TEGRA_MUX_PWRON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) TEGRA_MUX_RESET_OUT_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) TEGRA_MUX_RSVD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) TEGRA_MUX_RSVD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) TEGRA_MUX_RSVD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) TEGRA_MUX_RSVD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) TEGRA_MUX_RTCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) TEGRA_MUX_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) TEGRA_MUX_SDMMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) TEGRA_MUX_SDMMC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) TEGRA_MUX_SDMMC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) TEGRA_MUX_SDMMC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) TEGRA_MUX_SOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) TEGRA_MUX_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) TEGRA_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) TEGRA_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) TEGRA_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) TEGRA_MUX_SPI4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) TEGRA_MUX_SPI5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) TEGRA_MUX_SPI6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) TEGRA_MUX_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) TEGRA_MUX_TMDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) TEGRA_MUX_TRACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) TEGRA_MUX_UARTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) TEGRA_MUX_UARTB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) TEGRA_MUX_UARTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) TEGRA_MUX_UARTD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) TEGRA_MUX_ULPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) TEGRA_MUX_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) TEGRA_MUX_VGP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) TEGRA_MUX_VGP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) TEGRA_MUX_VGP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) TEGRA_MUX_VGP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) TEGRA_MUX_VGP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) TEGRA_MUX_VGP6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) TEGRA_MUX_VI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) TEGRA_MUX_VI_ALT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) TEGRA_MUX_VI_ALT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) TEGRA_MUX_VIMCLK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) TEGRA_MUX_VIMCLK2_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) static struct tegra_function tegra124_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) FUNCTION(blink),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) FUNCTION(ccla),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) FUNCTION(cec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) FUNCTION(cldvfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) FUNCTION(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) FUNCTION(clk12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) FUNCTION(cpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) FUNCTION(csi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) FUNCTION(dap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) FUNCTION(dap1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) FUNCTION(dap2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) FUNCTION(dev3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) FUNCTION(displaya),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) FUNCTION(displaya_alt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) FUNCTION(displayb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) FUNCTION(dp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) FUNCTION(dsi_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) FUNCTION(dtv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) FUNCTION(extperiph1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) FUNCTION(extperiph2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) FUNCTION(extperiph3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) FUNCTION(gmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) FUNCTION(gmi_alt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) FUNCTION(hda),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) FUNCTION(hsi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) FUNCTION(i2cpwr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) FUNCTION(i2s0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) FUNCTION(i2s1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) FUNCTION(i2s2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) FUNCTION(i2s3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) FUNCTION(i2s4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) FUNCTION(irda),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) FUNCTION(kbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) FUNCTION(owr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) FUNCTION(pe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) FUNCTION(pe0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) FUNCTION(pe1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) FUNCTION(pmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) FUNCTION(pwron),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) FUNCTION(reset_out_n),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) FUNCTION(rsvd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) FUNCTION(rsvd2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) FUNCTION(rsvd3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) FUNCTION(rsvd4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) FUNCTION(rtck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) FUNCTION(sata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) FUNCTION(sdmmc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) FUNCTION(sdmmc2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) FUNCTION(sdmmc3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) FUNCTION(sdmmc4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) FUNCTION(soc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) FUNCTION(spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) FUNCTION(spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) FUNCTION(spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) FUNCTION(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) FUNCTION(spi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) FUNCTION(spi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) FUNCTION(spi6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) FUNCTION(sys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) FUNCTION(tmds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) FUNCTION(trace),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) FUNCTION(uarta),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) FUNCTION(uartb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) FUNCTION(uartc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) FUNCTION(uartd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) FUNCTION(ulpi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) FUNCTION(usb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) FUNCTION(vgp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) FUNCTION(vgp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) FUNCTION(vgp3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) FUNCTION(vgp4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) FUNCTION(vgp5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) FUNCTION(vgp6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) FUNCTION(vi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) FUNCTION(vi_alt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) FUNCTION(vi_alt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) FUNCTION(vimclk2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) FUNCTION(vimclk2_alt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define PINGROUP_REG_A 0x3000 /* bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define PINGROUP_BIT_Y(b) (b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #define PINGROUP_BIT_N(b) (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .funcs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) TEGRA_MUX_##f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) TEGRA_MUX_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) TEGRA_MUX_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) TEGRA_MUX_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .mux_reg = PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .mux_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .mux_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .pupd_reg = PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .pupd_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .pupd_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .tri_reg = PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .tri_bank = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .tri_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .einput_bit = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .odrain_bit = PINGROUP_BIT_##od(6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .lock_bit = 7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .ioreset_bit = PINGROUP_BIT_##ior(8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .drv_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .parked_bitmask = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) slwf_b, slwf_w, drvtype) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .name = "drive_" #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .pins = drive_##pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .mux_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .pupd_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .tri_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .einput_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .odrain_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .lock_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .ioreset_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .rcv_sel_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .drv_reg = DRV_PINGROUP_REG(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .drv_bank = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .hsm_bit = hsm_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .schmitt_bit = schmitt_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .lpmd_bit = lpmd_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .drvdn_bit = drvdn_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .drvdn_width = drvdn_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .drvup_bit = drvup_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .drvup_width = drvup_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .slwr_bit = slwr_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .slwr_width = slwr_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .slwf_bit = slwf_b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .slwf_width = slwf_w, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .parked_bitmask = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .name = "mipi_pad_ctrl_" #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .pins = mipi_pad_ctrl_##pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .funcs = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) TEGRA_MUX_ ## f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) TEGRA_MUX_ ## f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) TEGRA_MUX_RSVD3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) TEGRA_MUX_RSVD4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .mux_bank = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .mux_bit = b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .pupd_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .tri_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .einput_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .odrain_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .lock_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .ioreset_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .rcv_sel_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .drv_reg = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static const struct tegra_pingroup tegra124_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, 0x3008, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, 0x300c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, 0x3010, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, 0x3014, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, 0x3018, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, 0x301c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, 0x3020, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, 0x3024, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, 0x3028, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, 0x302c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3030, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, 0x3034, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, 0x3038, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, 0x303c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, 0x3040, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, 0x3044, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, 0x3048, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, 0x304c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, 0x3050, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, 0x3058, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, 0x305c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, 0x3068, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, 0x306c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, 0x3110, N, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, 0x3114, N, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, 0x3118, N, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, 0x3164, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, 0x3168, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, 0x316c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, 0x3170, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, 0x3174, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, 0x3178, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, 0x317c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, 0x3180, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, 0x3184, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, 0x3188, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, 0x318c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, 0x3190, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, 0x3194, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, 0x3198, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, 0x319c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, 0x31a0, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, 0x31a4, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, 0x31a8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, 0x31ac, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, 0x31b0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, 0x31b4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, 0x31b8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, 0x31bc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, 0x31c0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, 0x31c4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, 0x31c8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, 0x31cc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, 0x31d0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, 0x31d4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, 0x31d8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, 0x31dc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, 0x31e0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, 0x31e4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, 0x31e8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, 0x31ec, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, 0x31f0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, 0x31f4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, 0x31f8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, 0x31fc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, 0x3200, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, 0x3204, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, 0x3208, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, 0x320c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) PINGROUP(ph0, PWM0, TRACE, GMI, DTV, 0x3210, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, 0x3214, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, 0x3218, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, 0x321c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, 0x3220, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, 0x3224, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, 0x3228, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, 0x322c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, 0x3230, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, 0x3234, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, 0x3238, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, 0x323c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, 0x3240, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, 0x3244, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, 0x3248, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, 0x324c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, 0x3250, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, 0x3254, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, 0x3258, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, 0x325c, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, 0x3260, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, 0x3264, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, 0x3268, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, 0x326c, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, 0x3270, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, 0x3274, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, 0x3278, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, 0x327c, N, Y, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, 0x3284, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) PINGROUP(pcc1, I2S4, RSVD2, RSVD3, SDMMC2, 0x3288, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, 0x328c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, 0x3290, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, 0x3294, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, 0x3298, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, 0x329c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, 0x32a0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, 0x32a4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, 0x32a8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, 0x32ac, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, 0x32b0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b4, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, 0x32b8, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, 0x32bc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, 0x32c0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, 0x32c4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, 0x32c8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32cc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, 0x32d0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, 0x32d4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, 0x32d8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, 0x32dc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, 0x32e0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, 0x32e4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, 0x32e8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, 0x32ec, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, 0x32f0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, 0x32f4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, 0x32f8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, 0x32fc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, 0x3300, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, 0x3304, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, 0x3308, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, 0x330c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, 0x3310, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, 0x3314, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, 0x3318, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, 0x331c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, 0x3324, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, 0x3328, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, 0x332c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, 0x3330, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, 0x3334, N, N, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, 0x3338, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, 0x333c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, 0x3340, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, 0x3344, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, 0x3348, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, 0x334c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, 0x3350, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, 0x3354, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, 0x3358, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, 0x335c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, 0x3360, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, 0x3364, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, 0x3368, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, 0x336c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, 0x3370, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, 0x3374, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, 0x3378, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, 0x337c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, 0x3380, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, 0x3384, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, 0x3390, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, 0x3394, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, 0x3398, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, 0x339c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, 0x33a0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, 0x33bc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, 0x33c0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, 0x33c4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, 0x33cc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, 0x33d0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, 0x33e0, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, 0x33e4, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, 0x33e8, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, 0x33ec, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, 0x33f0, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, 0x33f4, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, 0x33f8, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, 0x33fc, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, 0x3400, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, 0x3404, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, 0x3408, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, 0x340c, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, 0x3410, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, 0x3414, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, 0x3418, Y, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, 0x3430, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* pg_name, r, b, f0, f1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .ngpios = NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .gpio_compatible = "nvidia,tegra124-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .pins = tegra124_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .npins = ARRAY_SIZE(tegra124_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .functions = tegra124_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .nfunctions = ARRAY_SIZE(tegra124_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .groups = tegra124_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .ngroups = ARRAY_SIZE(tegra124_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .hsm_in_mux = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .schmitt_in_mux = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .drvtype_in_mux = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static int tegra124_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) static const struct of_device_id tegra124_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) { .compatible = "nvidia,tegra124-pinmux", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) static struct platform_driver tegra124_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .name = "tegra124-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .of_match_table = tegra124_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .probe = tegra124_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static int __init tegra124_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) return platform_driver_register(&tegra124_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) arch_initcall(tegra124_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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