^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the NVIDIA Tegra pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __PINMUX_TEGRA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __PINMUX_TEGRA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct tegra_pmx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) const struct tegra_pinctrl_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) const char **group_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) int nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void __iomem **regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 *backup_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum tegra_pinconf_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* argument: tegra_pinconf_pull */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) TEGRA_PINCONF_PARAM_PULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* argument: tegra_pinconf_tristate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) TEGRA_PINCONF_PARAM_TRISTATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* argument: Boolean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) TEGRA_PINCONF_PARAM_ENABLE_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* argument: Boolean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) TEGRA_PINCONF_PARAM_OPEN_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* argument: Boolean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) TEGRA_PINCONF_PARAM_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* argument: Boolean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) TEGRA_PINCONF_PARAM_IORESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* argument: Boolean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) TEGRA_PINCONF_PARAM_RCV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* argument: Boolean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* argument: Boolean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) TEGRA_PINCONF_PARAM_SCHMITT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* argument: Boolean */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* argument: Integer, range is HW-dependant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* argument: Integer, range is HW-dependant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* argument: Integer, range is HW-dependant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* argument: Integer, range is HW-dependant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* argument: Integer, range is HW-dependant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) TEGRA_PINCONF_PARAM_DRIVE_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum tegra_pinconf_pull {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) TEGRA_PINCONFIG_PULL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) TEGRA_PINCONFIG_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) TEGRA_PINCONFIG_PULL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum tegra_pinconf_tristate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) TEGRA_PINCONFIG_DRIVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) TEGRA_PINCONFIG_TRISTATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * struct tegra_function - Tegra pinctrl mux function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @name: The name of the function, exported to pinctrl core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @groups: An array of pin groups that may select this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @ngroups: The number of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct tegra_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * struct tegra_pingroup - Tegra pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @name The name of the pin group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @pins An array of pin IDs included in this pin group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @npins The number of entries in @pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @funcs The mux functions which can be muxed onto this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @mux_reg: Mux register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * This register contains the mux, einput, odrain, lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * ioreset, rcv_sel parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @mux_bank: Mux register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @mux_bit: Mux register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @pupd_reg: Pull-up/down register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @pupd_bank: Pull-up/down register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @pupd_bit: Pull-up/down register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @tri_reg: Tri-state register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @tri_bank: Tri-state register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @tri_bit: Tri-state register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @einput_bit: Enable-input register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @odrain_bit: Open-drain register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @lock_bit: Lock register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @ioreset_bit: IO reset register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @rcv_sel_bit: Receiver select bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @drv_reg: Drive fields register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * This register contains hsm, schmitt, lpmd, drvdn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * drvup, slwr, slwf, and drvtype parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @drv_bank: Drive fields register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @hsm_bit: High Speed Mode register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @sfsel_bit: GPIO/SFIO selection register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @schmitt_bit: Schmitt register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @lpmd_bit: Low Power Mode register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @drvdn_bit: Drive Down register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @drvdn_width: Drive Down field width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @drvup_bit: Drive Up register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @drvup_width: Drive Up field width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @slwr_bit: Slew Rising register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @slwr_width: Slew Rising field width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @slwf_bit: Slew Falling register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @slwf_width: Slew Falling field width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @drvtype_bit: Drive type register bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @parked_bitmask: Parked register mask. 0 if unsupported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * -1 in a *_reg field means that feature is unsupported for this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * *_bank and *_reg values are irrelevant when *_reg is -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * A representation of a group of pins (possibly just one pin) in the Tegra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * pin controller. Each group allows some parameter or parameters to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * configured. The most common is mux function selection. Many others exist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * certain groups may only support configuring certain parameters, hence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * each parameter is optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct tegra_pingroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 funcs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) s32 mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) s32 pupd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) s32 tri_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) s32 drv_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 mux_bank:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 pupd_bank:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 tri_bank:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 drv_bank:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) s32 mux_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) s32 pupd_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) s32 tri_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) s32 einput_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) s32 odrain_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) s32 lock_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) s32 ioreset_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) s32 rcv_sel_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) s32 hsm_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) s32 sfsel_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) s32 schmitt_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) s32 lpmd_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) s32 drvdn_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) s32 drvup_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) s32 slwr_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) s32 slwf_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) s32 drvtype_bit:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) s32 drvdn_width:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) s32 drvup_width:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) s32 slwr_width:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) s32 slwf_width:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 parked_bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @ngpios: The number of GPIO pins the pin controller HW affects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @pins: An array describing all pins the pin controller affects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * All pins which are also GPIOs must be listed first within the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * array, and be numbered identically to the GPIO controller's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * numbering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @npins: The numbmer of entries in @pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @functions: An array describing all mux functions the SoC supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @nfunctions: The numbmer of entries in @functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @groups: An array describing all pin groups the pin SoC supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @ngroups: The numbmer of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct tegra_pinctrl_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const char *gpio_compatible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct tegra_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const struct tegra_pingroup *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool hsm_in_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool schmitt_in_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bool drvtype_in_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bool sfsel_in_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) extern const struct dev_pm_ops tegra_pinctrl_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int tegra_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const struct tegra_pinctrl_soc_data *soc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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