^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct tegra_xusb_padctl_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct tegra_xusb_padctl_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct tegra_xusb_padctl_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct tegra_xusb_padctl_lane *lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct tegra_xusb_padctl_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int iddq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const unsigned int *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int num_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct tegra_xusb_padctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) const struct tegra_xusb_padctl_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pinctrl_dev *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct pinctrl_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct phy *phys[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(value, padctl->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return readl(padctl->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return padctl->soc->num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return padctl->soc->pins[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * For the tegra-xusb pad controller groups are synonymous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * with lanes/pins and there is always one lane/pin per group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *pins = &pinctrl->desc->pins[group].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) enum tegra_xusb_padctl_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) TEGRA_XUSB_PADCTL_IDDQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct tegra_xusb_padctl_property {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) enum tegra_xusb_padctl_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct pinctrl_map **maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int i, reserve = 0, num_configs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long config, *configs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const char *function, *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) err = of_property_read_string(np, "nvidia,function", &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (err != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) function = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (i = 0; i < ARRAY_SIZE(properties); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) err = of_property_read_u32(np, properties[i].name, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (err == -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) err = pinctrl_utils_add_config(padctl->pinctrl, &configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) &num_configs, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) reserve++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) reserve++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) err = of_property_count_strings(np, "nvidia,lanes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) reserve *= err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) num_maps, reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) of_property_for_each_string(np, "nvidia,lanes", prop, group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reserved_maps, num_maps, group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (num_configs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) err = pinctrl_utils_add_map_configs(padctl->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) maps, reserved_maps, num_maps, group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) configs, num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PIN_MAP_TYPE_CONFIGS_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) kfree(configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct device_node *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct pinctrl_map **maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned int *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int reserved_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *maps = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for_each_child_of_node(parent, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) err = tegra_xusb_padctl_parse_subnode(padctl, np, maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) &reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .get_groups_count = tegra_xusb_padctl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .get_group_name = tegra_xusb_padctl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .get_group_pins = tegra_xusb_padctl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return padctl->soc->num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const char *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return padctl->soc->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *num_groups = padctl->soc->functions[function].num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *groups = padctl->soc->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const struct tegra_xusb_padctl_lane *lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) lane = &padctl->soc->lanes[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) for (i = 0; i < lane->num_funcs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (lane->funcs[i] == function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (i >= lane->num_funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) value = padctl_readl(padctl, lane->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) value &= ~(lane->mask << lane->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) value |= i << lane->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) padctl_writel(padctl, value, lane->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .get_functions_count = tegra_xusb_padctl_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .get_function_name = tegra_xusb_padctl_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .get_function_groups = tegra_xusb_padctl_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .set_mux = tegra_xusb_padctl_pinmux_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const struct tegra_xusb_padctl_lane *lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) enum tegra_xusb_padctl_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) lane = &padctl->soc->lanes[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case TEGRA_XUSB_PADCTL_IDDQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* lanes with iddq == 0 don't support this parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (lane->iddq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) value = padctl_readl(padctl, lane->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (value & BIT(lane->iddq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) value = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *config = TEGRA_XUSB_PADCTL_PACK(param, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(padctl->dev, "invalid configuration parameter: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) const struct tegra_xusb_padctl_lane *lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) enum tegra_xusb_padctl_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) lane = &padctl->soc->lanes[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case TEGRA_XUSB_PADCTL_IDDQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* lanes with iddq == 0 don't support this parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (lane->iddq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) regval = padctl_readl(padctl, lane->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) regval &= ~BIT(lane->iddq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) regval |= BIT(lane->iddq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) padctl_writel(padctl, regval, lane->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(padctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "invalid configuration parameter: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const char *strip_prefix(const char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) const char *comma = strchr(s, ',');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (!comma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return comma + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for (i = 0; i < ARRAY_SIZE(properties); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned long config, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) enum tegra_xusb_padctl_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) const char *name = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (i = 0; i < ARRAY_SIZE(properties); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (properties[i].param == param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) name = properties[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) seq_printf(s, "%s=%lu", strip_prefix(name), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mutex_lock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (padctl->enable++ > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mutex_lock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (WARN_ON(padctl->enable == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (--padctl->enable > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mutex_unlock(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int tegra_xusb_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return tegra_xusb_padctl_enable(padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int tegra_xusb_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return tegra_xusb_padctl_disable(padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int pcie_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) timeout = jiffies + msecs_to_jiffies(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int pcie_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const struct phy_ops pcie_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .init = tegra_xusb_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .exit = tegra_xusb_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .power_on = pcie_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .power_off = pcie_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int sata_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) timeout = jiffies + msecs_to_jiffies(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int sata_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const struct phy_ops sata_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .init = tegra_xusb_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .exit = tegra_xusb_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .power_on = sata_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .power_off = sata_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static struct phy *tegra_xusb_padctl_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned int index = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (args->args_count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (index >= ARRAY_SIZE(padctl->phys))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return padctl->phys[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define PIN_OTG_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define PIN_OTG_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define PIN_OTG_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define PIN_ULPI_0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define PIN_HSIC_0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define PIN_HSIC_1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define PIN_PCIE_0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define PIN_PCIE_1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define PIN_PCIE_2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define PIN_PCIE_3 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define PIN_PCIE_4 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define PIN_SATA_0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const struct pinctrl_pin_desc tegra124_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINCTRL_PIN(PIN_OTG_0, "otg-0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINCTRL_PIN(PIN_OTG_1, "otg-1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINCTRL_PIN(PIN_OTG_2, "otg-2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINCTRL_PIN(PIN_HSIC_0, "hsic-0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINCTRL_PIN(PIN_HSIC_1, "hsic-1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINCTRL_PIN(PIN_PCIE_0, "pcie-0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINCTRL_PIN(PIN_PCIE_1, "pcie-1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINCTRL_PIN(PIN_PCIE_2, "pcie-2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINCTRL_PIN(PIN_PCIE_3, "pcie-3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINCTRL_PIN(PIN_PCIE_4, "pcie-4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINCTRL_PIN(PIN_SATA_0, "sata-0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const char * const tegra124_snps_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "otg-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) "otg-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "otg-2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "ulpi-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "hsic-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "hsic-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const char * const tegra124_xusb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "otg-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "otg-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "otg-2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "ulpi-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "hsic-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "hsic-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const char * const tegra124_uart_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "otg-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "otg-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "otg-2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const char * const tegra124_pcie_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "pcie-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "pcie-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "pcie-2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "pcie-3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) "pcie-4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const char * const tegra124_usb3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "pcie-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "pcie-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "sata-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const char * const tegra124_sata_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "sata-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static const char * const tegra124_rsvd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "otg-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "otg-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "otg-2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "pcie-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "pcie-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "pcie-2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "pcie-3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "pcie-4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "sata-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define TEGRA124_FUNCTION(_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .groups = tegra124_##_name##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static struct tegra_xusb_padctl_function tegra124_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) TEGRA124_FUNCTION(snps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) TEGRA124_FUNCTION(xusb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) TEGRA124_FUNCTION(uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) TEGRA124_FUNCTION(pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TEGRA124_FUNCTION(usb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) TEGRA124_FUNCTION(sata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) TEGRA124_FUNCTION(rsvd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) enum tegra124_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) TEGRA124_FUNC_SNPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) TEGRA124_FUNC_XUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) TEGRA124_FUNC_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) TEGRA124_FUNC_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) TEGRA124_FUNC_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) TEGRA124_FUNC_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) TEGRA124_FUNC_RSVD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static const unsigned int tegra124_otg_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) TEGRA124_FUNC_SNPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) TEGRA124_FUNC_XUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) TEGRA124_FUNC_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) TEGRA124_FUNC_RSVD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const unsigned int tegra124_usb_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) TEGRA124_FUNC_SNPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) TEGRA124_FUNC_XUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const unsigned int tegra124_pci_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) TEGRA124_FUNC_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) TEGRA124_FUNC_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) TEGRA124_FUNC_SATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) TEGRA124_FUNC_RSVD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .offset = _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .iddq = _iddq, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .funcs = tegra124_##_funcs##_functions, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const struct tegra_xusb_padctl_soc tegra124_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .num_pins = ARRAY_SIZE(tegra124_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .pins = tegra124_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .num_functions = ARRAY_SIZE(tegra124_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .functions = tegra124_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .num_lanes = ARRAY_SIZE(tegra124_lanes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .lanes = tegra124_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct of_device_id tegra_xusb_padctl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* predeclare these in order to silence sparse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct tegra_xusb_padctl *padctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!padctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) platform_set_drvdata(pdev, padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mutex_init(&padctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) padctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * Note that we can't replace this by of_device_get_match_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * because we need the separate matching table for this legacy code on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * Tegra124. of_device_get_match_data() would attempt to use the table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * from the updated driver and fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) padctl->soc = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) padctl->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (IS_ERR(padctl->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return PTR_ERR(padctl->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) padctl->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (IS_ERR(padctl->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return PTR_ERR(padctl->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) err = reset_control_deassert(padctl->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) memset(&padctl->desc, 0, sizeof(padctl->desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) padctl->desc.name = dev_name(padctl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) padctl->desc.pins = tegra124_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) padctl->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) padctl->pinctrl = devm_pinctrl_register(&pdev->dev, &padctl->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (IS_ERR(padctl->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_err(&pdev->dev, "failed to register pincontrol\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) err = PTR_ERR(padctl->pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) goto reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) err = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) goto reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) phy_set_drvdata(phy, padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) err = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) goto reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) phy_set_drvdata(phy, padctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) padctl->provider = devm_of_phy_provider_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) tegra_xusb_padctl_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (IS_ERR(padctl->provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) err = PTR_ERR(padctl->provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_err(&pdev->dev, "failed to register PHYs: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) goto reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) reset_control_assert(padctl->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) err = reset_control_assert(padctl->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_err(&pdev->dev, "failed to assert reset: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) EXPORT_SYMBOL_GPL(tegra_xusb_padctl_legacy_remove);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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