^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2018 Icenowy Zheng
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2014 Jackie Hwang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Jackie Hwang <huangshr@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2014 Chen-Yu Tsai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright (C) 2014 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "pinctrl-sunxi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct sunxi_desc_pin suniv_f1c100s_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SUNXI_FUNCTION(0x6, "spi1")), /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SUNXI_FUNCTION(0x4, "i2s"), /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SUNXI_FUNCTION(0x5, "uart1"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SUNXI_FUNCTION(0x3, "ir0"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SUNXI_FUNCTION(0x5, "uart1"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SUNXI_FUNCTION(0x6, "spi1")), /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SUNXI_FUNCTION(0x2, "dram"), /* CKE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SUNXI_FUNCTION(0x4, "i2s"), /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SUNXI_FUNCTION(0x5, "uart1"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SUNXI_FUNCTION(0x3, "ir0"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SUNXI_FUNCTION(0x5, "uart1"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SUNXI_FUNCTION(0x2, "spi0"), /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SUNXI_FUNCTION(0x3, "uart0")), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SUNXI_FUNCTION(0x4, "rsb"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SUNXI_FUNCTION(0x2, "lcd"), /* D4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SUNXI_FUNCTION(0x3, "uart1"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SUNXI_FUNCTION(0x3, "uart1"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SUNXI_FUNCTION(0x3, "i2s"), /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SUNXI_FUNCTION(0x3, "i2s"), /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SUNXI_FUNCTION(0x4, "rsb"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SUNXI_FUNCTION(0x3, "uart2"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SUNXI_FUNCTION(0x3, "lvds1"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SUNXI_FUNCTION(0x3, "spi0"), /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) SUNXI_FUNCTION(0x2, "lcd"), /* DE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) SUNXI_FUNCTION(0x3, "spi0"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) SUNXI_FUNCTION(0x3, "lcd"), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) SUNXI_FUNCTION(0x5, "uart0"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SUNXI_FUNCTION(0x3, "lcd"), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SUNXI_FUNCTION(0x5, "uart0"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SUNXI_FUNCTION(0x3, "lcd"), /* D8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) SUNXI_FUNCTION(0x4, "clk"), /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SUNXI_FUNCTION(0x2, "csi"), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SUNXI_FUNCTION(0x3, "lcd"), /* D9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SUNXI_FUNCTION(0x5, "rsb"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SUNXI_FUNCTION(0x2, "csi"), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SUNXI_FUNCTION(0x3, "lcd"), /* D16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SUNXI_FUNCTION(0x5, "rsb"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) SUNXI_FUNCTION(0x2, "csi"), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) SUNXI_FUNCTION(0x3, "lcd"), /* D17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) SUNXI_FUNCTION(0x4, "i2s"), /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SUNXI_FUNCTION(0x2, "csi"), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SUNXI_FUNCTION(0x5, "spdif"), /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) SUNXI_FUNCTION(0x2, "csi"), /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SUNXI_FUNCTION(0x3, "uart2"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SUNXI_FUNCTION(0x4, "spi1"), /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SUNXI_FUNCTION(0x2, "csi"), /* D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SUNXI_FUNCTION(0x3, "uart2"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SUNXI_FUNCTION(0x2, "csi"), /* D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) SUNXI_FUNCTION(0x2, "csi"), /* D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SUNXI_FUNCTION(0x2, "clk0"), /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SUNXI_FUNCTION(0x4, "ir"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SUNXI_FUNCTION(0x3, "jtag"), /* MS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SUNXI_FUNCTION(0x4, "ir0"), /* MS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) SUNXI_FUNCTION(0x3, "dgb0"), /* DI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) SUNXI_FUNCTION(0x3, "uart0"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) SUNXI_FUNCTION(0x3, "jtag"), /* DO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SUNXI_FUNCTION(0x3, "uart0"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SUNXI_FUNCTION(0x3, "jtag"), /* CK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .pins = suniv_f1c100s_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .npins = ARRAY_SIZE(suniv_f1c100s_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .irq_banks = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int suniv_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return sunxi_pinctrl_init(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) &suniv_f1c100s_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct of_device_id suniv_f1c100s_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { .compatible = "allwinner,suniv-f1c100s-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct platform_driver suniv_f1c100s_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .probe = suniv_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .name = "suniv-f1c100s-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .of_match_table = suniv_f1c100s_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) builtin_platform_driver(suniv_f1c100s_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags