^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Allwinner A80 SoCs pinctrl driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "pinctrl-sunxi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct sunxi_desc_pin sun9i_a80_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SUNXI_FUNCTION(0x4, "uart1"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SUNXI_FUNCTION(0x4, "uart1"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SUNXI_FUNCTION(0x2, "gmac"), /* RXCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SUNXI_FUNCTION(0x2, "gmac"), /* RXCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SUNXI_FUNCTION(0x4, "uart1"), /* RING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SUNXI_FUNCTION(0x4, "eclk"), /* IN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SUNXI_FUNCTION(0x4, "eclk"), /* IN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SUNXI_FUNCTION(0x4, "clk_out_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SUNXI_FUNCTION(0x2, "gmac"), /* MII-CRS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SUNXI_FUNCTION(0x4, "clk_out_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SUNXI_FUNCTION(0x2, "gmac"), /* TXCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SUNXI_FUNCTION(0x4, "pwm3"), /* PWM_P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SUNXI_FUNCTION(0x2, "gmac"), /* RGMII-TXCK / GMII-TXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SUNXI_FUNCTION(0x4, "pwm3"), /* PWM_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SUNXI_FUNCTION(0x2, "gmac"), /* MII-TXERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SUNXI_FUNCTION(0x2, "gmac"), /* RGMII-CLKIN / MII-COL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SUNXI_FUNCTION(0x2, "gmac"), /* EMDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SUNXI_FUNCTION(0x2, "gmac"), /* EMDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SUNXI_FUNCTION(0x3, "uart3"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SUNXI_FUNCTION(0x3, "uart3"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) SUNXI_FUNCTION(0x3, "mcsi"), /* MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PB_EINT14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SUNXI_FUNCTION(0x3, "mcsi"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SUNXI_FUNCTION(0x4, "i2c4"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PB_EINT15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SUNXI_FUNCTION(0x3, "mcsi"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SUNXI_FUNCTION(0x4, "i2c4"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PB_EINT16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SUNXI_FUNCTION(0x2, "nand0"), /* WE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SUNXI_FUNCTION(0x2, "nand0")), /* RE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SUNXI_FUNCTION(0x2, "nand0"), /* CE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SUNXI_FUNCTION(0x3, "nand0_b")), /* RE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SUNXI_FUNCTION(0x2, "nand0"), /* CE3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SUNXI_FUNCTION(0x3, "nand0_b")), /* DQS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SUNXI_FUNCTION(0x3, "ts"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SUNXI_FUNCTION(0x3, "ts"), /* ERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) SUNXI_FUNCTION(0x2, "csi"), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) SUNXI_FUNCTION(0x4, "uart5"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) SUNXI_FUNCTION(0x2, "csi"), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) SUNXI_FUNCTION(0x4, "uart5"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SUNXI_FUNCTION(0x2, "csi"), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) SUNXI_FUNCTION(0x4, "uart5"), /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) SUNXI_FUNCTION(0x2, "csi"), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) SUNXI_FUNCTION(0x4, "uart5"), /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) SUNXI_FUNCTION(0x2, "csi"), /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SUNXI_FUNCTION(0x3, "ts"), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SUNXI_FUNCTION(0x2, "csi"), /* D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) SUNXI_FUNCTION(0x3, "ts"), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) SUNXI_FUNCTION(0x2, "csi"), /* D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SUNXI_FUNCTION(0x3, "ts"), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) SUNXI_FUNCTION(0x2, "csi"), /* D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) SUNXI_FUNCTION(0x3, "ts"), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SUNXI_FUNCTION(0x2, "csi"), /* D8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) SUNXI_FUNCTION(0x3, "ts"), /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) SUNXI_FUNCTION(0x2, "csi"), /* D9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SUNXI_FUNCTION(0x3, "ts"), /* D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SUNXI_FUNCTION(0x2, "csi"), /* D10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SUNXI_FUNCTION(0x3, "ts"), /* D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SUNXI_FUNCTION(0x2, "csi"), /* D11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) SUNXI_FUNCTION(0x3, "ts"), /* D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SUNXI_FUNCTION(0x2, "csi"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SUNXI_FUNCTION(0x3, "i2c4"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) SUNXI_FUNCTION(0x2, "csi"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) SUNXI_FUNCTION(0x3, "i2c4"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PE_EINT17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) SUNXI_FUNCTION(0x4, "uart0")), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) SUNXI_FUNCTION(0x4, "uart0")), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) SUNXI_FUNCTION(0x2, "uart2"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) SUNXI_FUNCTION(0x2, "uart2"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) SUNXI_FUNCTION(0x2, "uart4"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) SUNXI_FUNCTION(0x2, "uart4"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) SUNXI_FUNCTION(0x2, "uart4"), /* RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SUNXI_FUNCTION(0x2, "uart4"), /* CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SUNXI_FUNCTION(0x2, "pwm0")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) SUNXI_FUNCTION(0x3, "pwm1"), /* Positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 8)), /* PH_EINT8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SUNXI_FUNCTION(0x3, "pwm1"), /* Negative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 9)), /* PH_EINT9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SUNXI_FUNCTION(0x3, "pwm2"), /* Positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 10)), /* PH_EINT10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) SUNXI_FUNCTION(0x3, "pwm2"), /* Negative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 11)), /* PH_EINT12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) SUNXI_FUNCTION(0x2, "uart0"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) SUNXI_FUNCTION(0x3, "spi3"), /* CS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 12)), /* PH_EINT12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) SUNXI_FUNCTION(0x2, "uart0"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) SUNXI_FUNCTION(0x3, "spi3"), /* CS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 13)), /* PH_EINT13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) SUNXI_FUNCTION(0x2, "spi3"), /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 14)), /* PH_EINT14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) SUNXI_FUNCTION(0x2, "spi3"), /* MOSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 15)), /* PH_EINT15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SUNXI_FUNCTION(0x2, "spi3"), /* MISO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 16)), /* PH_EINT16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) SUNXI_FUNCTION(0x2, "spi3"), /* CS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 17)), /* PH_EINT17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) SUNXI_FUNCTION(0x2, "spi3"), /* CS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 18)), /* PH_EINT18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) SUNXI_FUNCTION(0x2, "hdmi")), /* SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) SUNXI_FUNCTION(0x2, "hdmi")), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) SUNXI_FUNCTION(0x2, "hdmi")), /* CEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .pins = sun9i_a80_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .npins = ARRAY_SIZE(sun9i_a80_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .irq_banks = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .disable_strict_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return sunxi_pinctrl_init(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) &sun9i_a80_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const struct of_device_id sun9i_a80_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { .compatible = "allwinner,sun9i-a80-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static struct platform_driver sun9i_a80_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .probe = sun9i_a80_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .name = "sun9i-a80-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .of_match_table = sun9i_a80_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) builtin_platform_driver(sun9i_a80_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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