^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Allwinner A80 SoCs special pins pinctrl driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "pinctrl-sunxi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) SUNXI_FUNCTION(0x3, "s_uart"), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SUNXI_FUNCTION(0x3, "s_uart"), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SUNXI_FUNCTION(0x3, "s_jtag"), /* TMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SUNXI_FUNCTION(0x3, "s_jtag"), /* TCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SUNXI_FUNCTION(0x3, "s_jtag"), /* TDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SUNXI_FUNCTION(0x3, "s_jtag"), /* TDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SUNXI_FUNCTION(0x3, "s_cir_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SUNXI_FUNCTION(0x3, "1wire"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SUNXI_FUNCTION(0x2, "s_ps2"), /* SCK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SUNXI_FUNCTION(0x2, "s_ps2"), /* SDA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PM_EINT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PM_EINT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PM_EINT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PM_EINT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SUNXI_FUNCTION(0x3, "s_i2s1"), /* LRCKR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PM_EINT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SUNXI_FUNCTION(0x3, "s_i2c1"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PM_EINT8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SUNXI_FUNCTION(0x3, "s_i2c1"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PM_EINT9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SUNXI_FUNCTION(0x2, "s_i2s0"), /* MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SUNXI_FUNCTION(0x3, "s_i2s1")), /* MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SUNXI_FUNCTION(0x2, "s_i2s0"), /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SUNXI_FUNCTION(0x3, "s_i2s1")), /* BCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SUNXI_FUNCTION(0x2, "s_i2s0"), /* LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SUNXI_FUNCTION(0x3, "s_i2s1")), /* LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SUNXI_FUNCTION(0x2, "s_i2s0"), /* DIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SUNXI_FUNCTION(0x3, "s_i2s1")), /* DIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SUNXI_FUNCTION(0x2, "s_i2s0"), /* DOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SUNXI_FUNCTION(0x3, "s_i2s1")), /* DOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PM_EINT15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SUNXI_FUNCTION(0x3, "s_rsb")), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) SUNXI_FUNCTION(0x3, "s_rsb")), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .pins = sun9i_a80_r_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .npins = ARRAY_SIZE(sun9i_a80_r_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .pin_base = PL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .irq_banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .disable_strict_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return sunxi_pinctrl_init(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) &sun9i_a80_r_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .compatible = "allwinner,sun9i-a80-r-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct platform_driver sun9i_a80_r_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .probe = sun9i_a80_r_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "sun9i-a80-r-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .of_match_table = sun9i_a80_r_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) builtin_platform_driver(sun9i_a80_r_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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