^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Allwinner A31 SoCs special pins pinctrl driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Boris Brezillon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Boris Brezillon <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2014 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-sunxi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0), /* PL_EINT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1), /* PL_EINT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2), /* PL_EINT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3), /* PL_EINT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Hole */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0)), /* PM_EINT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1)), /* PM_EINT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2), /* PM_EINT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SUNXI_FUNCTION(0x3, "1wire")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3)), /* PM_EINT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4)), /* PM_EINT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5)), /* PM_EINT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6)), /* PM_EINT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SUNXI_FUNCTION(0x0, "gpio_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) SUNXI_FUNCTION(0x1, "gpio_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7), /* PM_EINT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .pins = sun6i_a31_r_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .npins = ARRAY_SIZE(sun6i_a31_r_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .pin_base = PL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .irq_banks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .disable_strict_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (IS_ERR(rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_err(&pdev->dev, "Reset controller missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return PTR_ERR(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = reset_control_deassert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = sunxi_pinctrl_init(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) &sun6i_a31_r_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reset_control_assert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct of_device_id sun6i_a31_r_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .compatible = "allwinner,sun6i-a31-r-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct platform_driver sun6i_a31_r_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .probe = sun6i_a31_r_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .name = "sun6i-a31-r-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .of_match_table = sun6i_a31_r_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) builtin_platform_driver(sun6i_a31_r_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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