^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) Maxime Coquelin 2015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Heavily based on Mediatek's pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "pinctrl-stm32.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STM32_GPIO_MODER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STM32_GPIO_TYPER 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STM32_GPIO_SPEEDR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STM32_GPIO_PUPDR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STM32_GPIO_IDR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STM32_GPIO_ODR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STM32_GPIO_BSRR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STM32_GPIO_LCKR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STM32_GPIO_AFRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STM32_GPIO_AFRH 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* custom bitfield to backup pin status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STM32_GPIO_BKP_MODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STM32_GPIO_BKP_ALT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STM32_GPIO_BKP_SPEED_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STM32_GPIO_BKP_PUPD_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STM32_GPIO_BKP_TYPE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STM32_GPIO_BKP_VAL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STM32_GPIO_PINS_PER_BANK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STM32_GPIO_IRQ_LINE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define gpio_range_to_bank(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) container_of(chip, struct stm32_gpio_bank, range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HWSPNLCK_TIMEOUT 1000 /* usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const char * const stm32_gpio_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "gpio", "af0", "af1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "af2", "af3", "af4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "af5", "af6", "af7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "af8", "af9", "af10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "af11", "af12", "af13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "af14", "af15", "analog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct stm32_pinctrl_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct stm32_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct pinctrl_gpio_range range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 bank_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 bank_ioport_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 irq_type[STM32_GPIO_PINS_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct stm32_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct pinctrl_dev *pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct pinctrl_desc pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct stm32_pinctrl_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const char **grp_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct stm32_gpio_bank *banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct stm32_pinctrl_match_data *match_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct hwspinlock *hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct stm32_desc_pin *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 pkg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u16 irqmux_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) spinlock_t irqmux_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline int stm32_gpio_pin(int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return gpio % STM32_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline u32 stm32_gpio_get_mode(u32 function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) switch (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case STM32_PIN_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case STM32_PIN_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline u32 stm32_gpio_get_alt(u32 function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) switch (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case STM32_PIN_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return function - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case STM32_PIN_ANALOG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 mode, u32 alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) STM32_GPIO_BKP_ALT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* GPIO functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) stm32_gpio_backup_value(bank, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) offset += STM32_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_err(pctl->dev, "pin %d not in range.\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return pinctrl_gpio_request(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pinctrl_gpio_free(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __stm32_gpio_set(bank, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int stm32_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __stm32_gpio_set(bank, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct irq_fwspec fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) fwspec.fwnode = bank->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) fwspec.param_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) fwspec.param[0] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) fwspec.param[1] = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return irq_create_fwspec_mapping(&fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int pin = stm32_gpio_pin(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 mode, alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) stm32_pmx_get_mode(bank, pin, &mode, &alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if ((alt == 0) && (mode == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else if ((alt == 0) && (mode == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct gpio_chip stm32_gpio_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .request = stm32_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .free = stm32_gpio_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .get = stm32_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .set = stm32_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .direction_input = stm32_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .direction_output = stm32_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .to_irq = stm32_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .get_direction = stm32_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .set_config = gpiochip_generic_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void stm32_gpio_irq_trigger(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct stm32_gpio_bank *bank = d->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* If level interrupt type then retrig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) irq_chip_retrigger_hierarchy(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void stm32_gpio_irq_eoi(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) irq_chip_eoi_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) stm32_gpio_irq_trigger(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct stm32_gpio_bank *bank = d->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 parent_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) parent_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) parent_type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) parent_type = IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bank->irq_type[d->hwirq] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return irq_chip_set_type_parent(d, parent_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct stm32_gpio_bank *bank = irq_data->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) irq_data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct stm32_gpio_bank *bank = irq_data->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void stm32_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) stm32_gpio_irq_trigger(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct irq_chip stm32_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "stm32gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .irq_eoi = stm32_gpio_irq_eoi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .irq_ack = irq_chip_ack_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .irq_unmask = stm32_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .irq_set_type = stm32_gpio_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .irq_set_wake = irq_chip_set_wake_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .irq_request_resources = stm32_gpio_irq_request_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .irq_release_resources = stm32_gpio_irq_release_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int stm32_gpio_domain_translate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if ((fwspec->param_count != 2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *type = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int stm32_gpio_domain_activate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct irq_data *irq_data, bool reserve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct stm32_gpio_bank *bank = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * gpio irq mux is shared between several banks, a lock has to be done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * to avoid overriding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) spin_lock_irqsave(&pctl->irqmux_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (pctl->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) HWSPNLCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(pctl->dev, "Can't get hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(pctl->dev, "irq line %ld already requested.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) irq_data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (pctl->hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) hwspin_unlock_in_atomic(pctl->hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pctl->irqmux_map |= BIT(irq_data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (pctl->hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hwspin_unlock_in_atomic(pctl->hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void stm32_gpio_domain_deactivate(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct irq_data *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct stm32_gpio_bank *bank = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spin_lock_irqsave(&pctl->irqmux_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pctl->irqmux_map &= ~BIT(irq_data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int stm32_gpio_domain_alloc(struct irq_domain *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned int nr_irqs, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct stm32_gpio_bank *bank = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct irq_fwspec *fwspec = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct irq_fwspec parent_fwspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) hwirq = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) parent_fwspec.fwnode = d->parent->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) parent_fwspec.param_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) parent_fwspec.param[0] = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) parent_fwspec.param[1] = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct irq_domain_ops stm32_gpio_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .translate = stm32_gpio_domain_translate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .alloc = stm32_gpio_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .free = irq_domain_free_irqs_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .activate = stm32_gpio_domain_activate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .deactivate = stm32_gpio_domain_deactivate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Pinctrl functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static struct stm32_pinctrl_group *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) for (i = 0; i < pctl->ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct stm32_pinctrl_group *grp = pctl->groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (grp->pin == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 pin_num, u32 fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) for (i = 0; i < pctl->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct stm32_desc_pin *pin = pctl->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const struct stm32_desc_function *func = pin->functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (pin->pin.number != pin_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) while (func && func->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (func->num == fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) func++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct pinctrl_map **map, unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (*num_maps == *reserved_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) (*map)[*num_maps].data.mux.group = grp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_err(pctl->dev, "invalid function %d on pin %d .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) fnum, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) (*num_maps)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned *reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct stm32_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct stm32_pinctrl_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct property *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 pinfunc, pin, func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned long *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned int num_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) bool has_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned reserve = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int num_pins, num_funcs, maps_per_pin, i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pins = of_find_property(node, "pinmux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) &num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) has_config = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) num_pins = pins->length / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) num_funcs = num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) maps_per_pin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (num_funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) maps_per_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (has_config && num_pins >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) maps_per_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!num_pins || !maps_per_pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) reserve = num_pins * maps_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) err = pinctrl_utils_reserve_map(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) reserved_maps, num_maps, reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) for (i = 0; i < num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) err = of_property_read_u32_index(node, "pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) i, &pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pin = STM32_GET_PIN_NO(pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) func = STM32_GET_PIN_FUNC(pinfunc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(pctl->dev, "invalid function.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) grp = stm32_pctrl_find_group_by_pin(pctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(pctl->dev, "unable to match pin %d to group\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) reserved_maps, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (has_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) err = pinctrl_utils_add_map_configs(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) reserved_maps, num_maps, grp->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) configs, num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PIN_MAP_TYPE_CONFIGS_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) kfree(configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unsigned reserved_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) reserved_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) for_each_child_of_node(np_config, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) &reserved_maps, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pinctrl_utils_free_map(pctldev, *map, *num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return pctl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return pctl->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) *pins = (unsigned *)&pctl->groups[group].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const struct pinctrl_ops stm32_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .dt_node_to_map = stm32_pctrl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .get_groups_count = stm32_pctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .get_group_name = stm32_pctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .get_group_pins = stm32_pctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Pinmux functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ARRAY_SIZE(stm32_gpio_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return stm32_gpio_functions[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) *groups = pctl->grp_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) *num_groups = pctl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int pin, u32 mode, u32 alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int alt_shift = (pin % 8) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (pctl->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) HWSPNLCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_err(pctl->dev, "Can't get hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) val = readl_relaxed(bank->base + alt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) val &= ~GENMASK(alt_shift + 3, alt_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) val |= (alt << alt_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) writel_relaxed(val, bank->base + alt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) val = readl_relaxed(bank->base + STM32_GPIO_MODER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) val &= ~GENMASK(pin * 2 + 1, pin * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) val |= mode << (pin * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) writel_relaxed(val, bank->base + STM32_GPIO_MODER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (pctl->hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) hwspin_unlock_in_atomic(pctl->hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) stm32_gpio_backup_mode(bank, pin, mode, alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u32 *alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int alt_shift = (pin % 8) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) val = readl_relaxed(bank->base + alt_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) val &= GENMASK(alt_shift + 3, alt_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *alt = val >> alt_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) val = readl_relaxed(bank->base + STM32_GPIO_MODER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) val &= GENMASK(pin * 2 + 1, pin * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) *mode = val >> (pin * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) bool ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct stm32_pinctrl_group *g = pctl->groups + group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct stm32_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 mode, alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_err(pctl->dev, "invalid function %d on group %d .\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) function, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev_err(pctl->dev, "No gpio range defined.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) bank = gpiochip_get_data(range->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pin = stm32_gpio_pin(g->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) mode = stm32_gpio_get_mode(function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) alt = stm32_gpio_get_alt(function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return stm32_pmx_set_mode(bank, pin, mode, alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct pinctrl_gpio_range *range, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int pin = stm32_gpio_pin(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return stm32_pmx_set_mode(bank, pin, !input, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct pinmux_ops stm32_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .get_functions_count = stm32_pmx_get_funcs_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .get_function_name = stm32_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .get_function_groups = stm32_pmx_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .set_mux = stm32_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .gpio_set_direction = stm32_pmx_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Pinconf functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) unsigned offset, u32 drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (pctl->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) HWSPNLCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_err(pctl->dev, "Can't get hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) val &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) val |= drive << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (pctl->hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) hwspin_unlock_in_atomic(pctl->hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) stm32_gpio_backup_driving(bank, offset, drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) val &= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return (val >> offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) unsigned offset, u32 speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (pctl->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) HWSPNLCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dev_err(pctl->dev, "Can't get hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) val &= ~GENMASK(offset * 2 + 1, offset * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) val |= speed << (offset * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (pctl->hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) hwspin_unlock_in_atomic(pctl->hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) stm32_gpio_backup_speed(bank, offset, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) val &= GENMASK(offset * 2 + 1, offset * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return (val >> (offset * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) unsigned offset, u32 bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (pctl->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) HWSPNLCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dev_err(pctl->dev, "Can't get hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) val &= ~GENMASK(offset * 2 + 1, offset * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) val |= bias << (offset * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (pctl->hwlock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) hwspin_unlock_in_atomic(pctl->hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) stm32_gpio_backup_bias(bank, offset, bias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) val &= GENMASK(offset * 2 + 1, offset * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return (val >> (offset * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) unsigned int offset, bool dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) clk_enable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) spin_lock_irqsave(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) spin_unlock_irqrestore(&bank->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) clk_disable(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unsigned int pin, enum pin_config_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) enum pin_config_param arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct stm32_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) int offset, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (!range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_err(pctl->dev, "No gpio range defined.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) bank = gpiochip_get_data(range->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) offset = stm32_gpio_pin(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ret = stm32_pconf_set_driving(bank, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret = stm32_pconf_set_driving(bank, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = stm32_pconf_set_speed(bank, offset, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ret = stm32_pconf_set_bias(bank, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = stm32_pconf_set_bias(bank, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ret = stm32_pconf_set_bias(bank, offset, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) __stm32_gpio_set(bank, offset, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) *config = pctl->groups[group].config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct stm32_pinctrl_group *g = &pctl->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) mutex_lock(&pctldev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = stm32_pconf_parse_conf(pctldev, g->pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) pinconf_to_config_param(configs[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) pinconf_to_config_argument(configs[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) mutex_unlock(&pctldev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) g->config = configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ret = stm32_pconf_parse_conf(pctldev, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) pinconf_to_config_param(configs[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) pinconf_to_config_argument(configs[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct stm32_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u32 mode, alt, drive, speed, bias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const char * const modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) "input", "output", "alternate", "analog" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static const char * const speeds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) "low", "medium", "high", "very high" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static const char * const biasing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) "floating", "pull up", "pull down", "" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) bool val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) bank = gpiochip_get_data(range->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) offset = stm32_gpio_pin(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) stm32_pmx_get_mode(bank, offset, &mode, &alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) bias = stm32_pconf_get_bias(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) seq_printf(s, "%s ", modes[mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) val = stm32_pconf_get(bank, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) seq_printf(s, "- %s - %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) val ? "high" : "low",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) biasing[bias]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) drive = stm32_pconf_get_driving(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) speed = stm32_pconf_get_speed(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) val = stm32_pconf_get(bank, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) seq_printf(s, "- %s - %s - %s - %s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) val ? "high" : "low",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) drive ? "open drain" : "push pull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) biasing[bias],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) speeds[speed], "speed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* alternate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) drive = stm32_pconf_get_driving(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) speed = stm32_pconf_get_speed(bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) seq_printf(s, "%d - %s - %s - %s %s", alt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) drive ? "open drain" : "push pull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) biasing[bias],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) speeds[speed], "speed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static const struct pinconf_ops stm32_pconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .pin_config_group_get = stm32_pconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .pin_config_group_set = stm32_pconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .pin_config_set = stm32_pconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .pin_config_dbg_show = stm32_pconf_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) int bank_ioport_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct pinctrl_gpio_range *range = &bank->range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct device *dev = pctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) int npins = STM32_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) int bank_nr, err, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (!IS_ERR(bank->rstc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) reset_control_deassert(bank->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (of_address_to_resource(np, 0, &res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) bank->base = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (IS_ERR(bank->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return PTR_ERR(bank->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) err = clk_prepare(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) dev_err(dev, "failed to prepare clk (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) bank->gpio_chip = stm32_gpio_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) bank->gpio_chip.base = args.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* get the last defined gpio line (offset + nb of pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) npins = args.args[0] + args.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) npins = max(npins, (int)(args.args[0] + args.args[2]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) bank_nr = pctl->nbanks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) range->name = bank->gpio_chip.label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) range->id = bank_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) range->base = range->id * STM32_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) range->npins = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) range->gc = &bank->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) pinctrl_add_gpio_range(pctl->pctl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) &pctl->banks[bank_nr].range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) bank_ioport_nr = bank_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) bank->gpio_chip.ngpio = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) bank->gpio_chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) bank->gpio_chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) bank->bank_nr = bank_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) bank->bank_ioport_nr = bank_ioport_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) spin_lock_init(&bank->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* create irq hierarchical domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) bank->fwnode = of_node_to_fwnode(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) STM32_GPIO_IRQ_LINE, bank->fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) &stm32_gpio_domain_ops, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (!bank->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) err = gpiochip_add_data(&bank->gpio_chip, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (!of_find_property(np, "interrupt-parent", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) parent = of_irq_find_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return ERR_PTR(-ENXIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) domain = irq_find_host(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (!domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* domain not registered yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct stm32_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct regmap *rm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) int offset, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) int mask, mask_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (IS_ERR(pctl->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return PTR_ERR(pctl->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) rm = pctl->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) mask = SYSCFG_IRQMUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) mask_width = fls(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct reg_field mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) mux.reg = offset + (i / 4) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) mux.lsb = (i % 4) * mask_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) mux.msb = mux.lsb + mask_width - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) i, mux.reg, mux.lsb, mux.msb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (IS_ERR(pctl->irqmux[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return PTR_ERR(pctl->irqmux[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static int stm32_pctrl_build_state(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) pctl->ngroups = pctl->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* Allocate groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) sizeof(*pctl->groups), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (!pctl->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* We assume that one pin is one group, use pin name as group name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) sizeof(*pctl->grp_names), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (!pctl->grp_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) for (i = 0; i < pctl->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) const struct stm32_desc_pin *pin = pctl->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct stm32_pinctrl_group *group = pctl->groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) group->name = pin->pin.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) group->pin = pin->pin.number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) pctl->grp_names[i] = pin->pin.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) struct stm32_desc_pin *pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) const struct stm32_desc_pin *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) int i, nb_pins_available = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) for (i = 0; i < pctl->match_data->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) p = pctl->match_data->pins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (pctl->pkg && !(pctl->pkg & p->pkg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) pins->pin = p->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pins->functions = p->functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) pins++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) nb_pins_available++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) pctl->npins = nb_pins_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static void stm32_pctl_get_package(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct stm32_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) pctl->pkg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) dev_warn(pctl->dev, "No package detected, use default one\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) int stm32_pctl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct stm32_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) int i, ret, hwlock_id, banks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) match = of_match_device(dev->driver->of_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (!match || !match->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (!of_find_property(np, "pins-are-numbered", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dev_err(dev, "only support pins-are-numbered format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (!pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) platform_set_drvdata(pdev, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /* check for IRQ controller (may require deferred probe) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) pctl->domain = stm32_pctrl_get_irq_domain(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (IS_ERR(pctl->domain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return PTR_ERR(pctl->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* hwspinlock is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (hwlock_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (hwlock_id == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return hwlock_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) spin_lock_init(&pctl->irqmux_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) pctl->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) pctl->match_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* get package information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) stm32_pctl_get_package(np, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) sizeof(*pctl->pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (!pctl->pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = stm32_pctrl_build_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dev_err(dev, "build state failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (pctl->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) for (i = 0; i < pctl->npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) pins[i] = pctl->pins[i].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) pctl->pctl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) pctl->pctl_desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pctl->pctl_desc.pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) pctl->pctl_desc.npins = pctl->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) pctl->pctl_desc.link_consumers = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) pctl->pctl_desc.confops = &stm32_pconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) pctl->pctl_desc.pmxops = &stm32_pmx_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) pctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (IS_ERR(pctl->pctl_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) dev_err(&pdev->dev, "Failed pinctrl registration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return PTR_ERR(pctl->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) for_each_available_child_of_node(np, child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (of_property_read_bool(child, "gpio-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) banks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (!banks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) dev_err(dev, "at least one GPIO bank is required\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (!pctl->banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct stm32_gpio_bank *bank = &pctl->banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if (of_property_read_bool(child, "gpio-controller")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) bank->rstc = of_reset_control_get_exclusive(child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (PTR_ERR(bank->rstc) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) bank->clk = of_clk_get_by_name(child, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (IS_ERR(bank->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) "failed to get clk (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) PTR_ERR(bank->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return PTR_ERR(bank->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (of_property_read_bool(child, "gpio-controller")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) ret = stm32_gpiolib_register_bank(pctl, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) pctl->nbanks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) dev_info(dev, "Pinctrl STM32 initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) struct stm32_pinctrl *pctl, u32 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) u32 val, alt, mode, offset = stm32_gpio_pin(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct pinctrl_gpio_range *range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct stm32_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) bool pin_is_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (!desc || (!pin_is_irq && !desc->gpio_owner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) bank = gpiochip_get_data(range->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) alt >>= STM32_GPIO_BKP_ALT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) mode >>= STM32_GPIO_BKP_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ret = stm32_pmx_set_mode(bank, offset, mode, alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (mode == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) val = val >> STM32_GPIO_BKP_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) __stm32_gpio_set(bank, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) val >>= STM32_GPIO_BKP_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) ret = stm32_pconf_set_driving(bank, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) val >>= STM32_GPIO_BKP_SPEED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ret = stm32_pconf_set_speed(bank, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) val >>= STM32_GPIO_BKP_PUPD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ret = stm32_pconf_set_bias(bank, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (pin_is_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) int __maybe_unused stm32_pinctrl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct stm32_pinctrl_group *g = pctl->groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) for (i = 0; i < pctl->ngroups; i++, g++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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