^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver header file for pin controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __PINCTRL_SPRD_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __PINCTRL_SPRD_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define NUM_OFFSET (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TYPE_OFFSET (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BIT_OFFSET (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define WIDTH_OFFSET (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPRD_PIN_INFO(num, type, offset, width, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) (((num) & 0xFFF) << NUM_OFFSET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ((type) & 0xF) << TYPE_OFFSET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ((offset) & 0xFF) << BIT_OFFSET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ((width) & 0xF) << WIDTH_OFFSET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ((reg) & 0xF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRD_PINCTRL_PIN(pin) SPRD_PINCTRL_PIN_DATA(pin, #pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPRD_PINCTRL_PIN_DATA(a, b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .name = b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .num = (((a) >> NUM_OFFSET) & 0xfff), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .type = (((a) >> TYPE_OFFSET) & 0xf), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .bit_width = ((a) >> WIDTH_OFFSET & 0xf), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .reg = ((a) & 0xf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum pin_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) GLOBAL_CTRL_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) COMMON_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MISC_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct sprd_pins_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum pin_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* for global control pins configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int sprd_pinctrl_core_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct sprd_pins_info *sprd_soc_pin_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int pins_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int sprd_pinctrl_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void sprd_pinctrl_shutdown(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif /* __PINCTRL_SPRD_H__ */