^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Spreadtrum pin controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "../pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "pinctrl-sprd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PINCTRL_BIT_MASK(width) (~(~0UL << (width)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PINCTRL_REG_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PINCTRL_REG_MISC_OFFSET 0x4020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PINCTRL_REG_LEN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PIN_FUNC_MASK (BIT(4) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PIN_FUNC_SEL_1 ~PIN_FUNC_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PIN_FUNC_SEL_2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PIN_FUNC_SEL_3 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PIN_FUNC_SEL_4 PIN_FUNC_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AP_SLEEP_MODE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PUBCP_SLEEP_MODE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TGLDSP_SLEEP_MODE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AGDSP_SLEEP_MODE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CM4_SLEEP_MODE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLEEP_MODE_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SLEEP_MODE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SLEEP_INPUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SLEEP_INPUT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SLEEP_INPUT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SLEEP_OUTPUT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SLEEP_OUTPUT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SLEEP_OUTPUT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DRIVE_STRENGTH_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DRIVE_STRENGTH_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SLEEP_PULL_DOWN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SLEEP_PULL_DOWN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SLEEP_PULL_DOWN_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PULL_DOWN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PULL_DOWN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PULL_DOWN_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SLEEP_PULL_UP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SLEEP_PULL_UP_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SLEEP_PULL_UP_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PULL_UP_4_7K (BIT(12) | BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PULL_UP_20K BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PULL_UP_MASK 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PULL_UP_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define INPUT_SCHMITT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define INPUT_SCHMITT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define INPUT_SCHMITT_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum pin_sleep_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) AP_SLEEP = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PUBCP_SLEEP = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) TGLDSP_SLEEP = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) AGDSP_SLEEP = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CM4_SLEEP = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum pin_func_sel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PIN_FUNC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PIN_FUNC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PIN_FUNC_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PIN_FUNC_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PIN_FUNC_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * struct sprd_pin: represent one pin's description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @name: pin name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @number: pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @type: pin type, can be GLOBAL_CTRL_PIN/COMMON_PIN/MISC_PIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @reg: pin register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @bit_offset: bit offset in pin register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @bit_width: bit width in pin register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct sprd_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum pin_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * struct sprd_pin_group: represent one group's description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @name: group name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @npins: pin numbers of this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @pins: pointer to pins array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct sprd_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * struct sprd_pinctrl_soc_info: represent the SoC's pins description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @groups: pointer to groups of pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @ngroups: group numbers of the whole SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @pins: pointer to pins description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @npins: pin numbers of the whole SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @grp_names: pointer to group names array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct sprd_pinctrl_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct sprd_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct sprd_pin *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const char **grp_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * struct sprd_pinctrl: represent the pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @dev: pointer to the device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @pctl: pointer to the pinctrl handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @base: base address of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @info: pointer to SoC's pins description information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct sprd_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct sprd_pinctrl_soc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SPRD_PIN_CONFIG_SLEEP_MODE (PIN_CONFIG_END + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < info->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!strcmp(info->pins[i].name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return info->pins[i].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct sprd_pin *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sprd_pinctrl_get_pin_by_id(struct sprd_pinctrl *sprd_pctl, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct sprd_pin *pin = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (i = 0; i < info->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (info->pins[i].number == id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pin = &info->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct sprd_pin_group *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sprd_pinctrl_find_group_by_name(struct sprd_pinctrl *sprd_pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const struct sprd_pin_group *grp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (i = 0; i < info->ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!strcmp(info->groups[i].name, name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) grp = &info->groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int sprd_pctrl_group_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct sprd_pinctrl_soc_info *info = pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return info->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const char *sprd_pctrl_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct sprd_pinctrl_soc_info *info = pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return info->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int sprd_pctrl_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct sprd_pinctrl_soc_info *info = pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (selector >= info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *pins = info->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *npins = info->groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int sprd_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) const struct sprd_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long *configs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int num_configs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int reserved_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int reserve = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const char *function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) enum pinctrl_map_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) grp = sprd_pinctrl_find_group_by_name(pctl, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(pctl->dev, "unable to find group for node %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) of_node_full_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = of_property_count_strings(np, "pins");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ret == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) type = PIN_MAP_TYPE_CONFIGS_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) type = PIN_MAP_TYPE_CONFIGS_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret = of_property_read_string(np, "function", &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "%s: could not parse property function\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) of_node_full_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) function = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) &num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(pctl->dev, "%s: could not parse node property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) of_node_full_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (function != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reserve++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) reserve++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) num_maps, reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = pinctrl_utils_add_map_mux(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &reserved_maps, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) grp->name, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (num_configs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) const char *group_or_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int pin_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (type == PIN_MAP_TYPE_CONFIGS_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pin_id = grp->pins[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) group_or_pin = pin_get_name(pctldev, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) group_or_pin = grp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = pinctrl_utils_add_map_configs(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) &reserved_maps, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) group_or_pin, configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) num_configs, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) kfree(configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void sprd_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) seq_printf(s, "%s", dev_name(pctldev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct pinctrl_ops sprd_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .get_groups_count = sprd_pctrl_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .get_group_name = sprd_pctrl_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .get_group_pins = sprd_pctrl_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .pin_dbg_show = sprd_pctrl_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .dt_node_to_map = sprd_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int sprd_pmx_get_function_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return PIN_FUNC_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const char *sprd_pmx_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) switch (selector) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case PIN_FUNC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return "func1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case PIN_FUNC_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return "func2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case PIN_FUNC_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return "func3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case PIN_FUNC_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return "func4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return "null";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int sprd_pmx_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct sprd_pinctrl_soc_info *info = pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *groups = info->grp_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *num_groups = info->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int sprd_pmx_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int func_selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int group_selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct sprd_pinctrl_soc_info *info = pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct sprd_pin_group *grp = &info->groups[group_selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int i, grp_pins = grp->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (group_selector >= info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) switch (func_selector) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case PIN_FUNC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) val &= PIN_FUNC_SEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case PIN_FUNC_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) val |= PIN_FUNC_SEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case PIN_FUNC_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) val |= PIN_FUNC_SEL_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case PIN_FUNC_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val |= PIN_FUNC_SEL_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) for (i = 0; i < grp_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int pin_id = grp->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!pin || pin->type != COMMON_PIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) reg = readl((void __iomem *)pin->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) reg &= ~PIN_FUNC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) reg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writel(reg, (void __iomem *)pin->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct pinmux_ops sprd_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .get_functions_count = sprd_pmx_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .get_function_name = sprd_pmx_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .get_function_groups = sprd_pmx_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .set_mux = sprd_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int reg, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (pin->type == GLOBAL_CTRL_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) reg = (readl((void __iomem *)pin->reg) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) reg = readl((void __iomem *)pin->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (pin->type == GLOBAL_CTRL_PIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) param == SPRD_PIN_CONFIG_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) arg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case SPRD_PIN_CONFIG_SLEEP_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) arg = (reg >> SLEEP_INPUT_SHIFT) & SLEEP_INPUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) arg = reg & SLEEP_OUTPUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if ((reg & SLEEP_OUTPUT) || (reg & SLEEP_INPUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) arg = (reg >> DRIVE_STRENGTH_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DRIVE_STRENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* combine sleep pull down and pull down config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) arg = ((reg >> SLEEP_PULL_DOWN_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SLEEP_PULL_DOWN_MASK) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) arg |= (reg >> PULL_DOWN_SHIFT) & PULL_DOWN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) arg = (reg >> INPUT_SCHMITT_SHIFT) & INPUT_SCHMITT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* combine sleep pull up and pull up config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) arg = ((reg >> SLEEP_PULL_UP_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SLEEP_PULL_UP_MASK) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) arg |= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case PIN_CONFIG_SLEEP_HARDWARE_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static unsigned int sprd_pinconf_drive(unsigned int mA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) switch (mA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) val |= BIT(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) val |= BIT(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) val |= BIT(19) | BIT(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val |= BIT(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) val |= BIT(21) | BIT(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case 14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) val |= BIT(21) | BIT(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) val |= BIT(19) | BIT(20) | BIT(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case 20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val |= BIT(22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) case 21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val |= BIT(22) | BIT(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val |= BIT(22) | BIT(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case 25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) val |= BIT(22) | BIT(20) | BIT(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case 27:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) val |= BIT(22) | BIT(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case 29:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val |= BIT(22) | BIT(21) | BIT(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case 31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val |= BIT(22) | BIT(21) | BIT(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case 33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) val |= BIT(22) | BIT(21) | BIT(20) | BIT(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static bool sprd_pinctrl_check_sleep_config(unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (param == PIN_CONFIG_SLEEP_HARDWARE_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) bool is_sleep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) is_sleep_config = sprd_pinctrl_check_sleep_config(configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int param, arg, shift, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (pin->type == GLOBAL_CTRL_PIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) param == SPRD_PIN_CONFIG_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) val = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case SPRD_PIN_CONFIG_SLEEP_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (arg & AP_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) val |= AP_SLEEP_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (arg & PUBCP_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val |= PUBCP_SLEEP_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (arg & TGLDSP_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) val |= TGLDSP_SLEEP_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (arg & AGDSP_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) val |= AGDSP_SLEEP_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (arg & CM4_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) val |= CM4_SLEEP_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) mask = SLEEP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) shift = SLEEP_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (is_sleep_config == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (arg > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) val |= SLEEP_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) val &= ~SLEEP_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mask = SLEEP_INPUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) shift = SLEEP_INPUT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (is_sleep_config == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (arg > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) val |= SLEEP_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val &= ~SLEEP_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mask = SLEEP_OUTPUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) shift = SLEEP_OUTPUT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (is_sleep_config == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) val = shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mask = SLEEP_OUTPUT | SLEEP_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (arg < 2 || arg > 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) val = sprd_pinconf_drive(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) mask = DRIVE_STRENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) shift = DRIVE_STRENGTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (is_sleep_config == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) val |= SLEEP_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mask = SLEEP_PULL_DOWN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) shift = SLEEP_PULL_DOWN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val |= PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) mask = PULL_DOWN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) shift = PULL_DOWN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (arg > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) val |= INPUT_SCHMITT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) val &= ~INPUT_SCHMITT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mask = INPUT_SCHMITT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) shift = INPUT_SCHMITT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (is_sleep_config == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) val |= SLEEP_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mask = SLEEP_PULL_UP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) shift = SLEEP_PULL_UP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (arg == 20000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) val |= PULL_UP_20K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) else if (arg == 4700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) val |= PULL_UP_4_7K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) mask = PULL_UP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) shift = PULL_UP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (is_sleep_config == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) val = shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mask = SLEEP_PULL_DOWN | SLEEP_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) val = shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mask = PULL_DOWN | PULL_UP_20K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PULL_UP_4_7K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case PIN_CONFIG_SLEEP_HARDWARE_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (pin->type == GLOBAL_CTRL_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) reg = readl((void __iomem *)pin->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) reg &= ~(PINCTRL_BIT_MASK(pin->bit_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) << pin->bit_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) reg |= (val & PINCTRL_BIT_MASK(pin->bit_width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) << pin->bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) writel(reg, (void __iomem *)pin->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) reg = readl((void __iomem *)pin->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) reg &= ~(mask << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) reg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) writel(reg, (void __iomem *)pin->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int sprd_pinconf_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) unsigned int selector, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct sprd_pinctrl_soc_info *info = pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct sprd_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned int pin_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (selector >= info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) grp = &info->groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pin_id = grp->pins[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return sprd_pinconf_get(pctldev, pin_id, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int sprd_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct sprd_pinctrl_soc_info *info = pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct sprd_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (selector >= info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) grp = &info->groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unsigned int pin_id = grp->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = sprd_pinconf_set(pctldev, pin_id, configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int sprd_pinconf_get_config(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) unsigned int pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (pin->type == GLOBAL_CTRL_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *config = (readl((void __iomem *)pin->reg) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) *config = readl((void __iomem *)pin->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static void sprd_pinconf_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct seq_file *s, unsigned int pin_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) seq_printf(s, "0x%lx", config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static void sprd_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct sprd_pinctrl_soc_info *info = pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct sprd_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (selector >= info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) grp = &info->groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) seq_putc(s, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) for (i = 0; i < grp->npins; i++, config++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) unsigned int pin_id = grp->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) name = pin_get_name(pctldev, pin_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) seq_printf(s, "%s: 0x%lx ", name, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const struct pinconf_ops sprd_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .pin_config_get = sprd_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .pin_config_set = sprd_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .pin_config_group_get = sprd_pinconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .pin_config_group_set = sprd_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .pin_config_dbg_show = sprd_pinconf_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .pin_config_group_dbg_show = sprd_pinconf_group_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const struct pinconf_generic_params sprd_dt_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {"sprd,control", SPRD_PIN_CONFIG_CONTROL, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {"sprd,sleep-mode", SPRD_PIN_CONFIG_SLEEP_MODE, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct pin_config_item sprd_conf_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PCONFDUMP(SPRD_PIN_CONFIG_CONTROL, "global control", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PCONFDUMP(SPRD_PIN_CONFIG_SLEEP_MODE, "sleep mode", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct pinctrl_desc sprd_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .pctlops = &sprd_pctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .pmxops = &sprd_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .confops = &sprd_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .num_custom_params = ARRAY_SIZE(sprd_dt_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .custom_params = sprd_dt_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .custom_conf_items = sprd_conf_items,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int sprd_pinctrl_parse_groups(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct sprd_pinctrl *sprd_pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct sprd_pin_group *grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) const char *pin_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int ret, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ret = of_property_count_strings(np, "pins");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) grp->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) grp->npins = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) grp->pins = devm_kcalloc(sprd_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) grp->npins, sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!grp->pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) of_property_for_each_string(np, "pins", prop, pin_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = sprd_pinctrl_get_id_by_name(sprd_pctl, pin_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) grp->pins[i++] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_dbg(sprd_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) "Group[%s] contains [%d] pins: id = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) grp->name, grp->npins, grp->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static unsigned int sprd_pinctrl_get_groups(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) unsigned int group_cnt, cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) group_cnt = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) cnt = of_get_child_count(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (cnt > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) group_cnt += cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return group_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct device_node *np = sprd_pctl->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct device_node *child, *sub_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct sprd_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) const char **temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) info->ngroups = sprd_pinctrl_get_groups(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (!info->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) info->groups = devm_kcalloc(sprd_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) info->ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) sizeof(struct sprd_pin_group),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!info->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) info->grp_names = devm_kcalloc(sprd_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) info->ngroups, sizeof(char *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (!info->grp_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) temp = info->grp_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) grp = info->groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *temp++ = grp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) grp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (of_get_child_count(child) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) for_each_child_of_node(child, sub_child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret = sprd_pinctrl_parse_groups(sub_child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) sprd_pctl, grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) of_node_put(sub_child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) *temp++ = grp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) grp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct sprd_pins_info *sprd_soc_pin_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int pins_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) unsigned int ctrl_pin = 0, com_pin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct sprd_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) info->npins = pins_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) info->pins = devm_kcalloc(sprd_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) info->npins, sizeof(struct sprd_pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!info->pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) for (i = 0, pin = info->pins; i < info->npins; i++, pin++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pin->name = sprd_soc_pin_info[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) pin->type = sprd_soc_pin_info[i].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) pin->number = sprd_soc_pin_info[i].num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) reg = sprd_soc_pin_info[i].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (pin->type == GLOBAL_CTRL_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pin->reg = (unsigned long)sprd_pctl->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINCTRL_REG_LEN * reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) pin->bit_offset = sprd_soc_pin_info[i].bit_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pin->bit_width = sprd_soc_pin_info[i].bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ctrl_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) } else if (pin->type == COMMON_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) pin->reg = (unsigned long)sprd_pctl->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINCTRL_REG_OFFSET + PINCTRL_REG_LEN *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) (i - ctrl_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) com_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) } else if (pin->type == MISC_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) pin->reg = (unsigned long)sprd_pctl->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) (i - ctrl_pin - com_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) for (i = 0, pin = info->pins; i < info->npins; pin++, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dev_dbg(sprd_pctl->dev, "pin name[%s-%d], type = %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "bit offset = %ld, bit width = %ld, reg = 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) pin->name, pin->number, pin->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) pin->bit_offset, pin->bit_width, pin->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) int sprd_pinctrl_core_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct sprd_pins_info *sprd_soc_pin_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int pins_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct sprd_pinctrl *sprd_pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct sprd_pinctrl_soc_info *pinctrl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct pinctrl_pin_desc *pin_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (!sprd_pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) sprd_pctl->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (IS_ERR(sprd_pctl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return PTR_ERR(sprd_pctl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) pinctrl_info = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) sizeof(struct sprd_pinctrl_soc_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (!pinctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) sprd_pctl->info = pinctrl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) sprd_pctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) platform_set_drvdata(pdev, sprd_pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = sprd_pinctrl_add_pins(sprd_pctl, sprd_soc_pin_info, pins_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev_err(&pdev->dev, "fail to add pins information\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ret = sprd_pinctrl_parse_dt(sprd_pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dev_err(&pdev->dev, "fail to parse dt properties\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pin_desc = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pinctrl_info->npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) sizeof(struct pinctrl_pin_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (!pin_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) for (i = 0; i < pinctrl_info->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) pin_desc[i].number = pinctrl_info->pins[i].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pin_desc[i].name = pinctrl_info->pins[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pin_desc[i].drv_data = pinctrl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) sprd_pinctrl_desc.pins = pin_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) sprd_pinctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) sprd_pinctrl_desc.npins = pinctrl_info->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) sprd_pctl->pctl = pinctrl_register(&sprd_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) &pdev->dev, (void *)sprd_pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (IS_ERR(sprd_pctl->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dev_err(&pdev->dev, "could not register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return PTR_ERR(sprd_pctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) EXPORT_SYMBOL_GPL(sprd_pinctrl_core_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) int sprd_pinctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct sprd_pinctrl *sprd_pctl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) pinctrl_unregister(sprd_pctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) EXPORT_SYMBOL_GPL(sprd_pinctrl_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) void sprd_pinctrl_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct pinctrl *pinctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct pinctrl_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) pinctl = devm_pinctrl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (IS_ERR(pinctl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) state = pinctrl_lookup_state(pinctl, "shutdown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (IS_ERR(state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pinctrl_select_state(pinctl, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) EXPORT_SYMBOL_GPL(sprd_pinctrl_shutdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags