^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the ST Microelectronics SPEAr3xx pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pinctrl-spear3xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const struct pinctrl_pin_desc spear3xx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) SPEAR_PIN_0_TO_101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* firda_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const unsigned firda_pins[] = { 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct spear_muxreg firda_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .mask = PMX_FIRDA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .val = PMX_FIRDA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct spear_modemux firda_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .muxregs = firda_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .nmuxregs = ARRAY_SIZE(firda_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct spear_pingroup spear3xx_firda_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .name = "firda_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .pins = firda_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .npins = ARRAY_SIZE(firda_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .modemuxs = firda_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .nmodemuxs = ARRAY_SIZE(firda_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const char *const firda_grps[] = { "firda_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct spear_function spear3xx_firda_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "firda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .groups = firda_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .ngroups = ARRAY_SIZE(firda_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* i2c_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const unsigned i2c_pins[] = { 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct spear_muxreg i2c_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .mask = PMX_I2C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .val = PMX_I2C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct spear_modemux i2c_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .muxregs = i2c_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .nmuxregs = ARRAY_SIZE(i2c_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct spear_pingroup spear3xx_i2c_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .name = "i2c0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .pins = i2c_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .npins = ARRAY_SIZE(i2c_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .modemuxs = i2c_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .nmodemuxs = ARRAY_SIZE(i2c_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const char *const i2c_grps[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct spear_function spear3xx_i2c_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .groups = i2c_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .ngroups = ARRAY_SIZE(i2c_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* ssp_cs_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct spear_muxreg ssp_cs_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .mask = PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .val = PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct spear_modemux ssp_cs_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .muxregs = ssp_cs_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct spear_pingroup spear3xx_ssp_cs_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "ssp_cs_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .pins = ssp_cs_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .npins = ARRAY_SIZE(ssp_cs_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .modemuxs = ssp_cs_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct spear_function spear3xx_ssp_cs_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "ssp_cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .groups = ssp_cs_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .ngroups = ARRAY_SIZE(ssp_cs_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* ssp_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct spear_muxreg ssp_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .mask = PMX_SSP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .val = PMX_SSP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct spear_modemux ssp_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .muxregs = ssp_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .nmuxregs = ARRAY_SIZE(ssp_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct spear_pingroup spear3xx_ssp_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .name = "ssp0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .pins = ssp_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .npins = ARRAY_SIZE(ssp_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .modemuxs = ssp_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .nmodemuxs = ARRAY_SIZE(ssp_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const char *const ssp_grps[] = { "ssp0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct spear_function spear3xx_ssp_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "ssp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .groups = ssp_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .ngroups = ARRAY_SIZE(ssp_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* mii_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 21, 22, 23, 24, 25, 26, 27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct spear_muxreg mii_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .val = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct spear_modemux mii_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .muxregs = mii_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .nmuxregs = ARRAY_SIZE(mii_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct spear_pingroup spear3xx_mii_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "mii0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .pins = mii_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .npins = ARRAY_SIZE(mii_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .modemuxs = mii_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .nmodemuxs = ARRAY_SIZE(mii_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const char *const mii_grps[] = { "mii0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct spear_function spear3xx_mii_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "mii0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .groups = mii_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .ngroups = ARRAY_SIZE(mii_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* gpio0_pin0_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const unsigned gpio0_pin0_pins[] = { 28 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct spear_muxreg gpio0_pin0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .mask = PMX_GPIO_PIN0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .val = PMX_GPIO_PIN0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct spear_modemux gpio0_pin0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .muxregs = gpio0_pin0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .name = "gpio0_pin0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .pins = gpio0_pin0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .npins = ARRAY_SIZE(gpio0_pin0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .modemuxs = gpio0_pin0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* gpio0_pin1_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const unsigned gpio0_pin1_pins[] = { 29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct spear_muxreg gpio0_pin1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .mask = PMX_GPIO_PIN1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .val = PMX_GPIO_PIN1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct spear_modemux gpio0_pin1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .muxregs = gpio0_pin1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "gpio0_pin1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .pins = gpio0_pin1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .npins = ARRAY_SIZE(gpio0_pin1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .modemuxs = gpio0_pin1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* gpio0_pin2_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const unsigned gpio0_pin2_pins[] = { 30 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct spear_muxreg gpio0_pin2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .mask = PMX_GPIO_PIN2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .val = PMX_GPIO_PIN2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct spear_modemux gpio0_pin2_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .muxregs = gpio0_pin2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "gpio0_pin2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .pins = gpio0_pin2_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .npins = ARRAY_SIZE(gpio0_pin2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .modemuxs = gpio0_pin2_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* gpio0_pin3_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const unsigned gpio0_pin3_pins[] = { 31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct spear_muxreg gpio0_pin3_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .mask = PMX_GPIO_PIN3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .val = PMX_GPIO_PIN3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct spear_modemux gpio0_pin3_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .muxregs = gpio0_pin3_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .name = "gpio0_pin3_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .pins = gpio0_pin3_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .npins = ARRAY_SIZE(gpio0_pin3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .modemuxs = gpio0_pin3_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* gpio0_pin4_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const unsigned gpio0_pin4_pins[] = { 32 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct spear_muxreg gpio0_pin4_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .mask = PMX_GPIO_PIN4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .val = PMX_GPIO_PIN4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct spear_modemux gpio0_pin4_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .muxregs = gpio0_pin4_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "gpio0_pin4_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .pins = gpio0_pin4_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .npins = ARRAY_SIZE(gpio0_pin4_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .modemuxs = gpio0_pin4_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* gpio0_pin5_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const unsigned gpio0_pin5_pins[] = { 33 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct spear_muxreg gpio0_pin5_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .mask = PMX_GPIO_PIN5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .val = PMX_GPIO_PIN5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct spear_modemux gpio0_pin5_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .muxregs = gpio0_pin5_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .name = "gpio0_pin5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .pins = gpio0_pin5_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .npins = ARRAY_SIZE(gpio0_pin5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .modemuxs = gpio0_pin5_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct spear_function spear3xx_gpio0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .groups = gpio0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .ngroups = ARRAY_SIZE(gpio0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* uart0_ext_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct spear_muxreg uart0_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .val = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct spear_modemux uart0_ext_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .muxregs = uart0_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct spear_pingroup spear3xx_uart0_ext_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .name = "uart0_ext_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .pins = uart0_ext_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .npins = ARRAY_SIZE(uart0_ext_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .modemuxs = uart0_ext_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct spear_function spear3xx_uart0_ext_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "uart0_ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .groups = uart0_ext_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .ngroups = ARRAY_SIZE(uart0_ext_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* uart0_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const unsigned uart0_pins[] = { 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct spear_muxreg uart0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .mask = PMX_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .val = PMX_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct spear_modemux uart0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .muxregs = uart0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .nmuxregs = ARRAY_SIZE(uart0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct spear_pingroup spear3xx_uart0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .name = "uart0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .pins = uart0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .npins = ARRAY_SIZE(uart0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .modemuxs = uart0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .nmodemuxs = ARRAY_SIZE(uart0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const char *const uart0_grps[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct spear_function spear3xx_uart0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .name = "uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .groups = uart0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .ngroups = ARRAY_SIZE(uart0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* timer_0_1_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static struct spear_muxreg timer_0_1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .mask = PMX_TIMER_0_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .val = PMX_TIMER_0_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct spear_modemux timer_0_1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .muxregs = timer_0_1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct spear_pingroup spear3xx_timer_0_1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .name = "timer_0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .pins = timer_0_1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .npins = ARRAY_SIZE(timer_0_1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .modemuxs = timer_0_1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct spear_function spear3xx_timer_0_1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .name = "timer_0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .groups = timer_0_1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .ngroups = ARRAY_SIZE(timer_0_1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* timer_2_3_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct spear_muxreg timer_2_3_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .reg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .mask = PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .val = PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct spear_modemux timer_2_3_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .modes = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .muxregs = timer_2_3_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct spear_pingroup spear3xx_timer_2_3_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .name = "timer_2_3_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .pins = timer_2_3_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .npins = ARRAY_SIZE(timer_2_3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .modemuxs = timer_2_3_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct spear_function spear3xx_timer_2_3_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "timer_2_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .groups = timer_2_3_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .ngroups = ARRAY_SIZE(timer_2_3_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Define muxreg arrays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DEFINE_MUXREG(firda_pins, 0, PMX_FIRDA_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DEFINE_MUXREG(i2c_pins, 0, PMX_I2C_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DEFINE_MUXREG(ssp_cs_pins, 0, PMX_SSP_CS_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DEFINE_MUXREG(ssp_pins, 0, PMX_SSP_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) DEFINE_MUXREG(mii_pins, 0, PMX_MII_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DEFINE_MUXREG(gpio0_pin0_pins, 0, PMX_GPIO_PIN0_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DEFINE_MUXREG(gpio0_pin1_pins, 0, PMX_GPIO_PIN1_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) DEFINE_MUXREG(gpio0_pin2_pins, 0, PMX_GPIO_PIN2_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DEFINE_MUXREG(gpio0_pin3_pins, 0, PMX_GPIO_PIN3_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DEFINE_MUXREG(gpio0_pin4_pins, 0, PMX_GPIO_PIN4_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) DEFINE_MUXREG(gpio0_pin5_pins, 0, PMX_GPIO_PIN5_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DEFINE_MUXREG(uart0_ext_pins, 0, PMX_UART0_MODEM_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) DEFINE_MUXREG(uart0_pins, 0, PMX_UART0_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) DEFINE_MUXREG(timer_0_1_pins, 0, PMX_TIMER_0_1_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DEFINE_MUXREG(timer_2_3_pins, 0, PMX_TIMER_2_3_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static struct spear_gpio_pingroup spear3xx_gpio_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) GPIO_PINGROUP(firda_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) GPIO_PINGROUP(i2c_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GPIO_PINGROUP(ssp_cs_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GPIO_PINGROUP(ssp_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GPIO_PINGROUP(mii_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GPIO_PINGROUP(gpio0_pin0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GPIO_PINGROUP(gpio0_pin1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GPIO_PINGROUP(gpio0_pin2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GPIO_PINGROUP(gpio0_pin3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GPIO_PINGROUP(gpio0_pin4_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GPIO_PINGROUP(gpio0_pin5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GPIO_PINGROUP(uart0_ext_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GPIO_PINGROUP(uart0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GPIO_PINGROUP(timer_0_1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GPIO_PINGROUP(timer_2_3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct spear_pinctrl_machdata spear3xx_machdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .pins = spear3xx_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .npins = ARRAY_SIZE(spear3xx_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .gpio_pingroups = spear3xx_gpio_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .ngpio_pingroups = ARRAY_SIZE(spear3xx_gpio_pingroup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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