^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the ST Microelectronics SPEAr320 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-spear3xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRIVER_NAME "spear320-pinmux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PMX_CONFIG_REG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MODE_CONFIG_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MODE_EXT_CONFIG_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AUTO_NET_SMII_MODE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AUTO_NET_MII_MODE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AUTO_EXP_MODE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SMALL_PRINTERS_MODE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EXTENDED_MODE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct spear_pmx_mode pmx_mode_auto_net_smii = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .name = "Automation Networking SMII mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .mode = AUTO_NET_SMII_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .mask = 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .val = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct spear_pmx_mode pmx_mode_auto_net_mii = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = "Automation Networking MII mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .mode = AUTO_NET_MII_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .mask = 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .val = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct spear_pmx_mode pmx_mode_auto_exp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "Automation Expanded mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .mode = AUTO_EXP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .mask = 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .val = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct spear_pmx_mode pmx_mode_small_printers = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .name = "Small Printers mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .mode = SMALL_PRINTERS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .mask = 0x00000007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .val = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct spear_pmx_mode pmx_mode_extended = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = "extended mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .mode = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .reg = MODE_EXT_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .mask = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .val = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct spear_pmx_mode *spear320_pmx_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) &pmx_mode_auto_net_smii,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) &pmx_mode_auto_net_mii,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &pmx_mode_auto_exp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) &pmx_mode_small_printers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) &pmx_mode_extended,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Extended mode registers and their offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EXT_CTRL_REG 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MII_MDIO_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MII_MDIO_10_11_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MII_MDIO_81_VAL (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MAC_MODE_MII 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MAC_MODE_RMII 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MAC_MODE_SMII 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MAC_MODE_SS_SMII 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MAC_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAC1_MODE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MAC2_MODE_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IP_SEL_PAD_0_9_REG 0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PMX_PL_0_1_MASK (0x3F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PMX_UART2_PL_0_1_VAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PMX_PL_2_3_MASK (0x3F << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PMX_I2C2_PL_2_3_VAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PMX_PL_4_5_MASK (0x3F << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PMX_PL_5_MASK (0x7 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PMX_TOUCH_Y_PL_5_VAL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PMX_PL_6_7_MASK (0x3F << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PMX_PL_6_MASK (0x7 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PMX_PL_7_MASK (0x7 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PMX_PL_8_9_MASK (0x3F << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IP_SEL_PAD_10_19_REG 0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PMX_PL_10_11_MASK (0x3F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PMX_SMII_PL_10_11_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PMX_PL_12_MASK (0x7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PMX_PWM3_PL_12_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PMX_PL_13_14_MASK (0x3F << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PMX_PL_13_MASK (0x7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PMX_PL_14_MASK (0x7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PMX_SSP2_PL_13_14_15_16_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PMX_PWM2_PL_13_VAL (0x2 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PMX_PWM1_PL_14_VAL (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PMX_PL_15_MASK (0x7 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PMX_PWM0_PL_15_VAL (0x2 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PMX_PL_15_16_MASK (0x3F << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PMX_PL_17_18_MASK (0x3F << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PMX_SSP1_PL_17_18_19_20_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PMX_PL_19_MASK (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PMX_I2C2_PL_19_VAL (0x1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PMX_RMII_PL_19_VAL (0x4 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IP_SEL_PAD_20_29_REG 0x00AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PMX_PL_20_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PMX_I2C2_PL_20_VAL (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PMX_RMII_PL_20_VAL (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PMX_SMII_PL_21_TO_27_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PMX_PL_28_29_MASK (0x3F << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PMX_PL_28_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PMX_PL_29_MASK (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PMX_UART1_PL_28_29_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PMX_PWM_3_PL_28_VAL (0x4 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PMX_PWM_2_PL_29_VAL (0x4 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IP_SEL_PAD_30_39_REG 0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PMX_PL_30_31_MASK (0x3F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PMX_CAN1_PL_30_31_VAL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PMX_PL_30_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PMX_PL_31_MASK (0x7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PMX_PL_32_33_MASK (0x3F << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PMX_CAN0_PL_32_33_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PMX_PL_34_MASK (0x7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PMX_PWM2_PL_34_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PMX_SSP2_PL_34_VAL (0x4 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PMX_PL_35_MASK (0x7 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PMX_I2S_REF_CLK_PL_35_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PMX_SSP2_PL_35_VAL (0x4 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PMX_PL_36_MASK (0x7 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PMX_TOUCH_X_PL_36_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PMX_SSP1_PL_36_VAL (0x4 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PMX_PL_37_38_MASK (0x3F << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PMX_PWM0_1_PL_37_38_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PMX_PL_39_MASK (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PMX_I2S_PL_39_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PMX_UART4_PL_39_VAL (0x2 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PMX_SSP1_PL_39_VAL (0x4 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IP_SEL_PAD_40_49_REG 0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PMX_PL_40_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PMX_I2S_PL_40_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PMX_UART4_PL_40_VAL (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PMX_PWM3_PL_40_VAL (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PMX_PL_41_42_MASK (0x3F << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PMX_PL_41_MASK (0x7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PMX_PL_42_MASK (0x7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PMX_I2S_PL_41_42_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PMX_PWM2_PL_41_VAL (0x4 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PMX_PWM1_PL_42_VAL (0x4 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PMX_PL_43_MASK (0x7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PMX_SDHCI_PL_43_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PMX_PWM0_PL_43_VAL (0x4 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PMX_PL_44_45_MASK (0x3F << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PMX_SDHCI_PL_44_45_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PMX_PL_46_47_MASK (0x3F << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PMX_SDHCI_PL_46_47_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PMX_PL_48_49_MASK (0x3F << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PMX_SDHCI_PL_48_49_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IP_SEL_PAD_50_59_REG 0x00B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PMX_PL_50_51_MASK (0x3F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PMX_PL_50_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PMX_PL_51_MASK (0x7 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PMX_SDHCI_PL_50_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PMX_SDHCI_CD_PL_51_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PMX_PL_52_53_MASK (0x3F << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PMX_FSMC_PL_52_53_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PMX_PL_54_55_56_MASK (0x1FF << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define PMX_PL_57_MASK (0x7 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PMX_FSMC_PL_57_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PMX_PWM3_PL_57_VAL (0x4 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PMX_PL_58_59_MASK (0x3F << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PMX_PL_58_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PMX_PL_59_MASK (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define PMX_PWM2_PL_58_VAL (0x4 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define PMX_PWM1_PL_59_VAL (0x4 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IP_SEL_PAD_60_69_REG 0x00BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PMX_PL_60_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define PMX_FSMC_PL_60_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PMX_PWM0_PL_60_VAL (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PMX_PL_61_TO_64_MASK (0xFFF << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PMX_PL_65_TO_68_MASK (0xFFF << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PMX_PL_69_MASK (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PMX_CLCD_PL_69_VAL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PMX_EMI_PL_69_VAL (0x2 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PMX_SPP_PL_69_VAL (0x3 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PMX_UART5_PL_69_VAL (0x4 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IP_SEL_PAD_70_79_REG 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define PMX_PL_70_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PMX_CLCD_PL_70_VAL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define PMX_SPP_PL_70_VAL (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define PMX_UART5_PL_70_VAL (0x4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define PMX_PL_71_72_MASK (0x3F << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PMX_CLCD_PL_71_72_VAL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define PMX_PL_73_MASK (0x7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define PMX_CLCD_PL_73_VAL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define PMX_SPP_PL_73_VAL (0x3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define PMX_UART3_PL_73_VAL (0x4 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define PMX_PL_74_MASK (0x7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define PMX_CLCD_PL_74_VAL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define PMX_EMI_PL_74_VAL (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define PMX_SPP_PL_74_VAL (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PMX_UART3_PL_74_VAL (0x4 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define PMX_PL_75_76_MASK (0x3F << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define PMX_CLCD_PL_75_76_VAL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define PMX_PL_77_78_79_MASK (0x1FF << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define PMX_CLCD_PL_77_78_79_VAL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IP_SEL_PAD_80_89_REG 0x00C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PMX_CLCD_PL_80_TO_85_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define PMX_PL_86_87_MASK (0x3F << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define PMX_PL_86_MASK (0x7 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PMX_PL_87_MASK (0x7 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define PMX_CLCD_PL_86_87_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define PMX_PWM3_PL_86_VAL (0x4 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define PMX_PWM2_PL_87_VAL (0x4 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PMX_PL_88_89_MASK (0x3F << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PMX_CLCD_PL_88_89_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IP_SEL_PAD_90_99_REG 0x00C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PMX_PL_90_91_MASK (0x3F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define PMX_CLCD_PL_90_91_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PMX_PL_92_93_MASK (0x3F << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define PMX_CLCD_PL_92_93_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PMX_PL_94_95_MASK (0x3F << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define PMX_CLCD_PL_94_95_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PMX_PL_96_97_MASK (0x3F << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PMX_CLCD_PL_96_97_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PMX_PL_98_MASK (0x7 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PMX_CLCD_PL_98_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define PMX_I2C1_PL_98_VAL (0x2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PMX_UART3_PL_98_VAL (0x4 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define PMX_PL_99_MASK (0x7 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PMX_SDHCI_PL_99_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PMX_I2C1_PL_99_VAL (0x2 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PMX_UART3_PL_99_VAL (0x4 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IP_SEL_MIX_PAD_REG 0x00CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PMX_PL_100_101_MASK (0x3F << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define PMX_SDHCI_PL_100_101_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define PMX_SSP1_PORT_94_TO_97_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PMX_SSP2_PORT_90_TO_93_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PMX_UART3_PORT_94_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PMX_UART3_PORT_73_VAL (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PMX_UART3_PORT_52_VAL (0x2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PMX_UART3_PORT_41_VAL (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PMX_UART3_PORT_15_VAL (0x4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PMX_UART3_PORT_8_VAL (0x5 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PMX_UART3_PORT_99_VAL (0x6 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define PMX_UART4_PORT_92_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PMX_UART4_PORT_71_VAL (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PMX_UART4_PORT_39_VAL (0x2 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PMX_UART4_PORT_13_VAL (0x3 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PMX_UART4_PORT_6_VAL (0x4 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PMX_UART4_PORT_101_VAL (0x5 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PMX_UART5_PORT_90_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PMX_UART5_PORT_69_VAL (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PMX_UART5_PORT_37_VAL (0x2 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PMX_UART5_PORT_4_VAL (0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PMX_UART6_PORT_88_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define PMX_UART6_PORT_2_VAL (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PMX_I2C1_PORT_8_9_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PMX_I2C2_PORT_96_97_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define PMX_SDHCI_CD_PORT_12_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Pad multiplexing for CLCD device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct spear_muxreg clcd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .reg = IP_SEL_PAD_60_69_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .mask = PMX_PL_69_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .val = PMX_CLCD_PL_69_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .reg = IP_SEL_PAD_70_79_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PMX_PL_74_MASK | PMX_PL_75_76_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PMX_PL_77_78_79_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .reg = IP_SEL_PAD_80_89_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PMX_PL_88_89_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PMX_CLCD_PL_88_89_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PMX_CLCD_PL_98_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct spear_modemux clcd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .muxregs = clcd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .nmuxregs = ARRAY_SIZE(clcd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct spear_pingroup clcd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .name = "clcd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .pins = clcd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .npins = ARRAY_SIZE(clcd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .modemuxs = clcd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .nmodemuxs = ARRAY_SIZE(clcd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const char *const clcd_grps[] = { "clcd_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static struct spear_function clcd_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .name = "clcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .groups = clcd_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .ngroups = ARRAY_SIZE(clcd_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Pad multiplexing for EMI (Parallel NOR flash) device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 93, 94, 95, 96, 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct spear_muxreg emi_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static struct spear_muxreg emi_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .reg = IP_SEL_PAD_50_59_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PMX_FSMC_EMI_PL_54_55_56_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PMX_FSMC_EMI_PL_58_59_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .reg = IP_SEL_PAD_60_69_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .mask = PMX_PL_69_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .val = PMX_EMI_PL_69_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .reg = IP_SEL_PAD_70_79_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PMX_PL_74_MASK | PMX_PL_75_76_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PMX_PL_77_78_79_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .reg = IP_SEL_PAD_80_89_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PMX_PL_88_89_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PMX_EMI_PL_88_89_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .reg = EXT_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .val = EMI_FSMC_DYNAMIC_MUX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static struct spear_modemux emi_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .modes = AUTO_EXP_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .muxregs = emi_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .nmuxregs = ARRAY_SIZE(emi_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .muxregs = emi_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static struct spear_pingroup emi_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .name = "emi_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .pins = emi_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .npins = ARRAY_SIZE(emi_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .modemuxs = emi_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .nmodemuxs = ARRAY_SIZE(emi_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const char *const emi_grps[] = { "emi_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static struct spear_function emi_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .name = "emi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .groups = emi_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .ngroups = ARRAY_SIZE(emi_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Pad multiplexing for FSMC (NAND flash) device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 61, 62, 63, 64, 65, 66, 67, 68 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct spear_muxreg fsmc_8bit_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .reg = IP_SEL_PAD_50_59_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PMX_PL_57_MASK | PMX_PL_58_59_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .reg = IP_SEL_PAD_60_69_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PMX_PL_65_TO_68_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PMX_FSMC_PL_65_TO_68_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .reg = EXT_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .val = EMI_FSMC_DYNAMIC_MUX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static struct spear_modemux fsmc_8bit_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .muxregs = fsmc_8bit_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static struct spear_pingroup fsmc_8bit_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .name = "fsmc_8bit_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .pins = fsmc_8bit_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .npins = ARRAY_SIZE(fsmc_8bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .modemuxs = fsmc_8bit_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct spear_muxreg fsmc_16bit_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .reg = IP_SEL_PAD_70_79_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PMX_FSMC_EMI_PL_73_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static struct spear_modemux fsmc_16bit_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .muxregs = fsmc_8bit_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .modes = AUTO_EXP_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .muxregs = fsmc_16bit_autoexp_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .muxregs = fsmc_16bit_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static struct spear_pingroup fsmc_16bit_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .name = "fsmc_16bit_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .pins = fsmc_16bit_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .npins = ARRAY_SIZE(fsmc_16bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .modemuxs = fsmc_16bit_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static struct spear_function fsmc_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .name = "fsmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .groups = fsmc_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .ngroups = ARRAY_SIZE(fsmc_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Pad multiplexing for SPP device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 80, 81, 82, 83, 84, 85 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static struct spear_muxreg spp_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .reg = IP_SEL_PAD_60_69_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .mask = PMX_PL_69_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .val = PMX_SPP_PL_69_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .reg = IP_SEL_PAD_70_79_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PMX_PL_74_MASK | PMX_PL_75_76_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PMX_PL_77_78_79_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .reg = IP_SEL_PAD_80_89_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .mask = PMX_PL_80_TO_85_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .val = PMX_SPP_PL_80_TO_85_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static struct spear_modemux spp_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .muxregs = spp_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .nmuxregs = ARRAY_SIZE(spp_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static struct spear_pingroup spp_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .name = "spp_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .pins = spp_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .npins = ARRAY_SIZE(spp_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .modemuxs = spp_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .nmodemuxs = ARRAY_SIZE(spp_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const char *const spp_grps[] = { "spp_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static struct spear_function spp_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .name = "spp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .groups = spp_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .ngroups = ARRAY_SIZE(spp_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Pad multiplexing for SDHCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const unsigned sdhci_led_pins[] = { 34 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static struct spear_muxreg sdhci_led_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .mask = PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static struct spear_muxreg sdhci_led_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .mask = PMX_PL_34_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .val = PMX_PWM2_PL_34_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct spear_modemux sdhci_led_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .muxregs = sdhci_led_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .muxregs = sdhci_led_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static struct spear_pingroup sdhci_led_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .name = "sdhci_led_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .pins = sdhci_led_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .npins = ARRAY_SIZE(sdhci_led_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .modemuxs = sdhci_led_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 50};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static struct spear_muxreg sdhci_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static struct spear_muxreg sdhci_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PMX_PL_48_49_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .reg = IP_SEL_PAD_50_59_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .mask = PMX_PL_50_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .val = PMX_SDHCI_PL_50_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .mask = PMX_PL_99_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .val = PMX_SDHCI_PL_99_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .mask = PMX_PL_100_101_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .val = PMX_SDHCI_PL_100_101_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static struct spear_muxreg sdhci_cd_12_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .mask = PMX_PL_12_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .val = PMX_SDHCI_CD_PL_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .val = PMX_SDHCI_CD_PORT_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static struct spear_muxreg sdhci_cd_51_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .reg = IP_SEL_PAD_50_59_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .mask = PMX_PL_51_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .val = PMX_SDHCI_CD_PL_51_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .val = PMX_SDHCI_CD_PORT_51_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define pmx_sdhci_common_modemux \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SMALL_PRINTERS_MODE | EXTENDED_MODE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .muxregs = sdhci_muxreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }, { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .modes = EXTENDED_MODE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .muxregs = sdhci_ext_muxreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static struct spear_modemux sdhci_modemux[][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* select pin 12 for cd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pmx_sdhci_common_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .muxregs = sdhci_cd_12_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* select pin 51 for cd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pmx_sdhci_common_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .muxregs = sdhci_cd_51_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct spear_pingroup sdhci_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .name = "sdhci_cd_12_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .pins = sdhci_cd_12_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .npins = ARRAY_SIZE(sdhci_cd_12_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .modemuxs = sdhci_modemux[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .name = "sdhci_cd_51_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .pins = sdhci_cd_51_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .npins = ARRAY_SIZE(sdhci_cd_51_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .modemuxs = sdhci_modemux[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "sdhci_led_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static struct spear_function sdhci_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .name = "sdhci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .groups = sdhci_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .ngroups = ARRAY_SIZE(sdhci_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* Pad multiplexing for I2S device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static struct spear_muxreg i2s_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .mask = PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static struct spear_muxreg i2s_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static struct spear_modemux i2s_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .muxregs = i2s_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .nmuxregs = ARRAY_SIZE(i2s_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .muxregs = i2s_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static struct spear_pingroup i2s_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .name = "i2s_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .pins = i2s_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .npins = ARRAY_SIZE(i2s_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .modemuxs = i2s_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .nmodemuxs = ARRAY_SIZE(i2s_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const char *const i2s_grps[] = { "i2s_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static struct spear_function i2s_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .name = "i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .groups = i2s_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .ngroups = ARRAY_SIZE(i2s_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Pad multiplexing for UART1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const unsigned uart1_pins[] = { 28, 29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static struct spear_muxreg uart1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static struct spear_muxreg uart1_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .reg = IP_SEL_PAD_20_29_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .mask = PMX_PL_28_29_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .val = PMX_UART1_PL_28_29_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static struct spear_modemux uart1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) | SMALL_PRINTERS_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .muxregs = uart1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .nmuxregs = ARRAY_SIZE(uart1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .muxregs = uart1_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static struct spear_pingroup uart1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .name = "uart1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .pins = uart1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .npins = ARRAY_SIZE(uart1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .modemuxs = uart1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .nmodemuxs = ARRAY_SIZE(uart1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const char *const uart1_grps[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static struct spear_function uart1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .name = "uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .groups = uart1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .ngroups = ARRAY_SIZE(uart1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* Pad multiplexing for UART1 Modem device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PMX_UART1_ENH_PL_6_7_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .mask = PMX_UART1_ENH_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PMX_PL_35_MASK | PMX_PL_36_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PMX_UART1_ENH_PL_36_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .mask = PMX_UART1_ENH_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PMX_UART1_ENH_PL_36_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .mask = PMX_UART1_ENH_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .reg = IP_SEL_PAD_80_89_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .mask = PMX_PL_80_TO_85_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .mask = PMX_UART1_ENH_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .muxregs = uart1_modem_ext_2_to_7_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .muxregs = uart1_modem_31_to_36_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .muxregs = uart1_modem_ext_31_to_36_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .modes = AUTO_EXP_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .muxregs = uart1_modem_34_to_45_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .muxregs = uart1_modem_ext_34_to_45_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .muxregs = uart1_modem_ext_80_to_85_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static struct spear_pingroup uart1_modem_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .name = "uart1_modem_2_to_7_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .pins = uart1_modem_2_to_7_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .modemuxs = uart1_modem_2_to_7_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .name = "uart1_modem_31_to_36_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .pins = uart1_modem_31_to_36_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .modemuxs = uart1_modem_31_to_36_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .name = "uart1_modem_34_to_45_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .pins = uart1_modem_34_to_45_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .modemuxs = uart1_modem_34_to_45_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .name = "uart1_modem_80_to_85_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .pins = uart1_modem_80_to_85_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .modemuxs = uart1_modem_80_to_85_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "uart1_modem_80_to_85_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static struct spear_function uart1_modem_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .name = "uart1_modem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .groups = uart1_modem_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .ngroups = ARRAY_SIZE(uart1_modem_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Pad multiplexing for UART2 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static const unsigned uart2_pins[] = { 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static struct spear_muxreg uart2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .mask = PMX_FIRDA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static struct spear_muxreg uart2_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .mask = PMX_PL_0_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .val = PMX_UART2_PL_0_1_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static struct spear_modemux uart2_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) | SMALL_PRINTERS_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .muxregs = uart2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .nmuxregs = ARRAY_SIZE(uart2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .muxregs = uart2_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static struct spear_pingroup uart2_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .name = "uart2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .pins = uart2_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .npins = ARRAY_SIZE(uart2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .modemuxs = uart2_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .nmodemuxs = ARRAY_SIZE(uart2_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static const char *const uart2_grps[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static struct spear_function uart2_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .name = "uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .groups = uart2_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .ngroups = ARRAY_SIZE(uart2_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* Pad multiplexing for uart3 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .mask = PMX_SSP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .mask = PMX_PL_8_9_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .val = PMX_UART3_PL_8_9_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .mask = PMX_UART3_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .val = PMX_UART3_PORT_8_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .mask = PMX_PL_15_16_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .val = PMX_UART3_PL_15_16_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .mask = PMX_UART3_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .val = PMX_UART3_PORT_15_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .mask = PMX_PL_41_42_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .val = PMX_UART3_PL_41_42_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .mask = PMX_UART3_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .val = PMX_UART3_PORT_41_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .reg = IP_SEL_PAD_50_59_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .mask = PMX_PL_52_53_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .val = PMX_UART3_PL_52_53_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .mask = PMX_UART3_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .val = PMX_UART3_PORT_52_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .reg = IP_SEL_PAD_70_79_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .mask = PMX_UART3_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .val = PMX_UART3_PORT_73_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .mask = PMX_PL_94_95_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .val = PMX_UART3_PL_94_95_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .mask = PMX_UART3_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .val = PMX_UART3_PORT_94_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .mask = PMX_UART3_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .val = PMX_UART3_PORT_99_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static struct spear_modemux uart3_modemux[][1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* Select signals on pins 8_9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .muxregs = uart3_ext_8_9_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* Select signals on pins 15_16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .muxregs = uart3_ext_15_16_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* Select signals on pins 41_42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .muxregs = uart3_ext_41_42_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* Select signals on pins 52_53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .muxregs = uart3_ext_52_53_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* Select signals on pins 73_74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .muxregs = uart3_ext_73_74_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* Select signals on pins 94_95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .muxregs = uart3_ext_94_95_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* Select signals on pins 98_99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .muxregs = uart3_ext_98_99_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) static struct spear_pingroup uart3_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .name = "uart3_8_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .pins = uart3_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .npins = ARRAY_SIZE(uart3_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .modemuxs = uart3_modemux[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .name = "uart3_15_16_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .pins = uart3_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .npins = ARRAY_SIZE(uart3_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .modemuxs = uart3_modemux[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .name = "uart3_41_42_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .pins = uart3_pins[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .npins = ARRAY_SIZE(uart3_pins[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .modemuxs = uart3_modemux[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .name = "uart3_52_53_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .pins = uart3_pins[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .npins = ARRAY_SIZE(uart3_pins[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .modemuxs = uart3_modemux[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .name = "uart3_73_74_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .pins = uart3_pins[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .npins = ARRAY_SIZE(uart3_pins[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .modemuxs = uart3_modemux[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .name = "uart3_94_95_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .pins = uart3_pins[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .npins = ARRAY_SIZE(uart3_pins[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .modemuxs = uart3_modemux[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .name = "uart3_98_99_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .pins = uart3_pins[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .npins = ARRAY_SIZE(uart3_pins[6]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .modemuxs = uart3_modemux[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) "uart3_94_95_grp", "uart3_98_99_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static struct spear_function uart3_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .name = "uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .groups = uart3_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .ngroups = ARRAY_SIZE(uart3_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* Pad multiplexing for uart4 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) { 71, 72 }, { 92, 93 }, { 100, 101 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .mask = PMX_SSP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .mask = PMX_PL_6_7_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .val = PMX_UART4_PL_6_7_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .mask = PMX_UART4_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .val = PMX_UART4_PORT_6_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .mask = PMX_PL_13_14_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .val = PMX_UART4_PL_13_14_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .mask = PMX_UART4_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .val = PMX_UART4_PORT_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .mask = PMX_PL_39_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .val = PMX_UART4_PL_39_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .mask = PMX_PL_40_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .val = PMX_UART4_PL_40_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .mask = PMX_UART4_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .val = PMX_UART4_PORT_39_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .reg = IP_SEL_PAD_70_79_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .mask = PMX_PL_71_72_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .val = PMX_UART4_PL_71_72_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .mask = PMX_UART4_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .val = PMX_UART4_PORT_71_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .mask = PMX_PL_92_93_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .val = PMX_UART4_PL_92_93_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .mask = PMX_UART4_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .val = PMX_UART4_PORT_92_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .mask = PMX_PL_100_101_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) PMX_UART4_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .val = PMX_UART4_PL_100_101_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) PMX_UART4_PORT_101_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static struct spear_modemux uart4_modemux[][1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* Select signals on pins 6_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .muxregs = uart4_ext_6_7_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* Select signals on pins 13_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .muxregs = uart4_ext_13_14_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) /* Select signals on pins 39_40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .muxregs = uart4_ext_39_40_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) /* Select signals on pins 71_72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .muxregs = uart4_ext_71_72_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* Select signals on pins 92_93 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .muxregs = uart4_ext_92_93_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* Select signals on pins 100_101_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .muxregs = uart4_ext_100_101_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static struct spear_pingroup uart4_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .name = "uart4_6_7_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .pins = uart4_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .npins = ARRAY_SIZE(uart4_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .modemuxs = uart4_modemux[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .name = "uart4_13_14_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .pins = uart4_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .npins = ARRAY_SIZE(uart4_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .modemuxs = uart4_modemux[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .name = "uart4_39_40_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .pins = uart4_pins[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .npins = ARRAY_SIZE(uart4_pins[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .modemuxs = uart4_modemux[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .name = "uart4_71_72_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .pins = uart4_pins[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .npins = ARRAY_SIZE(uart4_pins[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .modemuxs = uart4_modemux[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .name = "uart4_92_93_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .pins = uart4_pins[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .npins = ARRAY_SIZE(uart4_pins[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .modemuxs = uart4_modemux[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .name = "uart4_100_101_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .pins = uart4_pins[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .npins = ARRAY_SIZE(uart4_pins[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .modemuxs = uart4_modemux[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) "uart4_100_101_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static struct spear_function uart4_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .name = "uart4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .groups = uart4_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .ngroups = ARRAY_SIZE(uart4_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* Pad multiplexing for uart5 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) { 90, 91 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .mask = PMX_I2C_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .mask = PMX_PL_4_5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .val = PMX_UART5_PL_4_5_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .mask = PMX_UART5_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .val = PMX_UART5_PORT_4_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .mask = PMX_PL_37_38_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .val = PMX_UART5_PL_37_38_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .mask = PMX_UART5_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .val = PMX_UART5_PORT_37_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .reg = IP_SEL_PAD_60_69_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .mask = PMX_PL_69_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .val = PMX_UART5_PL_69_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .reg = IP_SEL_PAD_70_79_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .mask = PMX_PL_70_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .val = PMX_UART5_PL_70_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .mask = PMX_UART5_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .val = PMX_UART5_PORT_69_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .mask = PMX_PL_90_91_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .val = PMX_UART5_PL_90_91_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .mask = PMX_UART5_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .val = PMX_UART5_PORT_90_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static struct spear_modemux uart5_modemux[][1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* Select signals on pins 4_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .muxregs = uart5_ext_4_5_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* Select signals on pins 37_38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .muxregs = uart5_ext_37_38_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* Select signals on pins 69_70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .muxregs = uart5_ext_69_70_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /* Select signals on pins 90_91 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .muxregs = uart5_ext_90_91_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) static struct spear_pingroup uart5_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .name = "uart5_4_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .pins = uart5_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .npins = ARRAY_SIZE(uart5_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .modemuxs = uart5_modemux[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .name = "uart5_37_38_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .pins = uart5_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .npins = ARRAY_SIZE(uart5_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .modemuxs = uart5_modemux[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .name = "uart5_69_70_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .pins = uart5_pins[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .npins = ARRAY_SIZE(uart5_pins[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .modemuxs = uart5_modemux[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .name = "uart5_90_91_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .pins = uart5_pins[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .npins = ARRAY_SIZE(uart5_pins[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .modemuxs = uart5_modemux[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) "uart5_69_70_grp", "uart5_90_91_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static struct spear_function uart5_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .name = "uart5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .groups = uart5_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .ngroups = ARRAY_SIZE(uart5_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /* Pad multiplexing for uart6 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .mask = PMX_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .mask = PMX_PL_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .val = PMX_UART6_PL_2_3_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .mask = PMX_UART6_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .val = PMX_UART6_PORT_2_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .reg = IP_SEL_PAD_80_89_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .mask = PMX_PL_88_89_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .val = PMX_UART6_PL_88_89_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .mask = PMX_UART6_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .val = PMX_UART6_PORT_88_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static struct spear_modemux uart6_modemux[][1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* Select signals on pins 2_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .muxregs = uart6_ext_2_3_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* Select signals on pins 88_89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .muxregs = uart6_ext_88_89_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static struct spear_pingroup uart6_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .name = "uart6_2_3_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .pins = uart6_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .npins = ARRAY_SIZE(uart6_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .modemuxs = uart6_modemux[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .name = "uart6_88_89_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .pins = uart6_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .npins = ARRAY_SIZE(uart6_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .modemuxs = uart6_modemux[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static struct spear_function uart6_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .name = "uart6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .groups = uart6_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .ngroups = ARRAY_SIZE(uart6_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* UART - RS485 pmx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static const unsigned rs485_pins[] = { 77, 78, 79 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static struct spear_muxreg rs485_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .reg = IP_SEL_PAD_70_79_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .mask = PMX_PL_77_78_79_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .val = PMX_RS485_PL_77_78_79_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) static struct spear_modemux rs485_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .muxregs = rs485_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .nmuxregs = ARRAY_SIZE(rs485_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static struct spear_pingroup rs485_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .name = "rs485_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .pins = rs485_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .npins = ARRAY_SIZE(rs485_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .modemuxs = rs485_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .nmodemuxs = ARRAY_SIZE(rs485_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static const char *const rs485_grps[] = { "rs485_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static struct spear_function rs485_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .name = "rs485",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .groups = rs485_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .ngroups = ARRAY_SIZE(rs485_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* Pad multiplexing for Touchscreen device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static const unsigned touchscreen_pins[] = { 5, 36 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) static struct spear_muxreg touchscreen_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static struct spear_muxreg touchscreen_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .mask = PMX_PL_5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .val = PMX_TOUCH_Y_PL_5_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .mask = PMX_PL_36_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .val = PMX_TOUCH_X_PL_36_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static struct spear_modemux touchscreen_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .muxregs = touchscreen_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .muxregs = touchscreen_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static struct spear_pingroup touchscreen_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .name = "touchscreen_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .pins = touchscreen_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .npins = ARRAY_SIZE(touchscreen_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .modemuxs = touchscreen_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static const char *const touchscreen_grps[] = { "touchscreen_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static struct spear_function touchscreen_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .name = "touchscreen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .groups = touchscreen_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .ngroups = ARRAY_SIZE(touchscreen_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* Pad multiplexing for CAN device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static const unsigned can0_pins[] = { 32, 33 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static struct spear_muxreg can0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static struct spear_muxreg can0_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .mask = PMX_PL_32_33_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .val = PMX_CAN0_PL_32_33_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static struct spear_modemux can0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .muxregs = can0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .nmuxregs = ARRAY_SIZE(can0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .muxregs = can0_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static struct spear_pingroup can0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .name = "can0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .pins = can0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .npins = ARRAY_SIZE(can0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .modemuxs = can0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .nmodemuxs = ARRAY_SIZE(can0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static const char *const can0_grps[] = { "can0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static struct spear_function can0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .name = "can0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .groups = can0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .ngroups = ARRAY_SIZE(can0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static const unsigned can1_pins[] = { 30, 31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static struct spear_muxreg can1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) static struct spear_muxreg can1_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .mask = PMX_PL_30_31_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .val = PMX_CAN1_PL_30_31_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static struct spear_modemux can1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .muxregs = can1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .nmuxregs = ARRAY_SIZE(can1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .muxregs = can1_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static struct spear_pingroup can1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .name = "can1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .pins = can1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .npins = ARRAY_SIZE(can1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .modemuxs = can1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .nmodemuxs = ARRAY_SIZE(can1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static const char *const can1_grps[] = { "can1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static struct spear_function can1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .name = "can1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .groups = can1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .ngroups = ARRAY_SIZE(can1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* Pad multiplexing for PWM0_1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .mask = PMX_SSP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .mask = PMX_PL_8_9_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .val = PMX_PWM_0_1_PL_8_9_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static struct spear_muxreg pwm0_1_net_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .mask = PMX_PL_37_38_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .val = PMX_PWM0_1_PL_37_38_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .val = PMX_PWM1_PL_42_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) PMX_PWM0_PL_43_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .reg = IP_SEL_PAD_50_59_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .mask = PMX_PL_59_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .val = PMX_PWM1_PL_59_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .reg = IP_SEL_PAD_60_69_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .mask = PMX_PL_60_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .val = PMX_PWM0_PL_60_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .reg = IP_SEL_PAD_80_89_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .mask = PMX_PL_88_89_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .val = PMX_PWM0_1_PL_88_89_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .muxregs = pwm0_1_pin_8_9_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .muxregs = pwm0_1_autoexpsmallpri_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .muxregs = pwm0_1_pin_14_15_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .muxregs = pwm0_1_pin_30_31_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .muxregs = pwm0_1_net_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .muxregs = pwm0_1_pin_37_38_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .muxregs = pwm0_1_pin_42_43_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .muxregs = pwm0_1_pin_59_60_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .muxregs = pwm0_1_pin_88_89_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) static struct spear_pingroup pwm0_1_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .name = "pwm0_1_pin_8_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .pins = pwm0_1_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .npins = ARRAY_SIZE(pwm0_1_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .modemuxs = pwm0_1_pin_8_9_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .name = "pwm0_1_pin_14_15_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .pins = pwm0_1_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .npins = ARRAY_SIZE(pwm0_1_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .modemuxs = pwm0_1_pin_14_15_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .name = "pwm0_1_pin_30_31_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .pins = pwm0_1_pins[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .npins = ARRAY_SIZE(pwm0_1_pins[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .modemuxs = pwm0_1_pin_30_31_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .name = "pwm0_1_pin_37_38_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .pins = pwm0_1_pins[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .npins = ARRAY_SIZE(pwm0_1_pins[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .modemuxs = pwm0_1_pin_37_38_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .name = "pwm0_1_pin_42_43_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .pins = pwm0_1_pins[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .npins = ARRAY_SIZE(pwm0_1_pins[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .modemuxs = pwm0_1_pin_42_43_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .name = "pwm0_1_pin_59_60_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .pins = pwm0_1_pins[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .npins = ARRAY_SIZE(pwm0_1_pins[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .modemuxs = pwm0_1_pin_59_60_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .name = "pwm0_1_pin_88_89_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .pins = pwm0_1_pins[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .npins = ARRAY_SIZE(pwm0_1_pins[6]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .modemuxs = pwm0_1_pin_88_89_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) static struct spear_function pwm0_1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .name = "pwm0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .groups = pwm0_1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .ngroups = ARRAY_SIZE(pwm0_1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) /* Pad multiplexing for PWM2 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) { 58 }, { 87 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) static struct spear_muxreg pwm2_net_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .mask = PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) static struct spear_muxreg pwm2_pin_7_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .mask = PMX_PL_7_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .val = PMX_PWM_2_PL_7_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static struct spear_muxreg pwm2_pin_13_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .mask = PMX_PL_13_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .val = PMX_PWM2_PL_13_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static struct spear_muxreg pwm2_pin_29_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .mask = PMX_GPIO_PIN1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .reg = IP_SEL_PAD_20_29_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .mask = PMX_PL_29_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .val = PMX_PWM_2_PL_29_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) static struct spear_muxreg pwm2_pin_34_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .mask = PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .mask = PMX_PWM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .val = PMX_PWM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .mask = PMX_PL_34_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .val = PMX_PWM2_PL_34_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) static struct spear_muxreg pwm2_pin_41_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .mask = PMX_PL_41_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .val = PMX_PWM2_PL_41_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) static struct spear_muxreg pwm2_pin_58_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .reg = IP_SEL_PAD_50_59_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .mask = PMX_PL_58_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .val = PMX_PWM2_PL_58_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) static struct spear_muxreg pwm2_pin_87_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .reg = IP_SEL_PAD_80_89_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .mask = PMX_PL_87_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .val = PMX_PWM2_PL_87_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static struct spear_modemux pwm2_pin_7_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .muxregs = pwm2_net_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .muxregs = pwm2_pin_7_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) static struct spear_modemux pwm2_pin_13_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .muxregs = pwm2_autoexpsmallpri_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .muxregs = pwm2_pin_13_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static struct spear_modemux pwm2_pin_29_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .muxregs = pwm2_pin_29_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static struct spear_modemux pwm2_pin_34_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .muxregs = pwm2_pin_34_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static struct spear_modemux pwm2_pin_41_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .muxregs = pwm2_pin_41_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) static struct spear_modemux pwm2_pin_58_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .muxregs = pwm2_pin_58_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) static struct spear_modemux pwm2_pin_87_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .muxregs = pwm2_pin_87_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) static struct spear_pingroup pwm2_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .name = "pwm2_pin_7_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .pins = pwm2_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .npins = ARRAY_SIZE(pwm2_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .modemuxs = pwm2_pin_7_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .name = "pwm2_pin_13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .pins = pwm2_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .npins = ARRAY_SIZE(pwm2_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .modemuxs = pwm2_pin_13_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .name = "pwm2_pin_29_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .pins = pwm2_pins[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .npins = ARRAY_SIZE(pwm2_pins[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .modemuxs = pwm2_pin_29_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .name = "pwm2_pin_34_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .pins = pwm2_pins[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .npins = ARRAY_SIZE(pwm2_pins[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .modemuxs = pwm2_pin_34_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .name = "pwm2_pin_41_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .pins = pwm2_pins[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .npins = ARRAY_SIZE(pwm2_pins[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .modemuxs = pwm2_pin_41_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .name = "pwm2_pin_58_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .pins = pwm2_pins[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .npins = ARRAY_SIZE(pwm2_pins[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .modemuxs = pwm2_pin_58_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .name = "pwm2_pin_87_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .pins = pwm2_pins[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .npins = ARRAY_SIZE(pwm2_pins[6]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .modemuxs = pwm2_pin_87_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) static struct spear_function pwm2_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .name = "pwm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .groups = pwm2_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .ngroups = ARRAY_SIZE(pwm2_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) /* Pad multiplexing for PWM3 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) { 86 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) static struct spear_muxreg pwm3_pin_6_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .mask = PMX_SSP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .mask = PMX_PL_6_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .val = PMX_PWM_3_PL_6_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static struct spear_muxreg pwm3_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) static struct spear_muxreg pwm3_pin_12_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .mask = PMX_PL_12_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .val = PMX_PWM3_PL_12_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) static struct spear_muxreg pwm3_pin_28_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .mask = PMX_GPIO_PIN0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .reg = IP_SEL_PAD_20_29_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .mask = PMX_PL_28_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .val = PMX_PWM_3_PL_28_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) static struct spear_muxreg pwm3_pin_40_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .mask = PMX_PL_40_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .val = PMX_PWM3_PL_40_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static struct spear_muxreg pwm3_pin_57_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .reg = IP_SEL_PAD_50_59_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .mask = PMX_PL_57_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .val = PMX_PWM3_PL_57_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) static struct spear_muxreg pwm3_pin_86_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .reg = IP_SEL_PAD_80_89_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .mask = PMX_PL_86_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .val = PMX_PWM3_PL_86_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static struct spear_modemux pwm3_pin_6_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .muxregs = pwm3_pin_6_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) static struct spear_modemux pwm3_pin_12_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) AUTO_NET_SMII_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .muxregs = pwm3_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .muxregs = pwm3_pin_12_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static struct spear_modemux pwm3_pin_28_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .muxregs = pwm3_pin_28_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static struct spear_modemux pwm3_pin_40_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .muxregs = pwm3_pin_40_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static struct spear_modemux pwm3_pin_57_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .muxregs = pwm3_pin_57_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) static struct spear_modemux pwm3_pin_86_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .muxregs = pwm3_pin_86_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) static struct spear_pingroup pwm3_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .name = "pwm3_pin_6_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .pins = pwm3_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .npins = ARRAY_SIZE(pwm3_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .modemuxs = pwm3_pin_6_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .name = "pwm3_pin_12_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .pins = pwm3_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .npins = ARRAY_SIZE(pwm3_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .modemuxs = pwm3_pin_12_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .name = "pwm3_pin_28_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .pins = pwm3_pins[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .npins = ARRAY_SIZE(pwm3_pins[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .modemuxs = pwm3_pin_28_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .name = "pwm3_pin_40_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .pins = pwm3_pins[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .npins = ARRAY_SIZE(pwm3_pins[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .modemuxs = pwm3_pin_40_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .name = "pwm3_pin_57_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .pins = pwm3_pins[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .npins = ARRAY_SIZE(pwm3_pins[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .modemuxs = pwm3_pin_57_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .name = "pwm3_pin_86_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .pins = pwm3_pins[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .npins = ARRAY_SIZE(pwm3_pins[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .modemuxs = pwm3_pin_86_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) "pwm3_pin_86_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static struct spear_function pwm3_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .name = "pwm3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .groups = pwm3_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .ngroups = ARRAY_SIZE(pwm3_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) /* Pad multiplexing for SSP1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) { 65, 68 }, { 94, 97 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) static struct spear_muxreg ssp1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) .val = PMX_SSP1_PL_17_18_19_20_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .reg = IP_SEL_PAD_20_29_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .mask = PMX_PL_20_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .val = PMX_SSP1_PL_17_18_19_20_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .mask = PMX_SSP1_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .val = PMX_SSP1_PORT_17_TO_20_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) PMX_SSP1_PL_39_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .mask = PMX_SSP1_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .val = PMX_SSP1_PORT_36_TO_39_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .mask = PMX_PL_48_49_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .val = PMX_SSP1_PL_48_49_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .reg = IP_SEL_PAD_50_59_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .mask = PMX_PL_50_51_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .val = PMX_SSP1_PL_50_51_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .mask = PMX_SSP1_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .val = PMX_SSP1_PORT_48_TO_51_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .reg = IP_SEL_PAD_60_69_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .mask = PMX_PL_65_TO_68_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .val = PMX_SSP1_PL_65_TO_68_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .mask = PMX_SSP1_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .val = PMX_SSP1_PORT_65_TO_68_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .mask = PMX_SSP1_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .val = PMX_SSP1_PORT_94_TO_97_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) static struct spear_modemux ssp1_17_20_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .muxregs = ssp1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .muxregs = ssp1_ext_17_20_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) static struct spear_modemux ssp1_36_39_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .muxregs = ssp1_ext_36_39_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) static struct spear_modemux ssp1_48_51_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .muxregs = ssp1_ext_48_51_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) static struct spear_modemux ssp1_65_68_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .muxregs = ssp1_ext_65_68_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) static struct spear_modemux ssp1_94_97_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .muxregs = ssp1_ext_94_97_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static struct spear_pingroup ssp1_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .name = "ssp1_17_20_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .pins = ssp1_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .npins = ARRAY_SIZE(ssp1_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .modemuxs = ssp1_17_20_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .name = "ssp1_36_39_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .pins = ssp1_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .npins = ARRAY_SIZE(ssp1_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .modemuxs = ssp1_36_39_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .name = "ssp1_48_51_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .pins = ssp1_pins[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .npins = ARRAY_SIZE(ssp1_pins[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .modemuxs = ssp1_48_51_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .name = "ssp1_65_68_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .pins = ssp1_pins[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .npins = ARRAY_SIZE(ssp1_pins[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .modemuxs = ssp1_65_68_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .name = "ssp1_94_97_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .pins = ssp1_pins[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .npins = ARRAY_SIZE(ssp1_pins[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .modemuxs = ssp1_94_97_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) static struct spear_function ssp1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .name = "ssp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .groups = ssp1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .ngroups = ARRAY_SIZE(ssp1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) /* Pad multiplexing for SSP2 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) { 61, 64 }, { 90, 93 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) static struct spear_muxreg ssp2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .val = PMX_SSP2_PL_13_14_15_16_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) .mask = PMX_SSP2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .val = PMX_SSP2_PORT_13_TO_16_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) PMX_GPIO_PIN5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .reg = IP_SEL_PAD_30_39_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) PMX_SSP2_PL_35_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .mask = PMX_SSP2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) .val = PMX_SSP2_PORT_32_TO_35_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .reg = IP_SEL_PAD_40_49_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .mask = PMX_SSP2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .val = PMX_SSP2_PORT_44_TO_47_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .reg = IP_SEL_PAD_60_69_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .mask = PMX_PL_61_TO_64_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) .val = PMX_SSP2_PL_61_TO_64_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .mask = PMX_SSP2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .val = PMX_SSP2_PORT_61_TO_64_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .mask = PMX_SSP2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .val = PMX_SSP2_PORT_90_TO_93_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) static struct spear_modemux ssp2_13_16_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .muxregs = ssp2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .muxregs = ssp2_ext_13_16_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static struct spear_modemux ssp2_32_35_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .muxregs = ssp2_ext_32_35_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) static struct spear_modemux ssp2_44_47_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .muxregs = ssp2_ext_44_47_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static struct spear_modemux ssp2_61_64_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .muxregs = ssp2_ext_61_64_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) static struct spear_modemux ssp2_90_93_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .muxregs = ssp2_ext_90_93_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) static struct spear_pingroup ssp2_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .name = "ssp2_13_16_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .pins = ssp2_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .npins = ARRAY_SIZE(ssp2_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .modemuxs = ssp2_13_16_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .name = "ssp2_32_35_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) .pins = ssp2_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .npins = ARRAY_SIZE(ssp2_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .modemuxs = ssp2_32_35_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .name = "ssp2_44_47_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .pins = ssp2_pins[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .npins = ARRAY_SIZE(ssp2_pins[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .modemuxs = ssp2_44_47_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .name = "ssp2_61_64_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .pins = ssp2_pins[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .npins = ARRAY_SIZE(ssp2_pins[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .modemuxs = ssp2_61_64_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) .name = "ssp2_90_93_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) .pins = ssp2_pins[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) .npins = ARRAY_SIZE(ssp2_pins[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .modemuxs = ssp2_90_93_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) static struct spear_function ssp2_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .name = "ssp2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .groups = ssp2_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .ngroups = ARRAY_SIZE(ssp2_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) /* Pad multiplexing for cadence mii2 as mii device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) 90, 91, 92, 93, 94, 95, 96, 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) static struct spear_muxreg mii2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .reg = IP_SEL_PAD_80_89_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) PMX_PL_88_89_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) PMX_MII2_PL_88_89_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) .reg = EXT_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) MII_MDIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) (MAC_MODE_MII << MAC1_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) MII_MDIO_81_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) static struct spear_modemux mii2_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) .muxregs = mii2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) .nmuxregs = ARRAY_SIZE(mii2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static struct spear_pingroup mii2_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) .name = "mii2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) .pins = mii2_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .npins = ARRAY_SIZE(mii2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .modemuxs = mii2_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .nmodemuxs = ARRAY_SIZE(mii2_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) static const char *const mii2_grps[] = { "mii2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) static struct spear_function mii2_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) .name = "mii2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) .groups = mii2_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .ngroups = ARRAY_SIZE(mii2_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) /* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) 21, 22, 23, 24, 25, 26, 27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) static struct spear_muxreg mii0_1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) static struct spear_muxreg smii0_1_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .mask = PMX_PL_10_11_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .val = PMX_SMII_PL_10_11_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .reg = IP_SEL_PAD_20_29_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .mask = PMX_PL_21_TO_27_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) .val = PMX_SMII_PL_21_TO_27_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) .reg = EXT_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) MII_MDIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) | MII_MDIO_10_11_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static struct spear_muxreg rmii0_1_ext_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) PMX_RMII_PL_19_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .reg = IP_SEL_PAD_20_29_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .reg = EXT_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) MII_MDIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) | MII_MDIO_10_11_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) static struct spear_modemux mii0_1_modemux[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) /* configure as smii */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) SMALL_PRINTERS_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .muxregs = mii0_1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) .muxregs = smii0_1_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) /* configure as rmii */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) SMALL_PRINTERS_MODE | EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .muxregs = mii0_1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) .muxregs = rmii0_1_ext_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) static struct spear_pingroup mii0_1_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .name = "smii0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .pins = smii0_1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .npins = ARRAY_SIZE(smii0_1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .modemuxs = mii0_1_modemux[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) .name = "rmii0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .pins = rmii0_1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .npins = ARRAY_SIZE(rmii0_1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .modemuxs = mii0_1_modemux[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) static struct spear_function mii0_1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) .name = "mii0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) .groups = mii0_1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) .ngroups = ARRAY_SIZE(mii0_1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) /* Pad multiplexing for i2c1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) .mask = PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) .mask = PMX_PL_8_9_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) .val = PMX_I2C1_PL_8_9_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) .mask = PMX_I2C1_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) .val = PMX_I2C1_PORT_8_9_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) .mask = PMX_I2C1_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) .val = PMX_I2C1_PORT_98_99_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) static struct spear_modemux i2c1_modemux[][1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) /* Select signals on pins 8-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) .muxregs = i2c1_ext_8_9_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) /* Select signals on pins 98-99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) .muxregs = i2c1_ext_98_99_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) static struct spear_pingroup i2c1_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) .name = "i2c1_8_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) .pins = i2c1_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) .npins = ARRAY_SIZE(i2c1_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) .modemuxs = i2c1_modemux[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) .name = "i2c1_98_99_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) .pins = i2c1_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) .npins = ARRAY_SIZE(i2c1_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) .modemuxs = i2c1_modemux[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) static struct spear_function i2c1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) .name = "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) .groups = i2c1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) .ngroups = ARRAY_SIZE(i2c1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) /* Pad multiplexing for i2c2 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) { 75, 76 }, { 96, 97 } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) .mask = PMX_FIRDA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) .mask = PMX_PL_0_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) .val = PMX_I2C2_PL_0_1_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) .mask = PMX_I2C2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) .val = PMX_I2C2_PORT_0_1_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) .mask = PMX_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) .reg = IP_SEL_PAD_0_9_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) .mask = PMX_PL_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) .val = PMX_I2C2_PL_2_3_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) .mask = PMX_I2C2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) .val = PMX_I2C2_PORT_2_3_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) .reg = IP_SEL_PAD_10_19_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) .mask = PMX_PL_19_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) .val = PMX_I2C2_PL_19_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) .reg = IP_SEL_PAD_20_29_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) .mask = PMX_PL_20_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) .val = PMX_I2C2_PL_20_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) .mask = PMX_I2C2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) .val = PMX_I2C2_PORT_19_20_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) .reg = IP_SEL_PAD_70_79_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) .mask = PMX_PL_75_76_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) .val = PMX_I2C2_PL_75_76_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) .mask = PMX_I2C2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) .val = PMX_I2C2_PORT_75_76_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) .reg = IP_SEL_PAD_90_99_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) .mask = PMX_PL_96_97_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) .val = PMX_I2C2_PL_96_97_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) .reg = IP_SEL_MIX_PAD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) .mask = PMX_I2C2_PORT_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) .val = PMX_I2C2_PORT_96_97_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) static struct spear_modemux i2c2_modemux[][1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) /* Select signals on pins 0_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) .muxregs = i2c2_ext_0_1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) /* Select signals on pins 2_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) .muxregs = i2c2_ext_2_3_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) /* Select signals on pins 19_20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) .muxregs = i2c2_ext_19_20_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) /* Select signals on pins 75_76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) .muxregs = i2c2_ext_75_76_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) /* Select signals on pins 96_97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) .modes = EXTENDED_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) .muxregs = i2c2_ext_96_97_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) static struct spear_pingroup i2c2_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) .name = "i2c2_0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) .pins = i2c2_pins[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) .npins = ARRAY_SIZE(i2c2_pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) .modemuxs = i2c2_modemux[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) .name = "i2c2_2_3_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) .pins = i2c2_pins[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) .npins = ARRAY_SIZE(i2c2_pins[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .modemuxs = i2c2_modemux[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) .name = "i2c2_19_20_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) .pins = i2c2_pins[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) .npins = ARRAY_SIZE(i2c2_pins[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) .modemuxs = i2c2_modemux[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) .name = "i2c2_75_76_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) .pins = i2c2_pins[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) .npins = ARRAY_SIZE(i2c2_pins[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) .modemuxs = i2c2_modemux[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) .name = "i2c2_96_97_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) .pins = i2c2_pins[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) .npins = ARRAY_SIZE(i2c2_pins[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) .modemuxs = i2c2_modemux[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) static struct spear_function i2c2_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) .name = "i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) .groups = i2c2_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) .ngroups = ARRAY_SIZE(i2c2_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) /* pingroups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) static struct spear_pingroup *spear320_pingroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) SPEAR3XX_COMMON_PINGROUPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) &clcd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) &emi_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) &fsmc_8bit_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) &fsmc_16bit_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) &spp_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) &sdhci_led_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) &sdhci_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) &sdhci_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) &i2s_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) &uart1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) &uart1_modem_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) &uart1_modem_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) &uart1_modem_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) &uart1_modem_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) &uart2_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) &uart3_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) &uart3_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) &uart3_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) &uart3_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) &uart3_pingroup[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) &uart3_pingroup[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) &uart3_pingroup[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) &uart4_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) &uart4_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) &uart4_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) &uart4_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) &uart4_pingroup[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) &uart4_pingroup[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) &uart5_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) &uart5_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) &uart5_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) &uart5_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) &uart6_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) &uart6_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) &rs485_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) &touchscreen_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) &can0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) &can1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) &pwm0_1_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) &pwm0_1_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) &pwm0_1_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) &pwm0_1_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) &pwm0_1_pingroup[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) &pwm0_1_pingroup[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) &pwm0_1_pingroup[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) &pwm2_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) &pwm2_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) &pwm2_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) &pwm2_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) &pwm2_pingroup[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) &pwm2_pingroup[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) &pwm2_pingroup[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) &pwm3_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) &pwm3_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) &pwm3_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) &pwm3_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) &pwm3_pingroup[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) &pwm3_pingroup[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) &ssp1_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) &ssp1_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) &ssp1_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) &ssp1_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) &ssp1_pingroup[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) &ssp2_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) &ssp2_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) &ssp2_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) &ssp2_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) &ssp2_pingroup[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) &mii2_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) &mii0_1_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) &mii0_1_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) &i2c1_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) &i2c1_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) &i2c2_pingroup[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) &i2c2_pingroup[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) &i2c2_pingroup[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) &i2c2_pingroup[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) &i2c2_pingroup[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) /* functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) static struct spear_function *spear320_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) SPEAR3XX_COMMON_FUNCTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) &clcd_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) &emi_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) &fsmc_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) &spp_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) &sdhci_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) &i2s_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) &uart1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) &uart1_modem_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) &uart2_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) &uart3_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) &uart4_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) &uart5_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) &uart6_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) &rs485_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) &touchscreen_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) &can0_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) &can1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) &pwm0_1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) &pwm2_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) &pwm3_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) &ssp1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) &ssp2_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) &mii2_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) &mii0_1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) &i2c1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) &i2c2_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) static const struct of_device_id spear320_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) .compatible = "st,spear320-pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) static int spear320_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) spear3xx_machdata.groups = spear320_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) spear3xx_machdata.functions = spear320_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) spear3xx_machdata.modes_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) spear3xx_machdata.pmx_modes = spear320_pmx_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) return spear_pinctrl_probe(pdev, &spear3xx_machdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) static struct platform_driver spear320_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) .of_match_table = spear320_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) .probe = spear320_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) static int __init spear320_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) return platform_driver_register(&spear320_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) arch_initcall(spear320_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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