^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the ST Microelectronics SPEAr310 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-spear3xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRIVER_NAME "spear310-pinmux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PMX_CONFIG_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* emi_cs_0_to_5_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct spear_modemux emi_cs_0_to_5_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .muxregs = emi_cs_0_to_5_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct spear_pingroup emi_cs_0_to_5_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = "emi_cs_0_to_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .pins = emi_cs_0_to_5_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .modemuxs = emi_cs_0_to_5_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct spear_function emi_cs_0_to_5_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = "emi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .groups = emi_cs_0_to_5_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* uart1_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const unsigned uart1_pins[] = { 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct spear_muxreg uart1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .mask = PMX_FIRDA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct spear_modemux uart1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .muxregs = uart1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .nmuxregs = ARRAY_SIZE(uart1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct spear_pingroup uart1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .name = "uart1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .pins = uart1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .npins = ARRAY_SIZE(uart1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .modemuxs = uart1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .nmodemuxs = ARRAY_SIZE(uart1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const char *const uart1_grps[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct spear_function uart1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .groups = uart1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .ngroups = ARRAY_SIZE(uart1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* uart2_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const unsigned uart2_pins[] = { 43, 44 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct spear_muxreg uart2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .mask = PMX_TIMER_0_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct spear_modemux uart2_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .muxregs = uart2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .nmuxregs = ARRAY_SIZE(uart2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct spear_pingroup uart2_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .name = "uart2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .pins = uart2_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .npins = ARRAY_SIZE(uart2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .modemuxs = uart2_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .nmodemuxs = ARRAY_SIZE(uart2_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const char *const uart2_grps[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct spear_function uart2_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "uart2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .groups = uart2_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .ngroups = ARRAY_SIZE(uart2_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* uart3_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const unsigned uart3_pins[] = { 37, 38 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct spear_muxreg uart3_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct spear_modemux uart3_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .muxregs = uart3_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .nmuxregs = ARRAY_SIZE(uart3_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct spear_pingroup uart3_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "uart3_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .pins = uart3_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .npins = ARRAY_SIZE(uart3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .modemuxs = uart3_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .nmodemuxs = ARRAY_SIZE(uart3_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const char *const uart3_grps[] = { "uart3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct spear_function uart3_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "uart3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .groups = uart3_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .ngroups = ARRAY_SIZE(uart3_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* uart4_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const unsigned uart4_pins[] = { 39, 40 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct spear_muxreg uart4_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct spear_modemux uart4_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .muxregs = uart4_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .nmuxregs = ARRAY_SIZE(uart4_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct spear_pingroup uart4_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "uart4_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .pins = uart4_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .npins = ARRAY_SIZE(uart4_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .modemuxs = uart4_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .nmodemuxs = ARRAY_SIZE(uart4_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const char *const uart4_grps[] = { "uart4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct spear_function uart4_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "uart4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .groups = uart4_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .ngroups = ARRAY_SIZE(uart4_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* uart5_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const unsigned uart5_pins[] = { 41, 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct spear_muxreg uart5_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct spear_modemux uart5_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .muxregs = uart5_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .nmuxregs = ARRAY_SIZE(uart5_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct spear_pingroup uart5_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .name = "uart5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .pins = uart5_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .npins = ARRAY_SIZE(uart5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .modemuxs = uart5_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .nmodemuxs = ARRAY_SIZE(uart5_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const char *const uart5_grps[] = { "uart5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct spear_function uart5_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "uart5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .groups = uart5_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .ngroups = ARRAY_SIZE(uart5_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* fsmc_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const unsigned fsmc_pins[] = { 34, 35, 36 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct spear_muxreg fsmc_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .mask = PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct spear_modemux fsmc_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .muxregs = fsmc_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct spear_pingroup fsmc_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .name = "fsmc_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .pins = fsmc_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .npins = ARRAY_SIZE(fsmc_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .modemuxs = fsmc_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const char *const fsmc_grps[] = { "fsmc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct spear_function fsmc_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "fsmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .groups = fsmc_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .ngroups = ARRAY_SIZE(fsmc_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* rs485_0_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct spear_muxreg rs485_0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct spear_modemux rs485_0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .muxregs = rs485_0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static struct spear_pingroup rs485_0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .name = "rs485_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .pins = rs485_0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .npins = ARRAY_SIZE(rs485_0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .modemuxs = rs485_0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const char *const rs485_0_grps[] = { "rs485_0" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static struct spear_function rs485_0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .name = "rs485_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .groups = rs485_0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .ngroups = ARRAY_SIZE(rs485_0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* rs485_1_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static struct spear_muxreg rs485_1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct spear_modemux rs485_1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .muxregs = rs485_1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct spear_pingroup rs485_1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = "rs485_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .pins = rs485_1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .npins = ARRAY_SIZE(rs485_1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .modemuxs = rs485_1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const char *const rs485_1_grps[] = { "rs485_1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct spear_function rs485_1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = "rs485_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .groups = rs485_1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .ngroups = ARRAY_SIZE(rs485_1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* tdm_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct spear_muxreg tdm_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct spear_modemux tdm_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .muxregs = tdm_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .nmuxregs = ARRAY_SIZE(tdm_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct spear_pingroup tdm_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .name = "tdm_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .pins = tdm_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .npins = ARRAY_SIZE(tdm_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .modemuxs = tdm_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .nmodemuxs = ARRAY_SIZE(tdm_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const char *const tdm_grps[] = { "tdm_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct spear_function tdm_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .name = "tdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .groups = tdm_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .ngroups = ARRAY_SIZE(tdm_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* pingroups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct spear_pingroup *spear310_pingroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SPEAR3XX_COMMON_PINGROUPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) &emi_cs_0_to_5_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) &uart1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &uart2_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &uart3_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) &uart4_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) &uart5_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) &fsmc_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) &rs485_0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) &rs485_1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) &tdm_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct spear_function *spear310_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SPEAR3XX_COMMON_FUNCTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) &emi_cs_0_to_5_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &uart1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) &uart2_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) &uart3_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) &uart4_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) &uart5_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) &fsmc_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) &rs485_0_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) &rs485_1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) &tdm_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct of_device_id spear310_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .compatible = "st,spear310-pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int spear310_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) spear3xx_machdata.groups = spear310_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spear3xx_machdata.functions = spear310_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) spear3xx_machdata.modes_supported = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return spear_pinctrl_probe(pdev, &spear3xx_machdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct platform_driver spear310_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .of_match_table = spear310_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .probe = spear310_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int __init spear310_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return platform_driver_register(&spear310_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) arch_initcall(spear310_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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