^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the ST Microelectronics SPEAr300 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-spear3xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRIVER_NAME "spear300-pinmux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PMX_CONFIG_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MODE_CONFIG_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NAND_MODE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NOR_MODE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PHOTO_FRAME_MODE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LEND_IP_PHONE_MODE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HEND_IP_PHONE_MODE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LEND_WIFI_PHONE_MODE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HEND_WIFI_PHONE_MODE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ATA_PABX_WI2S_MODE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ATA_PABX_I2S_MODE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CAML_LCDW_MODE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CAMU_LCD_MODE (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CAMU_WLCD_MODE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CAML_LCD_MODE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct spear_pmx_mode pmx_mode_nand = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .name = "nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .mode = NAND_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .val = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static struct spear_pmx_mode pmx_mode_nor = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .name = "nor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .mode = NOR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .val = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct spear_pmx_mode pmx_mode_photo_frame = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .name = "photo frame mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .mode = PHOTO_FRAME_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .val = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = "lend ip phone mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .mode = LEND_IP_PHONE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .val = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = "hend ip phone mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .mode = HEND_IP_PHONE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .val = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "lend wifi phone mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .mode = LEND_WIFI_PHONE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .val = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "hend wifi phone mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .mode = HEND_WIFI_PHONE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .val = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "ata pabx wi2s mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .mode = ATA_PABX_WI2S_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .val = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .name = "ata pabx i2s mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .mode = ATA_PABX_I2S_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .val = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct spear_pmx_mode pmx_mode_caml_lcdw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .name = "caml lcdw mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .mode = CAML_LCDW_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .val = 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct spear_pmx_mode pmx_mode_camu_lcd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .name = "camu lcd mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .mode = CAMU_LCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .val = 0x0D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct spear_pmx_mode pmx_mode_camu_wlcd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "camu wlcd mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .mode = CAMU_WLCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .val = 0xE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct spear_pmx_mode pmx_mode_caml_lcd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .name = "caml lcd mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .mode = CAML_LCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .reg = MODE_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .mask = 0x0000000F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .val = 0x0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct spear_pmx_mode *spear300_pmx_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &pmx_mode_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &pmx_mode_nor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &pmx_mode_photo_frame,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) &pmx_mode_lend_ip_phone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) &pmx_mode_hend_ip_phone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) &pmx_mode_lend_wifi_phone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) &pmx_mode_hend_wifi_phone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) &pmx_mode_ata_pabx_wi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) &pmx_mode_ata_pabx_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) &pmx_mode_caml_lcdw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) &pmx_mode_camu_lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) &pmx_mode_camu_wlcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) &pmx_mode_caml_lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* fsmc_2chips_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const unsigned fsmc_2chips_pins[] = { 1, 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct spear_muxreg fsmc_2chips_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .mask = PMX_FIRDA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct spear_modemux fsmc_2chips_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .muxregs = fsmc_2chips_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct spear_pingroup fsmc_2chips_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .name = "fsmc_2chips_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .pins = fsmc_2chips_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .npins = ARRAY_SIZE(fsmc_2chips_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .modemuxs = fsmc_2chips_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* fsmc_4chips_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct spear_muxreg fsmc_4chips_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct spear_modemux fsmc_4chips_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .muxregs = fsmc_4chips_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct spear_pingroup fsmc_4chips_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .name = "fsmc_4chips_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .pins = fsmc_4chips_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .npins = ARRAY_SIZE(fsmc_4chips_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .modemuxs = fsmc_4chips_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct spear_function fsmc_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "fsmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .groups = fsmc_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .ngroups = ARRAY_SIZE(fsmc_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* clcd_lcdmode_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct spear_muxreg clcd_lcdmode_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct spear_modemux clcd_lcdmode_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CAMU_LCD_MODE | CAML_LCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .muxregs = clcd_lcdmode_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct spear_pingroup clcd_lcdmode_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "clcd_lcdmode_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .pins = clcd_lcdmode_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .npins = ARRAY_SIZE(clcd_lcdmode_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .modemuxs = clcd_lcdmode_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* clcd_pfmode_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct spear_muxreg clcd_pfmode_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .mask = PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct spear_modemux clcd_pfmode_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .modes = PHOTO_FRAME_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .muxregs = clcd_pfmode_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct spear_pingroup clcd_pfmode_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = "clcd_pfmode_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .pins = clcd_pfmode_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .npins = ARRAY_SIZE(clcd_pfmode_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .modemuxs = clcd_pfmode_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct spear_function clcd_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "clcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .groups = clcd_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .ngroups = ARRAY_SIZE(clcd_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* tdm_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct spear_muxreg tdm_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct spear_modemux tdm_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) | CAMU_WLCD_MODE | CAML_LCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .muxregs = tdm_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .nmuxregs = ARRAY_SIZE(tdm_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct spear_pingroup tdm_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .name = "tdm_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .pins = tdm_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .npins = ARRAY_SIZE(tdm_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .modemuxs = tdm_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .nmodemuxs = ARRAY_SIZE(tdm_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const char *const tdm_grps[] = { "tdm_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct spear_function tdm_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "tdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .groups = tdm_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .ngroups = ARRAY_SIZE(tdm_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* i2c_clk_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct spear_muxreg i2c_clk_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct spear_modemux i2c_clk_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) | CAML_LCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .muxregs = i2c_clk_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static struct spear_pingroup i2c_clk_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .name = "i2c_clk_grp_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .pins = i2c_clk_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .npins = ARRAY_SIZE(i2c_clk_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .modemuxs = i2c_clk_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const char *const i2c_grps[] = { "i2c_clk_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct spear_function i2c_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .groups = i2c_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .ngroups = ARRAY_SIZE(i2c_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* caml_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct spear_muxreg caml_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .mask = PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct spear_modemux caml_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .muxregs = caml_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .nmuxregs = ARRAY_SIZE(caml_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct spear_pingroup caml_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .name = "caml_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .pins = caml_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .npins = ARRAY_SIZE(caml_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .modemuxs = caml_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .nmodemuxs = ARRAY_SIZE(caml_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* camu_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct spear_muxreg camu_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct spear_modemux camu_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .muxregs = camu_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .nmuxregs = ARRAY_SIZE(camu_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static struct spear_pingroup camu_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .name = "camu_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .pins = camu_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .npins = ARRAY_SIZE(camu_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .modemuxs = camu_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .nmodemuxs = ARRAY_SIZE(camu_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct spear_function cam_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .name = "cam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .groups = cam_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .ngroups = ARRAY_SIZE(cam_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* dac_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const unsigned dac_pins[] = { 43, 44 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct spear_muxreg dac_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .mask = PMX_TIMER_0_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static struct spear_modemux dac_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) | CAMU_WLCD_MODE | CAML_LCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .muxregs = dac_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .nmuxregs = ARRAY_SIZE(dac_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct spear_pingroup dac_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .name = "dac_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .pins = dac_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .npins = ARRAY_SIZE(dac_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .modemuxs = dac_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .nmodemuxs = ARRAY_SIZE(dac_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const char *const dac_grps[] = { "dac_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct spear_function dac_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = "dac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .groups = dac_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .ngroups = ARRAY_SIZE(dac_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* i2s_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct spear_muxreg i2s_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static struct spear_modemux i2s_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) | CAMU_WLCD_MODE | CAML_LCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .muxregs = i2s_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .nmuxregs = ARRAY_SIZE(i2s_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct spear_pingroup i2s_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .name = "i2s_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .pins = i2s_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .npins = ARRAY_SIZE(i2s_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .modemuxs = i2s_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .nmodemuxs = ARRAY_SIZE(i2s_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const char *const i2s_grps[] = { "i2s_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct spear_function i2s_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .name = "i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .groups = i2s_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .ngroups = ARRAY_SIZE(i2s_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* sdhci_4bit_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct spear_muxreg sdhci_4bit_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static struct spear_modemux sdhci_4bit_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .muxregs = sdhci_4bit_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static struct spear_pingroup sdhci_4bit_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .name = "sdhci_4bit_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .pins = sdhci_4bit_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .npins = ARRAY_SIZE(sdhci_4bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .modemuxs = sdhci_4bit_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* sdhci_8bit_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 33 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static struct spear_muxreg sdhci_8bit_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static struct spear_modemux sdhci_8bit_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) CAMU_WLCD_MODE | CAML_LCD_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .muxregs = sdhci_8bit_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct spear_pingroup sdhci_8bit_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .name = "sdhci_8bit_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .pins = sdhci_8bit_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .npins = ARRAY_SIZE(sdhci_8bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .modemuxs = sdhci_8bit_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static struct spear_function sdhci_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .name = "sdhci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .groups = sdhci_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .ngroups = ARRAY_SIZE(sdhci_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* gpio1_0_to_3_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct spear_modemux gpio1_0_to_3_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .modes = PHOTO_FRAME_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .muxregs = gpio1_0_to_3_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static struct spear_pingroup gpio1_0_to_3_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .name = "gpio1_0_to_3_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .pins = gpio1_0_to_3_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .modemuxs = gpio1_0_to_3_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* gpio1_4_to_7_pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .reg = PMX_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static struct spear_modemux gpio1_4_to_7_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .modes = PHOTO_FRAME_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .muxregs = gpio1_4_to_7_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static struct spear_pingroup gpio1_4_to_7_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .name = "gpio1_4_to_7_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .pins = gpio1_4_to_7_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .modemuxs = gpio1_4_to_7_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static struct spear_function gpio1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .name = "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .groups = gpio1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .ngroups = ARRAY_SIZE(gpio1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* pingroups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static struct spear_pingroup *spear300_pingroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) SPEAR3XX_COMMON_PINGROUPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) &fsmc_2chips_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) &fsmc_4chips_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) &clcd_lcdmode_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) &clcd_pfmode_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) &tdm_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) &i2c_clk_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) &caml_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) &camu_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) &dac_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) &i2s_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) &sdhci_4bit_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) &sdhci_8bit_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) &gpio1_0_to_3_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &gpio1_4_to_7_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static struct spear_function *spear300_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SPEAR3XX_COMMON_FUNCTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) &fsmc_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) &clcd_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) &tdm_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) &i2c_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) &cam_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) &dac_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &i2s_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) &sdhci_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) &gpio1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const struct of_device_id spear300_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .compatible = "st,spear300-pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int spear300_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) spear3xx_machdata.groups = spear300_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) spear3xx_machdata.functions = spear300_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) spear3xx_machdata.gpio_pingroups = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) spear3xx_machdata.ngpio_pingroups = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) spear3xx_machdata.modes_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) spear3xx_machdata.pmx_modes = spear300_pmx_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static struct platform_driver spear300_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .of_match_table = spear300_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .probe = spear300_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int __init spear300_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return platform_driver_register(&spear300_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) arch_initcall(spear300_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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